KR100767418B1 - Preamble detector for code division multiple access system - Google Patents

Abstract

The present invention relates to a preamble receiver of a code division multiple access system. In particular, an object of the present invention is to use the allocated memory in hardware having limited register and memory sizes without waste. To this end, the present invention includes a data double buffer for storing a plurality of on-time, half-time input signals per reference clock; A multiplexer for alternately selecting and outputting on-time and half-time data stored in the data double buffer for each clock corresponding to a predetermined multiple of a reference clock; A code double buffer for storing a plurality of preamble codes for each reference clock; A round trip delay register for shifting and storing data stored in the code double buffer by one bit every half clock of the multiplexer; A multiplier for multiplying the data output from the multiplexer and the data output from the round trip delay register for each bit; An adder which adds and outputs each bit of data output from the multiplier; And an accumulator configured to add data output from the adder and data stored in the memory for each clock corresponding to a predetermined multiple of the reference clock and store the data in the memory. Therefore, the present invention has the effect of using all of the memory of the hardware without wasting by adjusting the number of signatures that can be received according to the cell radius.

Description

Preamble Receiver for Code Division Multiple Access System {PREAMBLE DETECTOR FOR CODE DIVISION MULTIPLE ACCESS SYSTEM}

1 is a block diagram showing the configuration of an I-channel despreader of one signature detector having a minimum cell radius in a preamble receiver of a code division multiple access system according to the present invention.

** Description of the symbols for the main parts of the drawings **

20, 30: data double buffer 51 ~ 58: multiplexer

60: preamble code 70, 80: code double buffer

100: 128-bit shift register 121 to 128: 8-bit adder

170: memory

The present invention relates to a preamble receiver of a code division multiple access system. More particularly, the present invention relates to a preamble receiver of a code division multiple access system that uses memory allocated in hardware having a limited register and memory size without waste.

A preamble code currently used in a code division multiple access system is a code obtained by spreading a sequence of signatures into a scrambling code, and a preamble receiver receiving the preamble code uses a matched filter and a correlator.

The sequence of signatures to be spread is one, and the spreading is done sequentially per bit of the signature. Thus, the register size required for despreading is the spread PN code length per sequence of bits.

The memory size used in the preamble receiver is related to the cell radius, and once the memory has been set to the maximum cell radius, a large portion of the memory is wasted in the urban area of the small cell radius. However, in the asynchronous IMT 2000 RACH (Random Access Channel) preamble code, 16 signatures exist and the method of spreading signatures is different.

Here, look at the 16 signatures are shown in Table 1 below.

Preamble Signature Value of n 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P ₀ (n) One One One One One One One One One One One One One One One One P ₁ (n) One -One One -One One -One One -One One -One One -One One -One One -One P ₂ (n) One One -One -One One One -One -One One One -One -One One One -One -One P ₃ (n) One -One -One One One -One -One One One -One -One One One -One -One One P ₄ (n) One One One One -One -One -One -One One One One One -One -One -One -One P ₅ (n) One -One One -One -One One -One One One -One One -One -One One -One One P ₆ (n) One One -One -One -One -One One One One One -One -One -One -One One One P ₇ (n) One -One -One One -One One One -One One -One -One One -One One One -One P ₈ (n) One One One One One One One One -One -One -One -One -One -One -One -One P ₉ (n) One -One One -One One -One One -One -One One -One One -One One -One One P ₁₀ (n) One One -One -One One One -One -One -One -One One One -One -One One One P ₁₁ (n) One -One -One One One -One -One One -One One One -One -One One One -One P ₁₂ (n) One One One One -One -One -One -One -One -One -One -One One One One One P ₁₃ (n) One -One One -One -One One -One One -One One -One One One -One One -One P ₁₄ (n) One One -One -One -One -One One One -One -One One One One One -One -One P ₁₅ (n) One -One -One One -One One One -One -One One One -One One -One -One One

In the signature spreading method, since the signature is spread with a 4096-scrambling code having 256 repetitions, the register size required for despreading in the preamble receiver is 4096.

This is expressed as an equation below.

, k=0,1,2,3, ...,4095Preamble Codes:

, k = 0,1,2,3, ..., 4095

, i=0,1, ...,4095Scrambling Code:

, i = 0,1, ..., 4095

, i=0,1, ...,4095signature :

, i = 0,1, ..., 4095

In addition, since 16 signatures are required, the number of memories is required to be 16 times more than that of a conventional code division multiple access system.                         

Thus, in terms of hardware, it takes up a considerable amount of memory.

Accordingly, the present invention has been made in view of the above problems, and the memory and register size, which are the biggest constraints in making the preamble receiver, are adjusted according to the cell radius, thereby eliminating all the registers or the memory. It is an object of the present invention to provide a preamble receiver of a code division multiple access system for use.

The present invention for achieving the above object comprises a data double buffer for storing a plurality of on-time, half-time input signal per reference clock; A multiplexer for alternately selecting and outputting on-time and half-time data stored in the data double buffer for each clock corresponding to a predetermined multiple of a reference clock; A code double buffer for storing a plurality of preamble codes for each reference clock; A round trip delay register for shifting and storing data stored in the code double buffer by one bit every half clock of the multiplexer; A multiplier for multiplying the data output from the multiplexer and the data output from the round trip delay register for each bit; An adder which adds and outputs each bit of data output from the multiplier; And an accumulator configured to add data output from the adder and data stored in the memory for each clock corresponding to a predetermined multiple of the reference clock and store the data in the memory.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

The code used for despreading is the product code of the signature code and the scrambling code and is 4096 in length. In the structure of de-spreading a matched filter suitable for this code, the number of adders increases, resulting in one clock delay.

In order to solve this problem, the present invention uses a method of increasing the clock speed and sharing time when designing the adder.

In the present invention, a chipx8 (1 / (3.84e6 * 8) sec) clock is used, the detection resolution is set to half chip, the minimum cell radius is 5km, and the preamble receiver is designed.

The I-channel despreader of one signature detector with the minimum cell radius is as follows.

FIG. 1 is a block diagram showing the configuration of an I-channel despreader of one signature detector having a minimum cell radius in a preamble receiver of a code division multiple access system according to the present invention. As shown in FIG. A data double buffer (20, 30) for storing time, half-time input signals; a multiplexer (51 to 58) for alternately selecting and outputting on-time and half-time data stored in the data double buffers (20, 30) every chipx8 clock; code double buffers 70 and 80 for storing 16 preamble codes per chipx1 clock; a 16-bit shift register (90) and a 128-bit shift register (100) for shifting and storing data stored in the code double buffers (70, 80) by one bit for each chipx4 clock; A multiplier (111 to 118) for multiplying the data output from the multiplexers (51 to 58) and the data output from the 16-bit shift register (90) for each bit; Adders (121 to 128, 131 to 134, 141, 142 and 150) for adding and outputting each bit of data output from the multipliers (111 to 118); It consists of a 16-bit adder 160 for adding the data output from the adders 121 to 128, 131 to 134, 141, 142 and 150 and the data stored in the memory 170 for each chipx8 clock and storing the data in the memory 170 again. It will be described an embodiment of the present invention.

The data double buffers 20 and 30 store 16 on-time and half-time input signals for each chipx1 clock, and are switched when the 16 chips fill the data double buffers 20 and 30.

At this time, the code double buffers 70 and 80 store the preamble code 60 by one bit for each chipx1 clock and output the preamble code 60 to the 16-bit shift register 90.

The 16-bit shift register 90 and the 128-bit shift register 100 connected in series thereof shift and store data by 1 bit for each chipx4 clock.

Data stored in the data double buffers 20 and 30 are stored in the temporary 16-bit register 40 and on-time data and half-time data are alternately selected by the multiplexers 51 to 58 every chipx8 clock.

Multipliers 111-118 multiply on-time data or half-time data with data stored in the 16-bit shift register 90 every chipx8 clock.

In the I-channel, eight 8-bit adders 121 to 128 add two 7-bit data output from the multipliers 111 to 118 and output them to the four 9-bit adders 131 to 134. The bit adders 131 to 134 add two 8-bit data and output them to the two 10-bit adders 141 and 142. The two 10-bit adders 141 and 142 add two 10-bit data and add 11 bits. Output to the adder 150.

The 16-bit adder 160 adds the 11-bit data output from the 11-bit adder 150 and the 16-bit data stored in the memory every chipx8 clock and stores the 16-bit data in the memory 170.

The memory 170 sequentially increases an address every chipx8 clock and stores 16-bit data input thereto.

The process continues for 32 * 8 = 256 clocks, and the despread values are stored sequentially in memory. In addition, a 128-bit shift register 100 for round trip delay has been used to store 128 chips when the cell radius is 5 km.

After all of the values sequentially despread in the memory 170 are stored, the data of the next data double buffer 20 and 30 and the despread value of the preamble code of the 16-bit shift register 90 are stored in the memory 170. Are stored in the memory 170 again.

The size of the data double buffer 20, 30 used here is 7 (input signal bits) * 16 * 2 (on-time, half-time) * 2 (I, Q channels), and the number of adders is I, Q. Including all the channels, there are 16 8-bit adders, 8 9-bit adders, 4 10-bit adders, 2 11-bit adders, and 2 16-bit adders.

It can be seen that the total number of adders is considerably smaller compared to the number of adders required in the receiver which does not share time, 4096 8-bit adders, 2048 9-bit adders, and so on.

The memory size is 16 (bits) * 128 (round trip delay) * 2 (on-time, half-time) * 2 (I, Q channels).

When the minimum cell radius is 5km, finding 16 signatures requires 16 times more buffers, shift registers, and memory as described above.

Supports {cell radius 10km, 8 signatures}, {cell radius 20km, 4 signatures} {cell radius 40km, 2 signatures} with hardware memory size limited to {5km radius, 16 signatures} It is the core of the present invention.

The preamble receiver supporting {cell radius 10km, 8 signatures} constitutes one detector by pairing two detectors in the preamble receiver supporting {cell radius 5km, 16 signatures}.

The first detector is unchanged, and the second detector has a 10km cell radius, so it looks for 128-255 chips in the round trip delay 0-255 chips. To do this, set all the starting points of the second detector to 128 chips behind the starting point of the first detector.

A preamble receiver supporting {cell radius 20 km, 4 signatures} forms one detector by pairing four detectors in a preamble receiver supporting {cell radius 5 km, 16 signatures}.

The first detector remains unchanged, the second detector has 128 to 255 of the round trip delay 0 to 511 chips, the third to 256 to 383 chips, and the fourth to 384 to 511 chips with a cell radius of 20 km. You will find it.                     

To do this, set all the starting points of the second, third, and fourth detectors to 128, 256, and 384 chips after the first detector.

The preamble receiver supporting {cell radius 40km, two signatures} constitutes one detector by pairing eight detectors in the preamble receiver supporting {cell radius 5km, 16 signatures}.

The first, second, third, and fourth detectors are identical to the preamble receiver's configuration with support for {cell radius 20km, four signatures}, and the fifth detector is 512 of the round trip delay 0-1023 chips with a cell radius of 40km. The sixth detector finds 640 ~ 767 chips, the seventh detector finds 768 ~ 895 chips, and the eighth detector finds 896-1023 chips.

For this purpose, the operation start point of the second, third, fourth, fifth, sixth, seventh, and eighth detectors is 128 chips, 256 chips, 384 chips, 512 chips, 640 chips, 768 chips, 896 chips set back.

The preamble receiver finds a round trip delay by calculating energy values by sequentially squaring the memory values of the I and Q channels after 4096 accumulations are completed during the round trip delay period according to the cell radius.

As described in detail above, the present invention has the effect of using all of the memory of the hardware without wasting by adjusting the number of signatures that can be received according to the cell radius.

In addition, since the number of adders is reduced by using a time sharing method, the overall power consumption is also reduced.

Claims (3)

A data double buffer for storing a plurality of on-time, half-time input signals per reference clock; A multiplexer for alternately selecting and outputting on-time and half-time data stored in the data double buffer for each clock corresponding to a predetermined multiple of a reference clock; A code double buffer for storing a plurality of preamble codes for each reference clock; A round trip delay register for shifting and storing data stored in the code double buffer by one bit every half clock of the multiplexer; A multiplier for multiplying the data output from the multiplexer and the data output from the round trip delay register for each bit; An adder which adds and outputs each bit of data output from the multiplier; And a accumulator configured to add data output from the adder and data stored in the memory for each clock corresponding to a predetermined multiple of a reference clock and store the data in the memory. The preamble receiver of claim 1, wherein the number of bits of the round trip delay register is configured to match the number of chips supporting a minimum cell radius. 2. The memory of claim 1, wherein the memory is designed in proportion to a round trip delay so that when a detector supporting a minimum cell radius supports a predetermined multiple of the minimum cell radius, the predetermined number of signatures supported by the system at the starting point of operation of the detector is determined. A preamble receiver of a code division multiple access system, characterized in that configured to be set at intervals divided by multiples.

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