KR100755133B1 - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

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KR100755133B1
KR100755133B1 KR1020060083897A KR20060083897A KR100755133B1 KR 100755133 B1 KR100755133 B1 KR 100755133B1 KR 1020060083897 A KR1020060083897 A KR 1020060083897A KR 20060083897 A KR20060083897 A KR 20060083897A KR 100755133 B1 KR100755133 B1 KR 100755133B1
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South Korea
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film
metal
forming
hard mask
uppermost
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KR1020060083897A
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Korean (ko)
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김광전
육심훈
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

A method for forming a metal wire of a semiconductor device is provided to remove ring defect by introducing a hard masking method to disconnect an uppermost metal layer and photoresist, directly. A barrier metal layer(101) is formed on a semiconductor substrate. An uppermost metal layer(103) is formed on an upper portion of a barrier metal layer. An anti-reflective coating(105) is formed on an upper portion of the uppermost metal layer. A hard mask layer(107) is formed on an upper portion of the anti-reflective layer. The hard mask is patterned. The anti-reflective layer and the uppermost metal layer are sequentially patterned through etching using the patterned hard mask layer as a mask to form an uppermost metal wire. The structure forming the uppermost metal wire is gap-filled by using an insulating material to form an interlayer dielectric. The interlayer dielectric is planarized.

Description

반도체 소자의 금속 배선 형성 방법{METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE}METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE

도 1은 금속 배선이 형성된 반도체 소자의 단면도,1 is a cross-sectional view of a semiconductor device in which metal wiring is formed;

도 2a 내지 도 2g는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.2A to 2G are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 더욱 상세하게는 하드 마스킹 기법을 도입하여 최상부 금속막과 포토레지스트가 직접 접하지 않게 하여 링 디펙트(Ring defect)를 제거한 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices. More particularly, the metal wirings of semiconductor devices are removed from ring defects by introducing hard masking techniques so that the top metal film and the photoresist do not directly contact each other. It relates to a forming method.

반도체 공정 중 최상부 금속막(Top metal layer)은 큰 전압이 걸리기 때문에 전압에 의한 스트레스를 견뎌야 한다. 이것을 위해서 보통 최상부 금속막은 두께를 두껍게 형성하는데, 두꺼운 금속을 식각하기 위해서 포토레지스트도 더 높게 올라가야 하며, 현상(develop)을 오랫동안 한다든지 이중으로 현상 공정을 수행하기도 한다. 하지만 이 과정 중에 현상 화합물이 금속을 부식시킴으로써 금속막이 통째로 없어지거나 원형의 금속이 장벽 금속 위에 남기도 한다. 이것을 제거하기 위해서 비반사막을 깔아서 현상 화합물과 금속이 접촉하는 것을 방지하여 현상 화합물에 의한 금속 부식을 제거하고 있다.Since the top metal layer takes a large voltage during the semiconductor process, it must withstand the stress caused by the voltage. For this purpose, the uppermost metal film is usually made thicker, in order to etch the thick metal, the photoresist must also be raised, and the development process is performed for a long time or a double development process. However, during this process, the developing compound corrodes the metal, causing the entire metal film to disappear or the circular metal remains on the barrier metal. In order to remove this, an antireflection film is laid to prevent the developing compound from coming into contact with the metal to remove metal corrosion caused by the developing compound.

종래 기술에 따른 반도체 소자의 금속 배선 형성 방법을 도 1을 통해 살펴보기로 한다.A method of forming a metal wire of a semiconductor device according to the prior art will be described with reference to FIG. 1.

먼저, 최상부 금속막(13)의 하부에는 장벽금속막(Barrier Metal)(11)으로서 티타늄막(Ti) 또는 티타늄나이트라이드막(TiN)을 형성한다.First, a titanium film Ti or a titanium nitride film TiN is formed below the uppermost metal film 13 as a barrier metal film 11.

최상부 금속막(13)의 상부에는 금속 배선의 재료인 알루미늄막(Al)의 반사율이 심한 관계로 금속 배선의 패턴을 정의하기 위한 포토리쏘그라피 공정시 직접적인 마스킹 작업이 불가능하므로 알루미늄막(Al)의 반사율을 낮추기 위하여 최상부 금속막(13)상에 비반사막(Anti-Reflection-Coating)(15) 역할을 하는 티타늄(Ti)/티타늄나이트라이드막(TiN)을 형성한다.Since the reflectivity of the aluminum film Al, which is the material of the metal wiring, is high on the uppermost metal film 13, direct masking is not possible in the photolithography process to define the pattern of the metal wiring. In order to lower the reflectance, a titanium (Ti) / titanium nitride film (TiN) serving as an anti-reflection coating (15) is formed on the uppermost metal film (13).

이후, 비반사막(15) 상부에 소정두께의 포토레지스트를 도포한 후 패터닝하며, 포토레지스트를 마스크로 하여 비반사막(15)과 최상부 금속막(13)을 순차 패터닝하여 최상부 금속 배선을 형성한다.Thereafter, a photoresist having a predetermined thickness is coated on the antireflective film 15 and then patterned. The top reflective film 15 and the uppermost metal film 13 are sequentially patterned to form a top metal wiring.

그리고, 전체 상부에 절연 물질을 매립하여 층간 절연막(17)인 IMD(Inter-Metallic Dielectric)층을 형성한 후에 평탄화하여 최상부 금속 배선을 완성한다.Then, the insulating material is embedded in the entire upper portion to form an inter-metal dielectric (IMD) layer, which is an interlayer insulating film 17, and then planarized to complete the top metal wiring.

그러나, 전술한 바와 같은 종래 기술에 의하면 비반사막(15)으로 주로 이용되는 티타늄(Ti)/티타늄나이트라이드막(TiN)은 디가싱(Degassing)에 의해 가스 홀(Gas hole)이 생성되는 결점으로 인해 링 디펙트를 유발하는 문제점이 있었다.However, according to the conventional technology as described above, the titanium (Ti) / titanium nitride film (TiN), which is mainly used as the anti-reflective film 15, is a defect that gas holes are generated by degassing. There was a problem causing ring defects.

본 발명은 이와 같은 종래의 문제점을 해결하기 위하여 제안한 것으로, 하드 마스킹 기법을 도입하여 최상부 금속막과 포토레지스트가 직접 접하지 않게 하여 링 디펙트를 제거한 반도체 소자의 금속 배선 형성 방법을 제공하는 데 그 목적이 있다.The present invention has been proposed to solve such a conventional problem, and provides a method of forming a metal wiring of a semiconductor device in which ring defects are removed by introducing a hard masking technique so that the top metal film and the photoresist do not directly contact each other. There is a purpose.

이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은, 반도체 기판 상에 장벽금속막을 형성하는 단계와, 장벽금속막의 상부에 최상부 금속막을 형성하는 단계와, 최상부 금속막의 상부에 비반사막을 형성하는 단계와, 비반사막의 상부에 하드 마스크막을 형성하는 단계와, 하드 마스크막을 패터닝하는 단계와, 패터닝한 하드 마스크막을 마스크로 한 식각을 통해 비반사막과 최상부 금속막을 순차 패터닝하여 최상부 금속 배선을 형성하는 단계와, 최상부 금속 배선을 형성한 구조물에 대해 절연 물질을 이용해 매립하여 층간 절연막을 형성하는 단계와, 층간 절연막을 평탄화하는 단계를 포함한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to the present invention includes forming a barrier metal film on a semiconductor substrate, forming a top metal film on the top of the barrier metal film, and forming a top metal film on the top of the top metal film. Forming a non-reflective film, forming a hard mask film on top of the non-reflective film, patterning the hard mask film, and patterning the anti-reflective film and the uppermost metal film sequentially by etching using the patterned hard mask film as a mask. Forming a metal wiring, forming an interlayer insulating film by filling an uppermost metal wiring with an insulating material, and planarizing the interlayer insulating film.

바람직하기로, 하드 마스크막에 이용하였던 물질과 동일한 물질을 이용하여 층간 절연막을 형성한다.Preferably, an interlayer insulating film is formed using the same material as that used for the hard mask film.

또한, 하드 마스크막과 층간 절연막에 이용되는 절연 물질은 금속 성분과 비교할 때에 식각 선택비 차가 큰 산화막을 이용하는 것이 바람직하다.In addition, as the insulating material used for the hard mask film and the interlayer insulating film, it is preferable to use an oxide film having a large difference in etching selectivity compared with the metal component.

이하, 본 발명의 바람직한 실시 예를 첨부된 도면들을 참조하여 상세히 설명 한다. 본 발명을 설명함에 있어, 관련된 공지 구성 또는 기능에 대한 구체적인 설명이 본 발명의 요지를 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

도 2a 내지 도 2g는 본 발명에 따른 금속 배선 형성 방법을 나타낸 공정 단면도이다.2A to 2G are cross-sectional views illustrating a method of forming a metal wiring according to the present invention.

도 2a를 참조하면, 반도체 기판(도시 생략됨)상에 장벽금속막(Barrier Metal)(101)으로서 티타늄막(Ti) 또는 티타늄나이트라이드막(TiN)을 형성한다.Referring to FIG. 2A, a titanium film Ti or a titanium nitride film TiN is formed as a barrier metal 101 on a semiconductor substrate (not shown).

그리고, 장벽금속막(101)의 상부에는 금속 배선의 재료인 알루미늄막(Al)으로 최상부 금속막(103)을 형성한다.On top of the barrier metal film 101, an uppermost metal film 103 is formed of aluminum film Al, which is a material of metal wiring.

다음으로, 최상부 금속막(103)으로 이용되는 알루미늄의 반사율이 심한 관계로 금속 배선의 패턴을 정의하기 위한 포토리쏘그라피 공정시 직접적인 마스킹 작업이 불가능하므로 알루미늄막(Al)의 반사율을 낮추기 위하여 최상부 금속막(103)상에 비반사막(Anti-Reflection-Coating)(105) 역할을 하는 티타늄(Ti)/티타늄나이트라이드막(TiN)을 형성한다.Next, since the reflectivity of the aluminum used as the uppermost metal film 103 is severe, direct masking is not possible during the photolithography process to define the pattern of the metal wiring, so that the uppermost metal may be lowered to lower the reflectance of the aluminum film Al. A titanium (Ti) / titanium nitride film (TiN) serving as an anti-reflection-coating 105 is formed on the film 103.

그리고, 비반사막(105)의 상부에 하드 마스크막(107)을 형성한다. 하드 마스크막(107)은 금속 성분과 비교할 때에 식각 선택비 차가 큰 산화막을 이용하는 것이 바람직하다. 여기서 하드 마스킹 물질로서 산화막 대신에 질화막을 이용할 수도 있으나, 이후 공정에서 층간 절연물질로 주로 이용되는 산화막을 이용하는 것이 더 바람직하다.Then, a hard mask film 107 is formed on the antireflective film 105. The hard mask film 107 is preferably an oxide film having a large difference in etching selectivity compared with the metal component. A nitride film may be used instead of the oxide film as the hard masking material, but it is more preferable to use an oxide film mainly used as an interlayer insulating material in a subsequent process.

도 2b를 참조하면, 하드 마스크막(107) 상부에 소정두께의 포토레지스트를 도포한 후 최상층 금속 배선이 형성될 부위에만 남도록 선택적으로 노광 및 현상하여 패터닝한다.Referring to FIG. 2B, a photoresist having a predetermined thickness is coated on the hard mask layer 107 and then selectively exposed and developed so as to remain only at a portion where the uppermost metal wiring is to be formed.

도 2c를 참조하면, 패터닝된 포토레지스트를 마스크로 하여 하드 마스크막(107)을 패터닝한다.Referring to FIG. 2C, the hard mask film 107 is patterned using the patterned photoresist as a mask.

도 2d를 참조하면, 하드 마스크막(107)을 마스크로 한 반응성 이온 식각(RIE)을 통해 비반사막(105)과 최상부 금속막(103)을 순차 패터닝하여 최상부 금속 배선을 형성한다. 여기서 하드 마스크막(107)의 재질인 산화막은 금속 성분과 비교할 때에 식각 선택비 차가 크므로 식각을 하지 않는 곳의 최상부 금속막(103)이 어택(Attack)을 받지 않는다.Referring to FIG. 2D, the top anti-reflective film 105 and the top metal film 103 are sequentially patterned through reactive ion etching (RIE) using the hard mask film 107 as a mask to form a top metal wiring. Since the oxide film, which is a material of the hard mask film 107, has a large difference in etching selectivity compared to a metal component, the uppermost metal film 103 at which the etching is not performed is not attacked.

도 2f를 참조하면, 패터닝된 구조물에 대해 하드 마스크막(107)에 이용하였던 물질과 동일한 물질, 즉 산화막을 이용해 매립하여 층간 절연막(107)인 IMD(Inter-Metallic Dielectric)층을 형성한다.Referring to FIG. 2F, an interlayer insulating layer 107 (IMD) layer, which is an interlayer insulating layer 107, is formed by filling the patterned structure with the same material as that used for the hard mask layer 107, that is, an oxide layer.

도 2g를 참조하면, 화학적 기계적 연마(CMP) 공정을 통해 전체 구조물의 표면을 평탄화하여 최상부 금속 배선을 완성한다.Referring to FIG. 2G, the surface of the entire structure is planarized through a chemical mechanical polishing (CMP) process to complete the top metal wiring.

지금까지의 설명은 본 발명을 예시적으로 설명한 것에 불과한 것으로, 본 발명의 기술이 당업자에 의하여 용이하게 변형 실시될 가능성이 자명하다. 이러한 변형된 실시 예들은 본 발명의 특허청구범위에 기재된 기술사상에 당연히 포함되는 것으로 해석되어야 할 것이다.The above description is merely illustrative of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be construed as naturally included in the technical spirit described in the claims of the present invention.

전술한 바와 같이 본 발명은 하드 마스킹 기법을 도입하여 최상부 금속막과 포토레지스트가 직접 접하지 않게 하여 링 디펙트를 제거함으로써 반도체 소자의 전기적 특성이 향상되는 효과가 있다.As described above, the present invention has an effect of improving the electrical characteristics of the semiconductor device by removing the ring defect by introducing a hard masking technique so that the uppermost metal layer and the photoresist do not directly contact each other.

Claims (3)

(a) 반도체 기판 상에 장벽금속막을 형성하는 단계와,(a) forming a barrier metal film on the semiconductor substrate; (b) 상기 장벽금속막의 상부에 최상부 금속막을 형성하는 단계와,(b) forming an uppermost metal film on the barrier metal film; (c) 상기 최상부 금속막의 상부에 비반사막을 형성하는 단계와,(c) forming an antireflective film on the uppermost metal film; (d) 상기 비반사막의 상부에 하드 마스크막을 형성하는 단계와,(d) forming a hard mask film on the antireflective film, (e) 상기 하드 마스크막을 패터닝하는 단계와,(e) patterning the hard mask layer; (f) 상기 패터닝한 하드 마스크막을 마스크로 한 식각을 통해 상기 비반사막과 상기 최상부 금속막을 순차 패터닝하여 최상부 금속 배선을 형성하는 단계와,(f) sequentially patterning the non-reflective film and the top metal film through etching using the patterned hard mask film as a mask to form a top metal wiring; (g) 상기 최상부 금속 배선을 형성한 구조물에 대해 절연 물질을 이용해 매립하여 층간 절연막을 형성하는 단계와,(g) filling the structure on which the uppermost metal wiring is formed with an insulating material to form an interlayer insulating film; (h) 상기 층간 절연막을 평탄화하는 단계(h) planarizing the interlayer insulating film 를 포함하는 반도체 소자의 금속 배선 형성 방법.Metal wiring forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 (g) 단계는, 상기 하드 마스크막에 이용하였던 물질과 동일한 물질을 이용하여 상기 층간 절연막을 형성하는In the step (g), the insulating interlayer is formed using the same material as that used for the hard mask film. 반도체 소자의 금속 배선 형성 방법.Metal wiring formation method of a semiconductor element. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 (d) 단계 및 상기 (g) 단계에서 이용하는 절연 물질은 산화막인The insulating material used in the steps (d) and (g) is an oxide film. 반도체 소자의 금속 배선 형성 방법.Metal wiring formation method of a semiconductor element.
KR1020060083897A 2006-08-31 2006-08-31 Method for forming metal line of semiconductor device KR100755133B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100227853B1 (en) * 1997-01-24 1999-11-01 윤종용 Semiconductor device and process for fabricating the same
KR20060000487A (en) 2004-06-29 2006-01-06 매그나칩 반도체 유한회사 Method for forming photo resist pattern of semiconductor device
KR100548515B1 (en) * 2003-07-09 2006-02-02 매그나칩 반도체 유한회사 method for forming metal line of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100227853B1 (en) * 1997-01-24 1999-11-01 윤종용 Semiconductor device and process for fabricating the same
KR100548515B1 (en) * 2003-07-09 2006-02-02 매그나칩 반도체 유한회사 method for forming metal line of semiconductor device
KR20060000487A (en) 2004-06-29 2006-01-06 매그나칩 반도체 유한회사 Method for forming photo resist pattern of semiconductor device

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