KR100752965B1 - A method and system for reducing photo-assisted corrosion in wafers during cleaning processes - Google Patents

Abstract

The present invention provides a method and system for reducing and eliminating corrosion by light during the cleaning process. In one example, a method for manufacturing a composite material for a cover of a wafer cleaning system is provided. The first transparent layer is formed. A transparency variable layer is formed on the first transparent layer. An electrical connection is defined between the first and second portions of the transparency variable layer. Then, a second transparent layer is formed on the variable transparency layer.

Description

A METHOD AND SYSTEM FOR REDUCING PHOTO-ASSISTED CORROSION IN WAFERS DURING CLEANING PROCESSES}

BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to semiconductor wafer cleaning, and more particularly to techniques for reducing corrosion by light on a wafer used to manufacture semiconductor devices.

It is well known in the semiconductor chip fabrication process that there is a need to clean the surface of the wafer after a chemical mechanical polishing (CMP) process. The Cu CMP process leaves various types of contaminants such as particles and metal ions on the wafer surface. Therefore, cleaning needs to avoid deterioration of the electrical characteristics of the dielectric.

For discussion only, FIG. 1 shows a simplified wafer cleaning system with a brush box 100. After the CMP process, the wafer is sometimes processed by a cleaning process using HF in a wafer cleaning system. The wafer enters the brush box 100 into which the wafer is inserted between the upper brush 104a and the lower brush 104b. The wafer is typically rotated by a brush 104 and a set of rollers (not shown), thereby allowing the brush 104 to properly clean the top and bottom surfaces of the wafer. The cleaning process can typically be observed through a brush box cover 102 of transparent plastic material.

2A shows a partial cross-sectional view of an exemplary semiconductor chip after the top layer has been processed by the same CMP process. Using standard impurity implantation, photolithography and etching techniques, the P-type transistor and the N-type transistor are fabricated on the P-type silicon substrate 200. As shown, each transistor has a gate, source, and drain fabricated in a suitable well. The pattern of intersecting P-type transistors and N-type transistors causes complementary metal oxide semiconductor (CMOS) devices.

The first oxide layer 202 is formed over the transistor and the substrate 200. Conventional photolithography, etching and deposition techniques are used to make tungsten plug 210 and copper line 212. The tungsten plug 210 provides an electrical connection between the copper wires 212 and provides the active characteristics of the transistor. The second oxide layer 204 is formed on the copper oxide line 212 with the first oxide layer 202. Conventional photolithography, etching and deposition techniques are used to make copper vias 220 and copper wires 214 in the second oxide layer 204. The copper via 220 provides an electrical connection between copper wires in the second layer, and provides copper wire 212 or tungsten plug 210 in the first layer.

At this time, the wafer is typically processed by the same CMP process to planarize the surface of the wafer, leaving a level surface as shown in FIG. 2A. After the CMP process, the wafer is cleaned in a wafer cleaning system, as described above in connection with FIG.                 

FIG. 2B shows a partial cross-sectional view of the conventional semiconductor wafer of FIG. 2A after being cleaned in the wafer cleaning system of FIG. 1. As shown, the copper wire 214 of the top layer is susceptible to corrosion by light during the cleaning process. Corrosion by light is thought to be caused in part by light photon passing through the transparent plastic cover 102 of the brush box 100 and reaches a P / N junction that can act as a solar cell. Photons are projected onto the transparent plastic cover 102 by normal clean room illumination. Unfortunately, the amount of this normal light generally required to observe the cleaning process (i.e. whether the brush is properly cleaning the wafer) causes a catastrophic corrosion effect.

In this cross sectional example, a copper wire, copper via or tungsten plug is electrically connected to another part of the P / N junction. A cleaning fluid, typically an electrolyte used to clean the wafer surface, approaches the electrical circuit as electrons (e ⁻ ) and holes (h ⁺ ) are moved across the P / N junction. The photon generated electron / hole pairs at the junction are separated by an electric field. The introduced carrier causes a potential difference between the two sides of the junction. This potential difference increases with light intensity. Therefore, copper corrodes at the electrode connected to the P side of the junction: Cu → Cu ²⁺ + 2e ⁻ . The generation soluble ionic species can diffuse to the other electrode, which may result in ^{reduction: Cu 2+ + 2e - → Cu} . Note that the general equation of corrosion for some metals is M → M ^{n +} + ne ⁻ , and the general reduction equation for some metals is M ^{n +} + ne ⁻ → M.

Unfortunately, as shown in FIG. 2B, corrosion by light of this type displaces copper wire and impairs the dynamic properties of the intended physical topography. At some locations on the wafer surface above the P-type transistors, the corrosive effect of light results in corroded copper wire 224 or completely dissolved copper wire 226. In other words, the corrosion by light completely corrodes the copper wire so that the wire no longer exists. On the other hand, the corrosion effect of light causes copper deposit 222 to be formed over the entire surface of the N-type transistor. This distorted topography, which involves copper wire corrosion, will cause device defects that render the entire chip inoperable. Some defective devices mean that the entire chip must be discarded, which reduces yield and drastically increases the cost of the manufacturing process. However, this effect will generally occur across the entire wafer, thus damaging all chips on the wafer. Of course, this increases the manufacturing cost.

Several attempts have been made to reduce corrosion. One of them is the addition of corrosion inhibitors to the chemical cleaning liquids used to clean the wafer surface. Examples of corrosion inhibitors include complexing agents and passivating agents. However, this method of changing the chemical cleaning solution has not been provided adequately and effectively. For more information on the corrosive effects of light, see A. Beverley, et al., Published by Honolulu, Hawaii, at the 196th ECS Conference (October 1999). There is a literature. This document is incorporated herein by reference.

In view of the foregoing, there is a need for a cleaning process that avoids the problems of the prior art by implementing improved techniques to reduce the corrosive effect of light on the wafer during cleaning.

Generally speaking, the present invention satisfies these needs by providing a method and system for sufficiently removing corrosion by light on a semiconductor wafer during a cleaning operation. Of course, the present invention may be practiced in many ways, including as a process, apparatus, system, device or method. Several embodiments of the invention are described below.

In a first embodiment, a method for producing a composite material is disclosed. The first transparent layer is formed. A transparency variable layer is formed on the first transparent layer. An electrical connection is defined between the first and second portions of the transparency variable layer. Then, a second transparent layer is formed on the variable transparency layer.

In another embodiment, a semiconductor wafer cleaning system is disclosed. The system has a cover with a first part and a second part, which cover is made of a multilayer composite material. The cover comprises a first transparent layer; A transparency variable layer on the first transparent layer; A set of first electrical connections attached to the transparency variable layer in the first portion; A set of second electrical connections attached to the variable transparency layer in the second portion; A second transparent layer is included on the variable transparency layer.

In yet another embodiment, a variable transparency cover is disclosed. The cover includes a first transparent layer having a first side and a second side and extending between the first side and the second side; A transparency variable layer coated on the first transparent layer; A set of first electrical connections conductively integrated in the transparency variable layer coated at the first side; A set of second electrical connections conductively integrated in the transparency variable layer coated at the second side; A second transparent layer is coated on the variable transparency layer and extends between the first side and the second side.

Advantageously, the present invention addresses the problem of corrosion by light by providing a cover in a wafer cleaning system that can preferably be adjusted from being nearly transparent to being opaque. If the cover is opaque, since the cleaning process can proceed even in the absence of a significant amount of light, the deleterious effects of light energy on the wafer surface are almost eliminated. In addition to the standalone cleaning system, the cover may be integrated into a post-CMP cleaning system to minimize corrosion by light. In addition, corrosion by light can be minimized by integrating such a cover into an integrated CMP tool. The integrated CMP tool is a tool that implements both cleaning and CMP modules. Typically, these modules are connected or connected as special wafer handling facilities.

Therefore, the wafer to be cleaned preferably will not be susceptible to corrosion by light which alters the copper wire and damages the intended topography of the dynamics. As a result, device defects that render the entire chip disabled will be sufficiently reduced. Less chips will have to be discarded, preferably the yield will increase, and the cost of running the manufacturing process will not be excessively increased.

Other aspects and advantages of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings, which are shown for illustrative principles of the invention.

1 shows a wafer cleaning system with a brush box,                 

2A is a cross sectional view of a conventional semiconductor chip after an upper layer has been processed by the same CMP process;

FIG. 2B is a cross-sectional view of the conventional semiconductor chip of FIG. 2A after the wafer has been cleaned in the wafer cleaning system of FIG. 1;

3A is a top view of a wafer cleaning system according to one embodiment of the present invention;

3B is a side view of a wafer cleaning system according to one embodiment of the present invention;

3C is a side view of a wafer cleaning system in accordance with one embodiment of the present invention;

4A is a side view of a composite material used for a cover of a wafer cleaning system according to one embodiment of the present invention;

4B is a top view of a composite material used for the cover of a wafer cleaning system according to one embodiment of the present invention;

5 is a high level schematic diagram of a preferred system component for a transparency variable cover in accordance with one embodiment of the present invention;

6A is a flowchart illustrating a method for forming a composite material according to an embodiment of the present invention;

6B is a flowchart illustrating a method for forming a variable transparency cover for a wafer cleaning system according to an embodiment of the present invention.

An invention of a method and system for reducing copper corrosion by light during a wafer cleaning process is described. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by one of ordinary skill in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail so as not to unnecessarily obscure the present invention.

3A, 3B and 3C show top and side surfaces of a wafer cleaning system according to an embodiment of the present invention, respectively. Wafer cleaning system 300 typically includes an input 302 that is input such that a plurality of wafers are cleaned by the system after the wafer has been processed by a CMP operation. When the wafer is inserted into the input portion 302, the wafer is taken out of the input portion 302 and moved to the brush box 304 including the first brush box 304a and the second brush box 304b. Inside the brush box, several cleaning operations are applied to the wafer.

After the brush is applied to the wafer in brush box 304, the wafer is moved to an SRD portion (spin, rinse and dry station) 306. In the SRD portion 306, de-ionized (DI) water is sprinkled on the surface of the wafer while the wafer spins at a rotational speed of about 100 to 400 times per minute, and then dried. To spin. After the wafer is placed in the SRD portion 306, an unload handler 308 takes the wafer and moves it to the output portion 310. The cleaning system 300 is programmed and controlled from the system electronics 312.

Preferably, the transparency level of the cover of the wafer cleaning system 300 can be opaquely adjusted from being sufficiently transparent, as shown in FIG. 3C. A "cover" is part of a wafer cleaning system that provides wafer cleaning operations. The term "sufficiently transparent" means that almost all of the light that goes toward the outer surface of the cover passes through the cover. The term "opaque" means that no light that passes toward the outer surface of the cover passes through the cover. "Outer surface of the cover" refers to the surface of the cover that is not facing a wafer cleaning operation. The term "light" refers to ultraviolet light and light in the visible spectrum. Depending on the material used to construct the cover, a change in transparency is accompanied by a corresponding change in color, as described in more detail below with respect to FIG. 4A.

If the cover is sufficiently transparent, the user can observe the cleaning process. However, as detailed above, if the cleaning is done after the copper CMP process, the light energy helps to corrode the copper wire. Accordingly, the present invention preferably provides a cover for a cleaning system that can be adjusted opaquely when the cleaning operation is performed and sufficiently transparent when the cleaning operation is not performed. In some cases, it is desirable to perform a cleaning operation when the cover is sufficiently opaque, but the internal cleaning operation can still be observed. This will allow the operator to determine whether the brush is working properly, and so on.

4A and 4B show side and top surfaces, respectively, of a composite material 400 used for the cover of a wafer cleaning system according to one embodiment of the present invention. Preferably, the composite material 400 includes a first transparent layer 404a and a second transparent layer 404b and a transparency variable layer 406 coated between the first transparent layer and the second transparent layer. It is preferable that a 1st transparent layer and a 2nd transparent layer consist of transparent acrylic materials. However, other known plastics and / or glass may be used.

The transparency variable layer 406 is preferably made of a photochromic material such as tungsten oxide (WO ₃ , WO _X ) or an electrochromic material. Alternative materials may include, for example, NB ₂ O ₅ , V ₂ O ₇ , TiO ₂ , ZnO, Cr ₂ O ₃ , MnO ₂ , CoO, NiO ₂ . Any one of these materials may be realized depending on the particular application. For this illustrative discussion, the reference will be tungsten oxide. To produce the composite material, preferably, the variable transparency layer 406 is sputtered into a first transparent layer 404a or a second transparent layer 404b. Spin-on technology formed by a sol-gel "process. A second transparent layer 404b is formed on top of the variable transparency layer 406.

The set of electrical connections 402a, 402b is conductively integrated into a portion of the transparency variable layer 406. When the bias voltage V ⁺ is applied across the entirety of the variable transparency layer 406 between the portions, the electrical circuit defined by the electrical connection 402 and the variable transparency layer 406 is closed. As shown in the preferred embodiment of FIG. 4, the first portion is on the first side of the variable transparency layer 406 and the second portion is on the second side of the variable transparency layer 406.

As the desired voltage application (V ⁺ ) is increased, the current I flowing across the transparency variable layer 406 increases proportionally. The increase in current causes electrons (e ⁻ ) to flow and excite atoms in the photochromic or electrochromic material. Excitation of the atoms causes a change in the transparency level accompanied by a change in color. Tungsten oxide is, for example, yellow light in a less excited state, so that the transparency variable layer 406 becomes sufficiently transparent. Tungsten oxide is dark blue in a more excited state, and thus the transparency variable layer 406 becomes opaque. In short, the low voltage (V ⁺ ) makes the cover sufficiently transparent, and the high voltage (V ⁺ ) makes the cover opaque.

In general, the voltage V ⁺ is preferably between about 0.5 volts and about 3 volts, more preferably between about 1 volt and about 1.5 volts, most preferably about 1.25 volts. When tungsten oxide (WO ₃ ) is used, it is preferred that the voltage (V ⁺ ) be between about 0.5 volts and about 5 volts, most preferably about 3 volts.

The scale of the composite material 400 is preferably defined by at least two parameters and the cover thickness b and the variable layer thickness a. The cover thickness b is preferably about 1 cm. The variable layer thickness a is preferably between about 0.5 μm and about 10 μm, most preferably about 3 μm.

5 shows a high level schematic diagram of a preferred system component for a transparencies variable cover in accordance with one embodiment of the present invention. The voltage controller 502 has an electrode (not shown) connected to the electrical connection 402, thereby establishing a bias voltage (V ⁺ ) across the transparency variable layer 406. The tuning control circuit 504, which receives an input from the control unit 506, provides the voltage controller 502 with a suitable state. The control unit 506 provides operation control 512 and emergency control 514 to the user. If the user is using the operation control 512, the tuning control circuit 504 provides the voltage controller 502 with the state of the regular operation 510. Operation control 512 allows the user to adjust the voltage low or high, depending on the level of transparency required.

If the user is using the emergency control 514, the tuning control circuit 504 preferably provides a voltage shut-off to the voltage controller 502. When the voltage is shut off, the composite material 400 is preferably in the most transparent state. Emergency control 514 is required when a problem such as a broken wafer occurs in the cleaning system and the user needs to investigate the problem immediately. In other cases, emergency control 514 will be advantageous when the power is suddenly shut off and the operator needs to look inside the cleaner to determine the status of the cleaning session.

6A is a flowchart illustrating a method for forming a composite material 400 according to one embodiment of the present invention. The method starts at operation 702 in which the first transparent layer is formed. The method then proceeds to operation 704 where a transparency variable layer is formed over the first transparent layer. Preferably, the transparency variable layer has features such as those described with reference to FIGS. 4A and 4B. Next, the method proceeds to operation 706 where an electrical connection is defined between the first and second portions of the transparency variable layer. The method then proceeds to operation 708 where the second transparent layer is formed over the transparency variable layer.

6B is a flowchart illustrating a method for forming a variable transparency cover for a wafer cleaning system according to an embodiment of the present invention. The method starts with operation 802 where a first transparent layer is formed for the semiconductor cleaner cover. The method then proceeds to operation 804 where a transparency variable layer is formed over the first transparent layer.

Preferably, as described in connection with FIG. 4B, the cover is equipped with electrodes at suitable stages so that the circuit can be connected thereto and current flow is possible. Therefore, current flow across the cover allows the cover to change transparency. If the cleaning system is in operation and the cleaning process is performed after the same CMP, corrosion by light will be advantageously prevented. This is an important step in the cleaning technology, where all conventional cleaning systems use a one-state transparent cover that allows light to pass freely. The cleaning system using the variable cover can now be programmed so that the state of transparency becomes almost dark when the cleaning is in progress and becomes bright when the cleaning operation is being performed. Of course, the level of transparency can vary between each extreme, depending on the user needs and the type of cleaning being done.

Next, the method proceeds to operation 806 where an electrical connection is defined between the first and second portions of the transparency variable layer. The method then proceeds to operation 808 where the second transparent layer is formed over the transparency variable layer.

Although the present invention has been described in connection with the preferred embodiments, various modifications, additions, substitutions, and equivalents are apparent to those skilled in the art. For example, even with a particular reference as a brush box, any other brush scrub device may benefit from the method of teaching the present invention. Moreover, the cleaning embodiments can be applied to wafers of any size 200 mm, 300 mm or more, as well as other sizes and shapes. Therefore, the present invention may include all such modifications, additions, substitutions, and equivalents falling within the scope of the present invention.

Claims (20)

delete delete delete delete Surrounding the semiconductor wafer cleaning apparatus, and having a cover having a first portion and a second portion, and a voltage controller 502 having a first electrode connector and a second electrode connector, The cover, A first transparent layer 404a; A transparency variable layer 406 on the first transparent layer 404a; A set of first electrical connections attached to the variable transparency layer 406 in the first portion; A set of second electrical connections attached to the variable transparency layer 406 in the second portion; And a multi-layered composite material including a second transparent layer (404b) on the transparency variable layer (406). delete 6. The semiconductor wafer cleaning apparatus according to claim 5, wherein the first electrode connector is connected to the set of first electrical connections, and the second electrode connector is connected to the set of second electrical connections. 10. The apparatus of claim 7, further comprising a tuning control circuit 504 that integrates with the voltage controller 502, wherein the tuning control circuit 504 includes a variable transparency layer 406 to cause a change in transparency level in the cover. And a bias voltage). 9. The apparatus of claim 8, wherein increasing the bias voltage magnitude decreases the transparency level of the cover. 10. The apparatus of claim 8, wherein reducing the bias voltage magnitude increases the transparency level of the cover. 9. The semiconductor wafer cleaning apparatus according to claim 8, wherein the magnitude of the bias voltage is about zero and the cover is sufficiently transparent. With a first side and a second side, A first transparent layer (404a) extending between the first side and the second side; A transparency variable layer 406 coated on the first transparent layer 404a; A set of first electrical connections conductively integrated with the coated transparency variable layer at the first side; A set of second electrical connections conductively integrated with said coated transparency variable layer at said second side; A second transparent layer 406b coated over the variable transparency layer 406 and extending between the first side and the second side, A cover installed in the cleaning system to surround the substrate during cleaning. 13. The cover of claim 12, wherein said cleaning system further comprises a voltage controller (502) having a first electrode connector and a second electrode connector. The cover of claim 13, wherein the first electrode connector is connected to the set of first electrical connections, and the second electrode connector is connected to the set of second electrical connections. 15. The cleaning system of claim 14, wherein the cleaning system further comprises a tuning control circuit 504 that integrates with the voltage controller 502, wherein the tuning control circuit 504 is variable in transparency to cause a change in color in the cover. A cover configured to set a desired voltage application to layer 406. The cover of claim 15, wherein the change in color is configured to limit or increase the amount of light passing through the cover. 17. The cover of claim 16, wherein the cover is defined on a brush box in the cleaning system. 13. The cover of claim 12, wherein the cover is defined in a post-CMP semiconductor wafer cleaning system to minimize corrosion by light. 13. The cover of claim 12, wherein the cover is integrated into an integrated CMP tool with a cleaning module and a CMP module to minimize corrosion by light. The method of claim 12, wherein the variable transparency layer 406 is composed of WO ₃ , WO _X , NB ₂ O ₅ , V ₂ O ₇ , TiO ₂ , ZnO, Cr ₂ O ₃ , MnO ₂ , CoO, and NiO ₂ . The cover, characterized in that made of a material selected from.

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