KR100739936B1 - Method for fabricating fuse in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a fuse of a semiconductor device. In order to alleviate the compressive stress applied to a polysilicon film for a fuse, an insulating film having a tensile stress on or above a polysilicon film for a fuse or a low compressive stress By forming an insulating film to reduce the stress applied to the polysilicon film for the fuse, or to form a polysilicon film for the fuse and then perform a heat treatment process to reduce the stress of the polysilicon film itself for the fuse (fuse crack) It is a technique to prevent.

Fuse, Crack, Tensile Stress, Compression Stress

Description

Method for fabricating fuse in semiconductor device

1 is a view showing the structure of a typical fuse

2 is a graph showing stress hysteresis with respect to the temperature of PETEOS oxide film

3 is a graph showing stress hysteresis with respect to temperature of a polysilicon film for fuse

4 is a diagram schematically showing a stress state of each layer constituting a fuse;

)를 나타낸 그래프5 is a fracture toughness value of a polysilicon film for fuse (

) Graph

6A to 6C are graphs showing stress hysteresis with respect to the temperatures of the low pressure nitride film, the low pressure TEOS oxide film, and the O ₃ TEOS oxide film, respectively.

The present invention relates to a method of manufacturing a fuse of a semiconductor device, and more particularly to a method of manufacturing a fuse of a semiconductor device for preventing a fuse crack.

As semiconductor devices are highly integrated due to the development of fine pattern forming technology, in the case of DRAM (Dynamic Random Access Memory (DRAM)) devices, the memory capacity is increased by four times, and the size of the chip is about twice as large. Is increased.

Therefore, since the rate of partial defects is increased, the yield of a complete chip having no defects in the manufactured chip is reduced, resulting in a decrease in productivity. Thus, an extra memory cell is formed in the chip, thereby causing defects during the manufacturing process. It is used interchangeably with the cell to increase the yield of the chip.

To this end, after completing a semiconductor device, a fuse is opened to repair a defective circuit, and then a corresponding fuse is cut using a laser.

However, current production fuses have a problem of high fail rate due to cracks. Such a fuse crack is impossible to repair (repair) it is directly connected to the yield of the product.

On the other hand, the fuse crack is not detected during the probe test (Probe Test) process, it is found after the package (package) is a situation that is difficult to detect the failure.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to provide a method for manufacturing a fuse of a semiconductor device which can reduce the occurrence of fuse cracks.

The fuse manufacturing method of the semiconductor device according to an aspect of the present invention, in order to alleviate the compressive stress applied to the polysilicon film for the fuse, at least one insulating film of the upper insulating film and the lower insulating film formed on the upper and lower portions of the polysilicon film for fuse Is formed by including at least one of a low pressure TEOS (Tetra Ethyl Ortho Silicate) oxide film, a low pressure nitride film, and an O ₃ TEOS oxide film.

According to another aspect of the present invention, there is provided a method of manufacturing a fuse of a semiconductor device, the method including: providing a semiconductor substrate having a lower insulating film formed thereon, depositing a polysilicon film for a fuse on the lower insulating film, and performing a heat treatment process to obtain the fuse poly Relieving stress of the silicon film, and forming an upper insulating film on the fuse polysilicon film.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

FIG. 1 is a view illustrating a structure of a general fuse, and FIGS. 2 and 3 are graphs showing stress hysteresis with respect to temperatures of a PETEOS oxide film and a polysilicon film for a fuse, respectively, and FIG. 4 is a layer showing each layer constituting the fuse. It is a figure which shows typically the stress state of these.

According to FIG. 1, the fuse is a polysilicon film 11 for a 1500Å fuse sandwiched between a 2000 mm thick bottom PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate) oxide film 10 and a 18000 mm thick top PETEOS oxide film 12. It is composed of

2 and 3, the PETEOS oxide film has a compressive stress (-1E9dyn / cm 2) at room temperature, and a tensile stress (+ 3E9dyn / cm 2) in the case of polysilicon.

Therefore, as shown in FIG. 4, the fuse polysilicon film 11 has a stress state to be reduced, and the lower and upper PETEOS oxide films 10 and 12 have a stress state to be stretched in the longitudinal direction. .

As a result, the compressive stress of the lower PETEOS oxide film 10 and the upper PETEOS oxide film 12 existing above and below the polysilicon film 11 for a fuse acts as a tensile stress on the polysilicon film 11 for a fuse. As the polysilicon film 11 itself has a tensile stress, a crack is generated in the polysilicon film 11 for the fuse.

In general, cracks are generated when the following conditions (1) are satisfied.

>

>

는 응력집중도,

은 고유 파괴인성치(fracture toughness)를 나타낸다.Where

Is the stress concentration,

Represents the intrinsic fracture toughness.

)를 초과하는 응력집중도(

)가 발생하는 경우에 유발된다. 퓨즈로 사용되는 퓨즈용 폴리실리콘막의 파괴인성치는 평균적으로 0.85Mpa-m^0.5 정도인 것으로 보고된 바 있다(C.L Muhlstein et.al, Meth. of Mater 36(2004)).In other words, the crack is the inherent fracture toughness of the material (

Stress concentration in excess of

Is caused when) occurs. The fracture toughness of polysilicon films for fuses used as fuses has been reported to be on average 0.85 Mpa-m ^0.5 ( CL Muhlstein et.al, Meth. Of Mater 36 (2004) ).

)는 다음 수학식 2와 같이 막의 응력과 두께의 함수로 표현된다(A.G Evans et. al.j. Mater. Res.(1998)).Stress concentration in the case of thin film system

) Is expressed as a function of the stress and thickness of the film as shown in Equation 2 ( AG Evans et al. J. Mater. Res. (1998) ).

=Ω

= Ω

는 막의 잔류응력,

는 막 두께를 각각 나타낸다.Where Ω is proportional constant,

Is the residual stress of the membrane,

Represents the film thickness, respectively.

)를 살펴보면 다음 표 1과 같다.Stress concentration degree applied to the polysilicon film 11 for fuse by using Equation 2

) Is shown in Table 1 below.

Thickness Stress (dyn / ㎠) Kc (Mpa-m ^0.5 ) Top PETEOS oxide 2000 -1.00E + 09 -0.065 Polysilicon Film for Fuse 1500 -3.00E + 09 -0.170 Bottom PETEOS oxide 18000 -1.00E + 09 -0.196 -0.431

Here, the tensile stress of the polysilicon film 11 for fuse is actually referred to as compressive stress because it acts in the tensile direction.

)를 측정한 그래프이다.5 is a fracture toughness value of a polysilicon film for fuse (

) Is a graph of measurement.

)는 0.43 정도로, 퓨즈용 폴리실리콘막의 평균 파괴인성치(

)인 0.85보다 낮은 값이다. 그러나, 도 5의 A 부분과 같이 일부 파괴인성치(

)가 0.5보다 낮은 것으로 볼 때, 퓨즈용 폴리실리콘막에 크랙 발생 가능성이 충분히 있으며 실제 크랙 발생은 웨이퍼 전면이 아닌 일부 포인트(point)에서 일어나고 있다.Stress concentration of polysilicon film for fuse (

) Is about 0.43, the average fracture toughness of polysilicon film for fuse (

) Is lower than 0.85. However, as shown in part A of FIG. 5, some fracture toughness values (

) Is less than 0.5, there is a sufficient possibility of cracking in the polysilicon film for the fuse and the actual cracking occurs at some point, not the front of the wafer.

Cracks generated in the fuse are tensile mode cracks generated by the compressive stress of the PETEOS oxide films 10 and 12 of the lower and upper portions and the tensile stress of the polysilicon film 11 for the fuse itself.

Accordingly, in the present invention, instead of the PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate) oxide film having a compressive stress, an insulating film having a tensile stress or an insulating film having a low compressive stress is used to reduce the compressive stress applied to the polysilicon film for fuse or In order to prevent the occurrence of cracks by forming a polysilicon film for the fuse and then performing a heat treatment process to reduce the tensile stress of the polysilicon film for the fuse itself.

First Embodiment

Figure 6a to Figure 6c is a low-pressure nitride film (LP nitride), a low pressure TEOS oxide film and a TEOS O _3, respectively: a graph showing the (HARP High Aspect Ratio Planarization) Stress hysteresis (stress hysteresis) about the temperature of the oxide film.

6A to 6C, the low pressure nitride film and the low pressure TEOS oxide film at room temperature have stress values of + 1.0E10dyn / cm 2 and + 3.0E9dyn / cm 2, respectively, and are in a tensile stress state.

In addition, the O ₃ TEOS (HARP) oxide film has a stress value of -1.0E08dyn / cm 2, and has a lower compressive stress than the compressive stress state or the PETEOS oxide film.

Therefore, in the first embodiment of the present invention, at least one of the upper insulating film and the lower insulating film formed on and under the polysilicon film for fuse may be formed of a low pressure TEOS (Tetra Ethyl Ortho Silicate) oxide film, a low pressure nitride film, and an O ₃ TEOS oxide film. It is formed to include at least one to relieve the stress applied to the polysilicon film for the fuse.

)를 나타낸다.Table 2 shows the stress concentration applied to the polysilicon film for fuse when the existing upper PETEOS oxide film is replaced with the low pressure nitride film.

).

Thickness Stress (dyn / ㎠) Kc (Mpa-m ^0.5 ) Low pressure nitride film 2000 + 1.00E + 10 0.653 Polysilicon Film for Fuse 1500 -3.00E + 09 -0.170 Bottom PETEOS oxide 18000 -1.00E + 09 -0.196 0.287

As the low pressure nitride film is applied instead of the upper PETEOS oxide film, the compressive stress applied to the polysilicon film for the fuse is completely solved, and the tensile stress (0.287) of the value smaller than the conventional compressive stress (0.431) is applied to the polysilicon film for the fuse.

)를 나타낸다. Table 3 shows the stress concentration applied to the polysilicon film for fuse when the existing upper PETEOS oxide film is replaced with a low pressure TEOS oxide film.

).

Thickness Stress (dyn / ㎠) Kc (Mpa-m ^0.5 ) Low pressure TEOS oxide 2000 + 3.00E + 09 0.196 Polysilicon Film for Fuse 1500 -3.00E + 09 -0.170 Bottom PETEOS oxide 18000 -1.00E + 09 -0.196 -0.170

By applying the low pressure TEOS oxide film instead of the upper PETEOS oxide film, the compressive stress applied to the polysilicon film for fuse was relaxed from 0.431 to 0.170.

)를 나타낸다. Table 4 shows the stress concentration applied to the polysilicon film for fuse when the existing upper PETEOS oxide film is replaced with a laminated film of PETEOS oxide film and low pressure nitride film.

).

Thickness Stress (dyn / ㎠) Kc (Mpa-m ^0.5 ) Low pressure nitride film 1000 1.00E + 10 0.462 PETEOS oxide 1000 -1.00E + 09 -0.046 Polysilicon Film for Fuse 1500 -3.00E + 09 -0.170 Bottom PETEOS oxide 18000 -1.00E + 09 -0.196 0.050

As the PETEOS oxide film and the low pressure nitride film were laminated instead of the upper PETEOS oxide film, the compressive stress applied to the polysilicon film for fuse was completely solved, and the tensile stress of the polysilicon film for fuse was smaller than the conventional compressive stress (0.431). 0.050) is applied.

)를 나타낸다. Table 5 shows the stress concentration applied to the polysilicon film for fuse when the existing upper PETEOS oxide film is replaced with O ₃ TEOS oxide film.

).

Thickness Stress (dyn / ㎠) Kc (Mpa-m ^0.5 ) O ₃ TEOS oxide 2000 -1.00E + 08 -0.007 Polysilicon Film for Fuse 1500 -3.00E + 09 -0.170 Bottom PETEOS oxide 18000 -1.00E + 09 -0.196 -0.372

By applying O ₃ TEOS oxide instead of the upper PETEOS oxide, the compressive stress applied to the polysilicon film for fuse was relaxed from 0.431 to 0.372.

)를 나타낸다. Table 6 shows the stress concentration applied to the polysilicon film for fuse when the existing lower PETEOS oxide film is replaced with O ₃ TEOS oxide film.

).

Thickness Stress (dyn / ㎠) Kc (Mpa-m ^0.5 ) Top PETEOS oxide 2000 -1.00E + 09 -0.046 Polysilicon Film for Fuse 1500 -3.00E + 09 -0.170 O ₃ TEOS oxide 18000 -1.00E + 08 -0.020 -0.235

By applying O ₃ TEOS oxide instead of the lower PETEOS oxide, the compressive stress applied to the polysilicon film for fuse was relaxed from 0.431 to 0.235.

)를 나타낸다. Table 7 shows the stress concentration applied to the polysilicon film for fuse when the lower and upper PETEOS oxide films are replaced with O ₃ TEOS oxide films.

).

Thickness Stress (dyn / ㎠) Kc (Mpa-m ^0.5 ) O ₃ TEOS oxide 2000 -1.00E + 08 -0.007 Polysilicon Film for Fuse 1500 -3.00E + 09 -0.170 O ₃ TEOS oxide 18000 -1.00E + 08 -0.020 -0.196

Compressive stress applied to the polysilicon film for fuse was relaxed from 0.431 to 0.196 by applying the O ₃ TEOS oxide film instead of the lower and upper PETEOS oxide films.

According to Tables 2 to 7, above, one or more insulating films of the upper insulating film and the lower insulating film formed on the upper and lower portions of the polysilicon film for the fuse as in the first embodiment of the present invention are low-pressure TEOS (Tetra Ethyl Ortho Silicate) When at least one of an oxide film, a low pressure nitride film, and an O ₃ TEOS oxide film is formed, the stress applied to the polysilicon film for fuse is reduced.

Second Embodiment

A second embodiment of the present invention proposes a method for reducing the tensile stress of polysilicon for fuses themselves.

The cause of the tensile stress in the polysilicon film for the fuse is due to shrinkage caused by a subsequent thermal process. In order to reduce the shrinkage, a heat treatment process is performed immediately after deposition of the polysilicon film for the fuse.

That is, a polysilicon film for fuse is deposited on the semiconductor substrate on which the lower insulating film is formed. In this case, in order to minimize the shrinkage of the polysilicon film for the fuse, it is preferable to deposit the polysilicon film for the fuse using physical vapor deposition without using a furnace.

In addition, it is preferable to increase the bias power to 0.5 to 2 kW when depositing the polysilicon film for the fuse so that the polysilicon film for the fuse has a compressive stress, and WO _x , Mo _x , TaO _x, etc., when depositing the polysilicon film for the fuse. Likewise, it is preferable to deposit together a high temperature oxide film having a low specific resistance and low thermal expansion.

Then, a heat treatment process is performed to minimize shrinkage of the polysilicon film for the fuse.

The heat treatment step is carried out for 30 to 120 minutes in an argon gas atmosphere of 500 ~ 800 ℃. At this time, the flow rate of the argon gas is 0.5 to 5 slm.

Thereafter, an upper insulating film is formed on the polysilicon film for the fuse to complete the manufacture of the fuse according to the second embodiment of the present invention.

The present invention has the following effects.

First, it is possible to reduce the stress applied to the polysilicon film for the fuse can reduce the occurrence of cracks in the fuse.

Second, since the repair can be performed smoothly by reducing the fuse crack, the yield of the device can be improved.

Claims (8)

In order to alleviate the compressive stress applied to the polysilicon film for a fuse, at least one of an upper insulating film and a lower insulating film formed on and under the polysilicon film for a fuse may be a low pressure TEOS (Tetra Ethyl Ortho Silicate) oxide film, a low pressure nitride film, and A method of manufacturing a fuse of a semiconductor device, comprising forming at least one of an O ₃ TEOS oxide film. Providing a semiconductor substrate having a lower insulating film formed thereon; Depositing a polysilicon film for a fuse on the lower insulating film; Performing a heat treatment process to relieve stress of the polysilicon film for the fuse;  And forming an upper insulating film on the fuse polysilicon film. The method of claim 2, The heat treatment process is a fuse manufacturing method of a semiconductor device, characterized in that performed for 30 to 120 minutes at 500 ~ 800 ℃. The method of claim 2, The heat treatment process is carried out in an argon gas atmosphere having a flow rate of 0.5 ~ 5 slm, characterized in that the fuse manufacturing method of the semiconductor device. The method of claim 2, The fuse manufacturing method of the semiconductor device, characterized in that for depositing the polysilicon film for the fuse by physical vapor deposition. The method of claim 4, wherein And a bias power is set at 0.5 to 2 kW during the deposition of the polysilicon film for the fuse. The method of claim 4, wherein The fuse manufacturing method of the semiconductor device, characterized in that to deposit a high temperature oxide when the polysilicon film for the fuse. The method of claim 7, wherein The high temperature oxide is WO _x , MoO _x , TaO _x , characterized in that the fuse manufacturing method of the semiconductor device.

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