KR100739197B1 - Deinterleaving apparatus in digital audio broadcasting - Google Patents

Abstract

The present invention provides a control unit for outputting a length determination signal of data stored in a memory and each control signal according to a mode selection signal input from an external device; An address generator for generating and outputting a corresponding address according to a mode selection signal input from the outside; A first demultiplexer which receives symbol data and determines a length of the input data according to a control signal output from the controller, and optionally stores the length of the input data in a first or second memory; A second demultiplexer for selectively outputting an address output from the address generator to a first or second memory according to a control signal of the controller; First and second memories for storing input data output from the first demultiplexer and then outputting data values rearranged by addresses output from the second demultiplexer; And a multiplexer for selectively outputting rearranged data stored in the first or second memory according to the control signal. Accordingly, the present invention not only uses a lookup table memory for frequency deinterleaving address generation, but also simplifies the multiplier processing of the required computational structure for each mode, and also uses a clock required internally in the DAB system. The advantage is that the hardware area can be reduced by simplification.

Description

Frequency deinterleaving device in digital audio broadcasting {DEINTERLEAVING APPARATUS IN DIGITAL AUDIO BROADCASTING}

1 is a diagram illustrating frequency deinterleaving for transmission modes according to the prior art.

Figure 2 is a block diagram of a frequency deinterleaving apparatus using a look-up table according to the prior art.

3 is a block diagram of a frequency deinterleaving apparatus incorporating a lookup table and a transmission mode calculation according to the related art.

4 is a block diagram of a frequency deinterleaving apparatus in digital audio broadcasting according to the present invention;

FIG. 5 is a detailed configuration diagram of the address generator of FIG. 4. FIG.

*** Explanation of symbols on main parts of drawing ***

30: Control Block

31: Address Generator

32, 33: 1st, 2nd demultiplexer 34, 35: 1st, 2nd memory

36: Multiplexer

The present invention relates to a frequency deinterleaving apparatus, and more particularly, to a frequency deinterleaving apparatus for digital audio broadcasting in which an architecture of a frequency deinterleaver necessary for the configuration of a transmitter and a receiver using an OFDM scheme in digital audio broadcasting is more efficiently designed. will be.

The frequency deinterleaver in the Eureka-147 DAB defines the ability to rearrange digital signals to each carrier using the characteristics of OFDM, which uses multiple carriers, to reduce the effects of selective fading in order to improve the reception quality while moving. The receiver must deinterleave data processed in units of one OFDM symbol according to each mode.

(i)값 중 각 모드에 정해진 유효한 범위에 존재하는 값을 d_n으로 정의하고 k=F(n)=d_n-1024(예; 모드 1)로 결정되는 k값에 의하여 전송되어진 데이터를 디인터리빙한다.In order to process for each mode here, as shown in FIG.

(i) Defines the value existing in the valid range defined in each mode as d _n and decodes the data transmitted by the k value determined by k = F (n) = d _n -1024 (eg mode 1). Interleaving

In general, it is first stored in memory in OFDM symbol units and rearranged by a predetermined pattern. Since the required calculation method is different depending on the mode and the form is not general, in hardware implementation, four address generators are calculated separately. Implemented in logic to read data from a given address.                         

In addition, instead of implementing each hardware for the four modes, it is possible to store and use the result values obtained by calculating four calculation processes in advance in a lookup table.

In addition, two mixed methods are used to store the result in the lookup table based on the longest mode of OFDM symbol data, and to obtain the remaining modes 2, 3, and 4 by using a correlation between them. There is this.

First, a method of using a lookup table will be described with reference to FIG. 2.

In each mode, the lookup table that stores only the actual addresses among the result values calculated by each operation is recorded in a separate memory or register, and this mode is used in the memory where the received data is stored according to the control signal using the address generator. A method of deinterleaving outputs in order of addresses determined by different lookup tables.

Next, a method of mixing the lookup table and the calculation circuit will be described.

By using a combination of the two existing methods, all addresses are stored in the lookup table for Mode 1, which basically requires the most addresses, but for the other modes 2-4, the addresses in Mode 1 are reused and do not exist. It is a way to store only the values that do not.

Therefore, the structure of the lookup table is slightly different from the above method.

In order to store additional address values corresponding to mode 1, a total of 1536 * 11 ROMs is required. The range of [0, 2047] corresponds to [256, 1792].                         

In order to store the addresses corresponding to the remaining modes together, 1793 * 11 ROMs corresponding to [0, 1792] are required. When the address is in mode 1, the addresses can be read sequentially until [256, 1792]. The address corresponding to the modes 2 to 4 needs to be additionally hardware-processed for this part extracted using the equation shown in the following equation, and the structure thereof is referred to in FIG. 3.

mod 512

mod 512

mod 256

mod 256

mod 1024

mod 1024

However, the method using the lookup table requires a considerable amount of hardware resources as a whole, because it requires 1536 * 11, 384 * 11, 192 * 11, and 768 * 11 ROMs to deinterleave all modes. To occupy.

In addition, in the case of the blending method of the lookup table, there is a side to reduce the above disadvantages, but also requires a ROM of 1793 * 11, and to calculate the newly added expression to support the modes 2, 3, 4 There is a disadvantage that the hardware implementation must be implemented. However, since there is no relationship between them, the efficiency is inferior, and it is complicated because the modular operation must be performed again to know the address value corresponding to the actual mode 2-4 with the result value.

Accordingly, an object of the present invention is to provide a frequency deinterleaving apparatus for digital audio broadcasting that does not use a lookup table memory and implements a required calculation structure for each mode.

One embodiment of the present invention for achieving the above object is a control unit for outputting a length determination signal and each control signal of the data stored in the memory in accordance with the mode selection signal input from the outside; An address generator for generating and outputting a corresponding address according to a mode selection signal input from the outside; A first demultiplexer which receives symbol data and determines a length of the input data according to a control signal output from the controller, and optionally stores the length of the input data in a first or second memory; A second demultiplexer for selectively outputting an address output from the address generator to a first or second memory according to a control signal of the controller; First and second memories for storing input data output from the first demultiplexer and then outputting data values rearranged by addresses output from the second demultiplexer; And a multiplexer for selectively outputting rearranged data stored in the first or second memory according to the control signal.

Hereinafter, with reference to the accompanying drawings an embodiment according to the present invention will be described in detail.

4 is a block diagram illustrating the entire structure of a frequency deinterleaving apparatus in digital audio broadcasting according to the present invention.

Referring to FIG. 4, the frequency deinterleaving apparatus for digital audio broadcasting according to the present invention includes a control unit 30 for outputting a length determination signal of data stored in a memory and each control signal according to a mode selection signal input from an external device. ; An address generator 31 for generating and outputting a corresponding address according to a mode selection signal input from the outside; A first demultiplexer (32) which receives symbol data and determines a length of the input data according to a control signal output from the controller (30) and optionally stores the length of the input data in a first or second memory; A second demultiplexer (33) for selectively outputting an address output from the address generator (31) to a first or second memory in accordance with a control signal of the controller; First and second memories 34 and 35 which store input data output from the first demultiplexer 32 and output rearranged data values by addresses output from the second demultiplexer 33; ; And a multiplexer 36 for selectively outputting rearranged data stored in the first or second memory in accordance with the control signal.

The main characteristic of a frequency deinterleaver depends on how it extracts the location of the data rearrangement for that mode.

When analyzing the rearrangement positions of the four modes distinguished according to the type of input data, the maximum number of iterations from the correct output value to the next output value in the entire operation is 7 when the mode 1 is used.

Therefore, the clock required for the implementation of the frequency deinterleaver uses a clock that is eight times faster than the transmission data rate required to store the input data in memory. This clock is considered internally in consideration of the operation of other modules in the overall DAB system. This is the clock used in.

In order to implement each operation equation in hardware, the present invention proposes an address generator 31 as shown in FIG.

Referring to FIG. 5, the address generator 31 replaces a multiplier using a shift register and an adder and variably operates an addition constant value according to four modes according to a change of mode.

In order to check whether the address value thus created is in the correct range, the comparison value of the comparator block for determining the range according to the current mode value is variably processed.

를 구하기 위한

값으로 사용한다.As a result, after knowing the state of the corresponding arithmetic output value, if the output value does not fall within the range, the on time block

To save

Use as a value.

When it is determined that the desired output value is obtained through this repetitive operation, the on time block counts the current clock and maintains it until it is time to deinterleave the actual input transmission data.

The operation description in the frequency deinterleaving apparatus configured as described above is as follows.

The input QPSK symbol input data is first stored in memory for frequency deinterleaving. The length of the QPSK symbol input data is determined variably according to the mode, and is output as a rearranged data value by the address generator 31. At the same time, the input data is processed next time. Is stored in memory.

The controller 30 determines the length of data stored in the memory according to the type of the mode input from the outside, controls the input / output signal, and is in charge of the variable operation and output of the address generator.

The present invention is not limited to the embodiments described above, and various modifications and changes can be made by those skilled in the art, which are included in the spirit and scope of the present invention as defined in the appended claims.

As described above, the present invention does not use a lookup table memory for generating frequency deinterleaving addresses, and simplifies the multiplier processing even in the implementation of a required calculation structure for each mode, compared to the conventional methods.

In addition, by using the clock required internally in the DAB system, the frequency deinterleaver structure can be simplified to reduce the hardware area.

Claims (1)

A controller for outputting a length determination signal of data stored in a memory and each control signal according to a mode selection signal input from an external device; An address generator for generating and outputting a corresponding address according to a mode selection signal input from the outside; A first demultiplexer which receives symbol data and determines a length of the input data according to a control signal output from the controller, and optionally stores the length of the input data in a first or second memory; A second demultiplexer for selectively outputting an address output from the address generator to a first or second memory according to a control signal of the controller; First and second memories for storing input data output from the first demultiplexer and then outputting data values rearranged by addresses output from the second demultiplexer; And a multiplexer for selectively outputting rearranged data stored in the first or second memory according to the control signal.

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