KR100734663B1 - Method for pad open in semicoductor device - Google Patents

Method for pad open in semicoductor device Download PDF

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KR100734663B1
KR100734663B1 KR1020050131634A KR20050131634A KR100734663B1 KR 100734663 B1 KR100734663 B1 KR 100734663B1 KR 1020050131634 A KR1020050131634 A KR 1020050131634A KR 20050131634 A KR20050131634 A KR 20050131634A KR 100734663 B1 KR100734663 B1 KR 100734663B1
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pad
photosensitive
film
forming
oxide film
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KR1020050131634A
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Korean (ko)
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권산무
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A pad open method of a semiconductor device is provided to economize the costs for a pad open process by simplifying the pad open process using a photo sensitive nitride layer as a hard mask for the pad open process. An oxide layer(22) is formed on a final metal line(21). A photo sensitive nitride layer(23) is formed on the oxide layer. A pad pattern is formed on the photo sensitive nitride layer by using a photo mask. A bonding region of the final metal line is opened by etching selectively the oxide layer using the photo sensitive nitride layer as a hard mask. At this time, the bonding region opening process is performed by using a dry etching process on the oxide layer.

Description

반도체소자의 패드 오픈 방법{METHOD FOR PAD OPEN IN SEMICODUCTOR DEVICE}METHOD FOR PAD OPEN IN SEMICODUCTOR DEVICE

도 1은 종래 기술에 따른 패드 오픈 방법을 도시한 도면,1 is a view showing a pad opening method according to the prior art,

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 반도체소자의 패드 오픈 방법을 도시한 도면.2A to 2D are diagrams illustrating a pad opening method of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 최종 메탈배선 22 : 산화막21: final metal wiring 22: oxide film

23 : 광 감응성 질화막 24 : P/O 마스크23 photosensitive nitride film 24 P / O mask

25 : 패드 패턴25: pad pattern

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체소자의 패드 오픈 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of opening a pad of a semiconductor device.

일반적으로 패드 오픈(Pad open) 공정이라 함은 최종 메탈배선(Final metal line) 형성 후에 와이어 본딩(Wire bonding)이 이루어지는 부분을 오픈시키는 공정이다.In general, a pad open process is a process of opening a portion where wire bonding is performed after the final metal line is formed.

도 1은 종래 기술에 따른 패드오픈 방법을 도시한 도면이다.1 is a diagram illustrating a pad opening method according to the prior art.

도 1을 참조하면, 최종 메탈배선(11)을 형성한 후, 증착 공정을 순차 실시하여 최종 메탈배선(11) 상에 산화막(12)과 질화막(13)의 이중층으로 된 보호막을 형성한다.Referring to FIG. 1, after the final metal wiring 11 is formed, a deposition process is sequentially performed to form a protective film formed of a double layer of an oxide film 12 and a nitride film 13 on the final metal wiring 11.

이어서, 도포 공정을 진행하여 보호막 상에 감광막(PR)을 도포한 후 노광 및 현상으로 패터닝하여 패드 마스크를 형성한다.Subsequently, the coating process is performed to apply the photosensitive film PR on the protective film, and then patterned by exposure and development to form a pad mask.

이어서, 패드 마스크를 식각 마스크로 하는 식각 공정을 실시하여 보호막의 일부를 선택 식각함으로써 최종 메탈배선(11)의 본딩 예정지역을 오픈한다. 이상의 공정을 패드오픈 공정이라고 하며, 보호막 식각 공정을 패드 식각(Pad etch) 공정이라고 한다.Subsequently, an etching process using the pad mask as an etching mask is performed to selectively etch a part of the protective film to open the bonding scheduled region of the final metal wiring 11. The above process is called a pad-open process, and the protective film etching process is called a pad etch process.

위와 같은 패드 오픈 공정은 임계치수(Critical Dimension; CD) 관리가 필요한 임계 공정이 아니므로 공정 단순화가 요구된다.The pad open process as described above is not a critical process requiring critical dimension (CD) management and thus requires a simplified process.

그러나, 종래 기술은 감광막 도포, 노광 및 현상을 통한 패드마스크 형성, 패드 식각 공정을 거치는 등 패드오픈 공정이 매우 복잡하여 비용이 증가하는 문제가 있다.However, the prior art has a problem in that the cost of the pad opening process is very complicated, such as through the photosensitive film coating, the formation of the pad mask through exposure and development, the pad etching process.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위한 것으로, 공정을 단순화시켜 비용을 절감할 수 있는 반도체소자의 패드 오픈 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to provide a method of opening a pad of a semiconductor device which can reduce costs by simplifying a process.

상기 목적을 달성하기 위한 본 발명의 반도체소자의 패드 오픈 방법은 패드 용 최종 메탈배선을 형성하는 단계와, 상기 최종 메탈배선 상부에 산화막을 형성하는 단계와, 상기 산화막 상에 광 감응성막을 형성하는 단계와, 상기 광 감응성막에 패드 패턴을 전사하는 단계와, 상기 광 감응성막을 하드 마스크로 하여 상기 패드 패턴 아래의 산화막을 식각하여 상기 최종 메탈배선의 본딩 예정지역을 오픈시키는 단계를 포함하는 것을 특징으로 하며, 상기 광 감응성막은 광 감응성 질화막으로 형성하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of opening a pad of a semiconductor device, forming a final metal wiring for a pad, forming an oxide film on the final metal wiring, and forming a photosensitive film on the oxide film. And transferring a pad pattern to the photosensitive film, and etching the oxide film under the pad pattern using the photosensitive film as a hard mask to open a bonding area of the final metal wiring. The photosensitive film is formed of a photosensitive nitride film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시 예를 첨부 도면을 참조하여 설명한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 반도체소자의 패드오픈 방법을 도시한 도면이다.2A to 2D are diagrams illustrating a pad opening method of a semiconductor device according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 와이어 본딩이 진행될 패드용 최종 메탈배선(Final metal line, 21)을 형성한 후, 증착 공정을 실시하여 최종 메탈배선(21) 상에 산화막(22)을 형성한다.As shown in FIG. 2A, after forming a final metal line 21 for pads to be wire bonded, an oxide layer 22 is formed on the final metal line 21 by performing a deposition process.

다시, 증착 공정을 실시함으로써, 산화막(22) 상에 광 감응성 질화막(Photosensitive nitride, 23)을 형성한다.Again, by performing the vapor deposition process, a photosensitive nitride film 23 is formed on the oxide film 22.

도 2b에 도시된 바와 같이, 패드 패턴이 형성된 포토 마스크, 즉 P/O 마스크(24)를 이용한 노광(Exposure) 공정을 실시함으로써, 이러한 노광 공정에 의해 광 감응성 질화막(23)에 패드패턴(25)이 전사된다. 이때, 노광은 부분 노광으로 진행한다.As shown in FIG. 2B, by performing an exposure process using a photomask having a pad pattern, that is, a P / O mask 24, the pad pattern 25 is applied to the photosensitive nitride film 23 by such an exposure process. ) Is transferred. At this time, the exposure proceeds to partial exposure.

도 2c는 노광 후에 광 감응성 질화막(23)에 전사된 패드 패턴(25)을 도시한 도면이다. 이때, 패드 패턴(25)은 광 감응성 질화막(23)을 완전히 관통하는 형태가 아니다. 이는 상기 노광 공정시에 부분 노광을 진행함으로써 가능하며, 부분 노광하는 이유는 완전 노광(Full exposure)에 의해 광 감응성 질화막(23) 하부의 산화막이 어택받는 것을 방지하기 위함이다. 이상의 패드 패턴(25)을 형성하는 공정을 질화막 패드 오픈(Nitride pad open) 공정이라고 한다.FIG. 2C shows the pad pattern 25 transferred to the photosensitive nitride film 23 after exposure. In this case, the pad pattern 25 does not completely penetrate the photosensitive nitride film 23. This is possible by performing partial exposure during the exposure process, and the reason for partial exposure is to prevent the oxide film under the photosensitive nitride film 23 from being attacked by full exposure. The process of forming the pad pattern 25 mentioned above is called a nitride pad open process.

다음으로, 도 2d에 도시된 바와 같이, 광 감응성 질화막(23)을 하드 마스크로 이용하여 패드 식각 공정을 진행한다. 즉, 광 감응성 질화막(23)의 패드 패턴(25) 아래의 나머지 광 감응성 질화막과 산화막(22)을 순차 식각함으로써 최종 메탈배선(21)의 본딩 예정지역을 개방시키는 패드 오픈 공정을 진행한다. 이때, 패드 오픈 공정은 건식 식각(Dry etch)으로 진행하며, 산화막(22) 식각시 질화막 물질인 광 감응성 질화막(23)은 선택비를 가져 하드 마스크로서 충분히 그 역할을 한다. Next, as shown in FIG. 2D, the pad etching process is performed using the photosensitive nitride film 23 as a hard mask. That is, by sequentially etching the remaining photosensitive nitride film and the oxide film 22 under the pad pattern 25 of the photosensitive nitride film 23, the pad opening process of opening the bonding scheduled region of the final metal wiring 21 is performed. In this case, the pad opening process may be performed by dry etching, and the photosensitive nitride layer 23, which is a nitride layer material during etching of the oxide layer 22, may have a selectivity to sufficiently serve as a hard mask.

상술한 실시 예에 따르면, 패드 오픈 공정을 위한 하드 마스크로서 광 감응성질화막을 이용함에 따라 패드 오픈 공정을 단순화시킬 수 있다. 즉 감광막 도포 공정, 노광 공정, 현상 공정 및 애싱 공정을 진행하지 않아도 되어 공정이 매우 단순해진다.According to the above-described embodiments, the pad opening process may be simplified by using the photosensitive nitride film as a hard mask for the pad opening process. In other words, the photosensitive film coating step, the exposure step, the developing step, and the ashing step do not have to be performed.

한편, 상술한 실시 예에서는 하드 마스크로 사용되는 물질을 광 감응성 질화막을 예로 들었으나, 본 발명의 패드 오픈 공정시 광 감응성 성질을 갖고 식각 선택비가 높은 물질로도 적용이 가능하다.Meanwhile, in the above-described embodiment, the material used as the hard mask is exemplified by the photosensitive nitride film, but it is also applicable to a material having a photosensitive property and a high etching selectivity in the pad opening process of the present invention.

본 발명의 기술 사상은 상기 바람직한 실시 예에 따라 구체적으로 기술되었 으나, 상기한 실시 예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 패드 오픈 공정을 위한 하드 마스크로서 광 감응성 질화막을 이용함에 따라 패드 오픈 공정을 단순화시킬 수 있어 비용을 절감할 수 있는 효과가 있다.The present invention described above can simplify the pad opening process by using the photosensitive nitride film as a hard mask for the pad opening process, thereby reducing the cost.

Claims (5)

삭제delete 패드용 최종 메탈배선을 형성하는 단계와, Forming a final metallization for the pad, 상기 최종 메탈배선 상부에 산화막을 형성하는 단계와, Forming an oxide film on the final metal wiring; 상기 산화막 상에 광 감응성 질화막으로 된 광 감응성막을 형성하는 단계와, Forming a photosensitive film made of a photosensitive nitride film on the oxide film; 상기 광 감응성막에 패드 패턴을 전사하는 단계와, Transferring a pad pattern to the photosensitive film; 상기 광 감응성막을 하드 마스크로 하여 상기 패드 패턴 아래의 산화막을 식각하여 상기 최종 메탈배선의 본딩 예정지역을 오픈시키는 단계 Etching the oxide film under the pad pattern using the photosensitive film as a hard mask to open a bonding area of the final metal wiring; 를 포함하는 반도체소자의 패드 오픈 방법.Pad opening method of a semiconductor device comprising a. 패드용 최종 메탈배선을 형성하는 단계와, Forming a final metallization for the pad, 상기 최종 메탈배선 상부에 산화막을 형성하는 단계와, Forming an oxide film on the final metal wiring; 상기 산화막 상에 광 감응성막을 형성하는 단계와, Forming a photosensitive film on the oxide film; 패드 패턴이 형성된 포토 마스크를 이용하여 상기 광 감응성막에 패드 패턴을 전사하는 단계와, Transferring a pad pattern to the photosensitive film by using a photomask having a pad pattern formed thereon; 상기 광 감응성막을 하드 마스크로 하여 상기 패드 패턴 아래의 산화막을 식각하여 상기 최종 메탈배선의 본딩 예정지역을 오픈시키는 단계 Etching the oxide film under the pad pattern using the photosensitive film as a hard mask to open a bonding area of the final metal wiring; 를 포함하는 반도체소자의 패드 오픈 방법.Pad opening method of a semiconductor device comprising a. 제 3 항에 있어서,The method of claim 3, wherein 상기 노광은, 부분 노광으로 진행하는 것을 특징으로 하는 반도체소자의 패드 오픈 방법.The exposure is performed by partial exposure. The method of opening a pad of a semiconductor device. 패드용 최종 메탈배선을 형성하는 단계와, Forming a final metallization for the pad, 상기 최종 메탈배선 상부에 산화막을 형성하는 단계와, Forming an oxide film on the final metal wiring; 상기 산화막 상에 광 감응성막을 형성하는 단계와, Forming a photosensitive film on the oxide film; 상기 광 감응성막에 패드 패턴을 전사하는 단계와, Transferring a pad pattern to the photosensitive film; 상기 광 감응성막을 하드 마스크로 하여 상기 패드 패턴 아래의 산화막을 건식 식각하여 상기 최종 메탈배선의 본딩 예정지역을 오픈시키는 단계 Dry etching the oxide film under the pad pattern by using the photosensitive film as a hard mask to open a bonding area of the final metal wiring; 를 포함하는 반도체소자의 패드 오픈 방법.Pad opening method of a semiconductor device comprising a.
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US9829795B2 (en) 2014-09-05 2017-11-28 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices with flattened hardmask layers
CN113867043A (en) * 2020-06-30 2021-12-31 京东方科技集团股份有限公司 Light-emitting substrate, preparation method thereof and display device

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JPH098078A (en) * 1995-06-16 1997-01-10 Matsushita Electron Corp Forming method of pad for lead-out
JP2004273769A (en) * 2003-03-10 2004-09-30 Nec Kansai Ltd Passivation structure of semiconductor and its manufacturing method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098078A (en) * 1995-06-16 1997-01-10 Matsushita Electron Corp Forming method of pad for lead-out
JP2004273769A (en) * 2003-03-10 2004-09-30 Nec Kansai Ltd Passivation structure of semiconductor and its manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9829795B2 (en) 2014-09-05 2017-11-28 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices with flattened hardmask layers
US10503072B2 (en) 2014-09-05 2019-12-10 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices with flattened hardmask layers
CN113867043A (en) * 2020-06-30 2021-12-31 京东方科技集团股份有限公司 Light-emitting substrate, preparation method thereof and display device
CN113867043B (en) * 2020-06-30 2023-01-10 京东方科技集团股份有限公司 Light-emitting substrate, preparation method thereof and display device

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