KR100733463B1 - Semiconductor device and method for fabrication thereof - Google Patents

Abstract

The present invention provides a semiconductor device and a method of manufacturing the same, which prevents the phenomenon of etching the interlayer insulating film and the plug by infiltrating the lower portion of the lower electrode when the capacitor sacrificial insulating film is formed in the deep-out process to form a cylindrical capacitor To this end, the present invention for this purpose, is disposed to have a predetermined opening to expose the lower conductive region through the opening; A conductive film filling the open part and electrically connected to the conductive area; And a capacitor lower electrode disposed on the conductive layer, wherein the insulating layer has a first fence at the top thereof to prevent attack of the chemical penetrating through the defect of the capacitor lower electrode, and the first fence and It provides a semiconductor device comprising a spacer-shaped second fence surrounding the side wall of the insulating film forming the open portion.

In addition, the present invention includes an insulating film disposed to have a predetermined open portion to expose a lower conductive region through the open portion; A conductive film filling the open part and electrically connected to the conductive area; And a capacitor lower electrode disposed on the conductive layer, wherein the insulating layer has a first fence in the middle thereof to prevent attack of the chemical penetrating through the defect of the capacitor lower electrode, and forms an open portion. It provides a semiconductor device comprising a spacer-shaped second fence surrounding the side wall of the.

Capacitors, sacrificial insulating films, fences, spacers, contact plugs for storage nodes, cylinders.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATION THEREOF}             

1A to 1D are cross-sectional views showing a cylindrical capacitor forming process according to the prior art.

2 is a cross-sectional view for explaining the attack of the interlayer insulating film through the defect of the lower electrode.

3 is a cross-sectional view for explaining the attack of the interlayer insulating film through poor deposition of the conductive film for the lower electrode due to the particles.

4 is a cross-sectional view for explaining the attack of the interlayer insulating film due to the poor step coverage of the conductive film for the lower electrode;

5 is a plan view schematically showing a semiconductor device of the present invention in which a capacitor is formed.

FIG. 6 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention taken along the line a-a 'in FIG. 5. FIG.

FIG. 7 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the present invention taken along the line b-b ′ of FIG. 5.                 

8 is a cross-sectional view illustrating a semiconductor device in accordance with another embodiment of the present invention taken along the line a-a 'of FIG. 5.

FIG. 9 is a cross-sectional view of a semiconductor saw according to another exemplary embodiment of the present invention taken along the line b-b 'in FIG. 5; FIG.

10A to 10D are cross-sectional views illustrating a semiconductor device manufacturing process corresponding to FIGS. 6 and 7.

11A to 11D are cross-sectional views illustrating a semiconductor device manufacturing process corresponding to FIGS. 8 and 9.

Explanation of symbols on the main parts of the drawings

100 substrate 104 impurity diffusion region

106: first insulating film 107: cell contact plug

108: first etching stop film 109: second insulating film

110: conductive film 111: insulating hard mask

112 spacer 113 third insulating film

114: first fence 117: second fence

121: lower electrode 122: dielectric film

123: upper electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of suppressing occurrence of defects due to wet attack of a sacrificial insulating film for a capacitor.

The area occupied by the capacitor is decreasing with high integration, miniaturization and high speed of the semiconductor device. Even if the semiconductor device is highly integrated and miniaturized, the capacitance of the capacitor for driving the semiconductor device should be secured at least.

As a way to secure the capacitance of the capacitor, the lower electrode of the capacitor is formed in various structures such as cylinder structure, stack structure, pin structure, and concave structure, thereby limiting The effective surface area of the capacitor lower electrode is maximized.

Among them, the cylinder structure can secure the largest capacitance as a three-dimensional structure.

1A to 1D are cross-sectional views illustrating a cylindrical capacitor forming process according to the prior art, and looks at the conventional cylindrical capacitor forming process with reference to this.

First, as shown in FIG. 1A, an interlayer insulating film 11 is formed on a semiconductor substrate 10 on which various elements for forming semiconductor devices such as wells and transistors are formed.

When the interlayer insulating film 11 is used as an oxide-based material film, a BSG (Boro Silicate Glass) film, BPSG (Boro Phospho SIlicate Glass) film, PSG film, TEOS film, HDP (High Density Plasma) oxide film, and SOG (Spin On) A glass film or an advanced planarization layer (APL) film may be used, and an inorganic or organic low dielectric constant film may be used in addition to the oxide film series.

For reference, the gate electrode pattern does not appear in the process cross section here.

Subsequently, the interlayer insulating film 11 is selectively etched to form a contact hole exposing a cell contact plug (not shown). Subsequently, after the conductive film is deposited, a planarization process using an entire surface etch or a CMP is performed to form an interlayer insulating film 11 and a plurality of storage node contact plugs 12 having the planarized and isolated portions thereof.

The contact plug 12 for a storage node includes a configuration in which polysilicon alone or polysilicon is combined with Ti, TiN, Ta, TaN, and the like.

Subsequently, an etch stop layer serves as an etch stop to prevent attack of the storage node contact plug 12 when forming an opening defining a storage node forming region of a subsequent capacitor on the front surface where the storage node contact plug 12 is formed. (13) is formed.

The etch stop film 13 uses a nitride film-based material film such as a silicon nitride film or a silicon oxynitride film.

Subsequently, a sacrificial insulating film 14 for forming a capacitor is formed on the etch stop film 13. As the sacrificial insulating film 14, a conventional oxide film-based material film can be used, and mainly a single structure of TEOS film or a laminated structure of TEOS film / PSG film is used.

Subsequently, a mask pattern 15 defining a storage node contact formation region of the capacitor is formed on the sacrificial insulating layer 14.

The mask pattern 15 usually represents only a photoresist pattern. However, in recent years, as the vertical height of the capacitor increases, the height of the sacrificial insulating layer 14 which determines this increases. Due to the thinner thickness, there is a limit in etching the sacrificial insulating layer 14 only with the photoresist pattern. Therefore, a sacrificial hard mask to be used as an etch barrier is used under the photoresist pattern, the pattern is transferred to the sacrificial hard mask using the photoresist pattern, and then the etched layer and the sacrificial insulating layer 14 are removed using the sacrificial hard mask. Etching forms a desired pattern. As the sacrificial hard mask material, polysilicon, tungsten, a nitride film, and the like are used, and various kinds of sacrificial layers are used.

Subsequently, as shown in FIG. 1B, the sacrificial insulating layer 14 is selectively etched using the mask pattern 15 as an etch mask to expose the etch stop layer 13 on the contact plug 12 for the storage node. (16) is formed.

Here, the open part 16 represents the capacitor formation scheduled area.

In this case, in the case of a conventional DRAM (Dynamic Random Access Memory) process, the etching profile of the open part 16 is aligned on the side of the bit line (not shown), and to secure the margin of the etching process due to the large etching target. An etching process using a self alignment contact (hereinafter referred to as SAC) is applied.

Subsequently, the etch stop layer 13 is removed to expose the storage node contact plug 12.

Subsequently, a cleaning process is performed to remove the etching residue resulting from the formation of the open portion 16 and the interfacial oxide film formed on the bottom surface of the open portion 16. The cleaning process uses a wet method, and chemically uses HF or BOE (Buffered Oxide Etchant).

Subsequently, as illustrated in FIG. 1C, a conductive film for the storage node is deposited along the profile in which the open portion 16 is formed, and is electrically connected to the contact plug 12 for the storage node exposed as the open portion 16 is formed. .

Subsequently, the passivation layer is deposited to fill the empty portion of the open portion 16, and then the bottom electrode 17, that is, the storage node, of the isolated capacitor is subjected to an entire surface etching or CMP process to a target to which the sacrificial insulating layer 14 is exposed. Form.

Here, the conductive film for the lower electrode includes a single or combined configuration of polysilicon, Ti, TiN, Ta, TaN, Ir, IrO ₂ , Ru, RuO ₂ , Pt and the like.

In addition, a barrier film having a single or combined configuration such as Ti, TiN, Ta, TaN, TiSi ₂ , or the like may be formed at an interface between the lower electrode 17 and the contact plug 12 for a storage node. An adhesive layer may be further included between the storage node contact plug 12 and the barrier layer.

Subsequently, as shown in FIG. 1D, after removing the protective film, a dip-out process is performed to remove the sacrificial insulating film 14 so that the lower electrode 17 has a cylindrical structure. In the dip-out process, chemicals such as HF or BOE are used.                         

Subsequently, the dielectric film 18 and the upper electrode 19 are sequentially formed on the lower electrode 17, thereby completing the cell capacitor forming process.

On the other hand, in the dip-out process of the sacrificial insulating film 14 to form the conventional cylindrical capacitor described above, a chemical such as HF or BOE is used as an etchant, and the lower electrode has a defect or a particle or the like. If the lower electrode is not sufficiently deposited in the capacitor structure in which the lower electrode is formed due to the current, a problem occurs that such a chemical flows into the lower portion to etch the lower insulating interlayer 11. For example, when using TiN deposited using a chemical vapor deposition (CVD) method, which is used only as a material of the lower electrode 17, columnar grains having low density of grain boundaries are formed. Because of the grain structure, it is easy to penetrate the solution through the grain boundary. If the lower interlayer insulating film 11 is etched and removed, the chemicals are stored in the space of the etched interlayer insulating film 11 and then the contact plug 12 for the storage node and the sal contact plug below, if severe, during the subsequent thermal process. The substrate 10 is etched to generate a large defect.

Hereinafter, the attack of the interlayer insulating layer due to the chemical during the dip-out process will be described for each type.

2 is a cross-sectional view illustrating an attack of an interlayer insulating film through defects of a lower electrode.

Referring to FIG. 2A, when the lower electrode 17 has a defect as shown by reference numeral 20 in the vicinity of an interface with the storage node contact plug 12, the defects of FIGS. As described above, the chemical penetrates into the defect 20 in the deep-out process for removing the sacrificial insulating layer 14, and the interlayer insulating layer 110 is etched as shown by reference numeral 21.

3 is a cross-sectional view illustrating an attack of an interlayer insulating film due to poor deposition of a conductive film for a lower electrode due to particles.

Referring to (a) of FIG. 3, when a particle is present as shown by reference numeral '22' at the top of the open part after the open part forming process for forming the lower electrode, the lower part is open for the lower electrode in which the particle 22 exists. The conductive film 17 'is not deposited.

At this time, the interlayer insulating film 11 is etched as shown by reference numeral 23 in the deep-out process for removing the sacrificial insulating film 14 as shown in FIG.

4 is a cross-sectional view for explaining the attack of the interlayer insulating film due to the poor step coverage of the conductive film for the lower electrode.

Referring to (a) of FIG. 4, it can be seen that the thickness of the deposited film on the bottom of the open part becomes thinner than the upper part as indicated by '24' due to the increase in the aspect ratio during the deposition of the conductive film for the lower electrode.

At this time, in the deep-out process for removing the sacrificial insulating film 14 as shown in (b) of FIG. 4, the thickness of the conductive film for the lower electrode deposited on the bottom of the open portion is thin, and as shown by reference numeral 25. The interlayer insulating film 11 is etched.

The present invention has been proposed to solve the above problems of the prior art, and when a capacitor sacrificial insulating film is formed in a dip-out process to form a cylinder type capacitor, the chemical penetrates into the lower portion of the lower electrode, such as an interlayer insulating film and a plug. It is an object of the present invention to provide a semiconductor device capable of preventing the etching phenomenon and a manufacturing method thereof.

In order to achieve the above object, the present invention includes an insulating film disposed to have a predetermined open portion to expose a lower conductive region through the open portion; A conductive film filling the open part and electrically connected to the conductive area; And a capacitor lower electrode disposed on the conductive layer, wherein the insulating layer has a first fence at the top thereof to prevent attack of the chemical penetrating through the defect of the capacitor lower electrode, and the first fence and It provides a semiconductor device comprising a spacer-shaped second fence surrounding the side wall of the insulating film forming the open portion.

In addition, to achieve the above object, the present invention is an insulating film disposed to have a predetermined open portion to expose a lower conductive region through the open portion; A conductive film filling the open part and electrically connected to the conductive area; And a capacitor lower electrode disposed on the conductive layer, wherein the insulating layer has a first fence in the middle thereof to prevent attack of the chemical penetrating through the defect of the capacitor lower electrode, and forms an open portion. It provides a semiconductor device comprising a spacer-shaped second fence surrounding the side wall of the.

In addition, to achieve the above object, the present invention comprises the steps of forming a first insulating film on a lower structure including a conductive region; Forming a second insulating layer for forming a first fence on the first insulating layer to prevent attack of the first insulating layer by chemicals through defects in a capacitor lower electrode during a subsequent dip-out process; Selectively etching the second insulating layer and the first insulating layer to form a first open portion exposing the conductive region, wherein the second insulating layer forms a first fence at the top of the first insulating layer; Forming a third insulating layer to form a second fence to prevent attack of the first insulating layer by chemicals through defects in the capacitor lower electrode during a subsequent dip-out process along the profile in which the first opening is formed; Forming a spacer-shaped second fence on the sidewalls of the first insulating film and the first fence forming the open portion by performing an entire surface etching; Filling the first open portion and forming a conductive film substantially planar with the first fence; Forming a sacrificial insulating film for capacitor formation on the conductive film; Selectively etching the sacrificial insulating layer to form a second open portion exposing the conductive layer; Forming a capacitor lower electrode in contact with the conductive layer along the profile of the second open portion; And removing the sacrificial insulating layer by performing a dip-out process so that the capacitor lower electrode has a cylindrical shape.

In addition, to achieve the above object, the present invention comprises the steps of forming a first insulating film on a lower structure including a conductive region; Forming a second insulating layer for forming a first fence on the first insulating layer to prevent attack of the first insulating layer by chemicals through defects in a capacitor lower electrode during a subsequent dip-out process; Forming a fourth insulating film on the second insulating film; Selectively etching the fourth insulating layer, the second insulating layer, and the first insulating layer to form a first open portion exposing the conductive region, wherein the second insulating layer is between the first insulating layer and the fourth insulating layer. Making a first fence; Forming a third insulating layer to form a second fence to prevent attack of the first insulating layer by chemicals through defects in the capacitor lower electrode during a subsequent dip-out process along the profile in which the first opening is formed; Forming a second spacer having a spacer shape on sidewalls of the first insulating layer, the first fence, and the fourth insulating layer forming the profile of the open part by performing an entire surface etching; Filling the first open portion and forming a conductive film substantially planar with the fourth insulating layer; Forming a sacrificial insulating film for capacitor formation on the conductive film; Selectively etching the sacrificial insulating layer to form a second open portion exposing the conductive layer; Forming a capacitor lower electrode in contact with the conductive layer along the profile of the second open portion; And removing the sacrificial insulating layer by performing a dip-out process so that the capacitor lower electrode has a cylindrical shape.

The present invention has a fence for preventing the chemical from penetrating under the lower electrode during the sacrificial insulating film dip-out process for forming the cylindrical capacitor.

That is, a fence having a spacer shape using a nitride film-based material film on the side of the insulating film including a fence and having a fence by using a nitride film-based material film on or in the middle of the planarized contact plug for the storage node and the oxide film-based insulating film. By having a, even if there is a defect in the lower electrode or the step coverage of the lower electrode in the dip-out process, the penetration of the chemical through the fence is blocked.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

5 is a plan view schematically illustrating a semiconductor device of the present invention in which a capacitor is formed.

Referring to FIG. 5, a plurality of gate electrodes G1 to G3 extending in a line shape in the y direction are arranged at regular intervals, and the gate electrodes G1 to G3 intersect with the gate electrodes G1 to G3. A plurality of bit lines BL1 to BL3 extended in a line form in the x direction, which is a direction, are disposed. Cell contact plugs (not shown) are formed in the impurity diffusion region of the substrate between the gate electrodes G1 to G3, and the bit lines BL1 and BL2 are formed through the bit line contact plugs BLC1 and BLC2, respectively. It is in contact with the impurity diffusion region. Some of the cell contact plugs are in contact with the storage node contact plugs SNC1 to SNC4, which bury the open portions aligned on the side surfaces of the bit lines BL1 to BL3, respectively, on the storage node contact plugs SNC1 to SNC4. The cell capacitors Cap1 to Cap4 are formed.

FIG. 6 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention taken along the line a-a '.                     

Referring to FIG. 6, the semiconductor device of the present invention is disposed to have a predetermined open portion, and exposes second and third insulating layers 109 and 113 to expose a lower conductive region such as the cell contact plug 107 through the open portion. A conductive layer, for example, a storage node contact plug 117 and a capacitor lower electrode 121 disposed on the storage node contact plug 117 are electrically connected to the exposed cell contact plug 107 by filling the open part. The third insulating layer 113 has a first fence 114 at the top thereof to prevent the attack of the chemical penetrating through the defect of the capacitor lower electrode 121, and the first fence 114 and the open portion. The second fence 116 has a spacer shape surrounding sidewalls of the second and third insulating layers 109 and 113.

Meanwhile, although the cell contact plug 107 is used as an example of the conductive region, the conductive region may be formed of any conductive material such as a metal wiring, a gate electrode, and a bit line in addition to the cell contact plug. Include patterns of forms.

In addition, although the storage node contact plug 117 is used as an example of the conductive film, the conductive plug includes all types of conductive patterns in which a capacitor is connected.

Other components in the example shown in FIG. 6 will be described in more detail.

An impurity diffusion region 104 such as a source / drain is formed in the substrate 100. The impurity diffusion region 104 is formed to be aligned with the gate electrode, but the gate electrode does not appear in the cross section of FIG. 6. The cell contact plug 107 penetrates through the first insulating film 106 and contacts the impurity diffusion region 104, and is substantially flattened with the first insulating film 106.                     

Between the second insulating layer 109 and the first insulating layer 106, a first etch stop layer 108 is formed to prevent attack of the lower cell contact plug 107 when forming a second opening, that is, a storage node contact hole. It is formed using an insulating film of nitride film series. Bit lines BL1 to BL3 are formed on the second insulating layer 109, and the bit lines BL1 to BL3 are surrounded by the third insulating layer 113, and contact holes for storage nodes, that is, second open portions are formed. The etching profile is aligned with the bit lines BL1 to BL3.

The bit lines BL1 to BL3 include a conductive film 110 made of tungsten or the like, an insulating hard mask 111 thereon, and spacers 112 on the sidewalls thereof.

Here, the capacitor lower electrode 121 is made of polysilicon, Ti, TiN, Ta, TaN, Ir, IrO ₂ , Ru, RuO ₂ , Pt or the like or a combination of the lower electrode 121 and the storage node A barrier film having a single or combined configuration such as Ti, TiN, Ta, TaN, TiSi ₂ , or the like may be further included at an interface between the contact plugs 117 for the storage node and the contact plug 117 for the storage node. A conductive adhesive layer may be further included in between.

The lower electrode 121 has a cylindrical structure, a dielectric film 122 is formed on the lower electrode 121, and an upper electrode 123 is formed on the dielectric film 122. Therefore, the upper electrode 123, the dielectric film 122, and the lower electrode 121 form cylindrical capacitors Cap1 and Cap2.

FIG. 7 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present disclosure taken along the line b-b ′ of FIG. 5.                     

6 is cut out in the direction crossing the bit lines BL1 to BL3, so that the bit lines BL1 to BL3 appear on the cross section, while the gate electrodes G1 to G3 do not appear.

On the other hand, since Fig. 7 is cut in the direction crossing the gate electrodes G1 and G2, the gate electrodes G1 and G2 appear on the cross section, whereas the bit lines BL1 to BL3 do not appear.

In the configuration of FIG. 7, the same components as in FIG. 6 will be omitted.

Referring to FIG. 7, the gate insulating layer 101, the gate conductive layer 102, and the insulating hard mask 103 are stacked on the substrate 100, and the spacer type etch stop layer 105b and the spacer are omitted on the sidewalls. Has Therefore, the impurity diffusion region 104 is aligned with the side surfaces of the gate electrodes G1 and G2 and extends below the surface of the substrate 100. The cell contact plug 107 is formed on the gate electrodes G1 and G2. The first open portion is aligned and buried and is substantially planarized with the insulating hard mask 103 and the first insulating film 106.

The gate insulating film 101 uses an oxide-based insulating film such as a silicon oxide film, and the gate conductive film 102 includes a structure in which polysilicon, tungsten, tungsten silicide, tungsten nitride, or the like is used alone or in combination. The mask 103 and the etch stop film 105b include a nitride film series such as a silicon nitride film or a silicon oxynitride film. The first to third insulating films 106, 109, and 113 are made of a conventional oxide film-based insulating film.

6 and 7, the first fence 114 is formed by using a nitride film-based material film on the storage node contact plug 117 and the third insulating film 113 planarized. The lower electrode in the dip-out process by having the spacer-shaped second fence 116 using a nitride film-based material film on the sidewalls of the third insulating film 113 including the one fence 114 and the second insulating film 109. Even if there is a defect (defect) or poor step coverage of the lower electrode, it is possible to block the chemical penetration through the fence.

FIG. 8 is a cross-sectional view of a semiconductor device according to another exemplary embodiment in which FIG. 5 is cut along the a-a 'direction.

Referring to FIG. 8, the semiconductor device of the present invention is disposed to have a predetermined open portion and exposes second to fourth insulating layers 109, 113, and 124 through which the exposed conductive region, for example, the cell contact plug 107, is exposed. And a conductive film electrically connected to the exposed cell contact plug 107 by filling the open part, for example, a storage node contact plug 117 and a capacitor lower electrode 121 disposed on the storage node contact plug 117. And a first fence 114 between the third insulating film 113 and the fourth insulating film 124 to prevent attack of the chemical penetrating through the defect of the capacitor lower electrode 121. A second fence 116 having a spacer shape is formed around the sidewalls of the second to fourth insulating layers 109, 113, and 124 forming the fence 114 and the open part.

In some embodiments, the fourth insulating layer 124 may be removed.

Here, the same reference numerals are used for the same components as those in FIGS. 6 and 7, and a detailed description thereof will be omitted.

FIG. 9 is a cross-sectional view illustrating a semiconductor chip according to another exemplary embodiment in which FIG. 5 is cut along the b-b 'direction.

8 is cut out in the direction crossing the bit lines BL1 to BL3, the bit lines BL1 to BL3 appear on the cross-section, whereas the gate electrodes G1 to G3 do not appear.

9 is cut out in the direction crossing the gate electrodes G1 and G2, the gate electrodes G1 and G2 appear on the cross section while the bit lines BL1 to BL3 do not appear.

Here, the description of the same components as in Figs. 6 to 8 is omitted.

8 and 9, a nitride film-based material film is formed between the storage node contact plug 117 and the planarized fourth insulating film 124 and the third insulating film 113. It has a spacer shape using a nitride film-based material film on the sidewalls of the fourth insulating film 124 including the first fence 114, the third insulating film 113 and the second insulating film 109 including one fence 114. By having the second fence 116, the penetration of the chemical through the fence can be blocked even if the lower electrode is defective or the step coverage of the lower electrode is poor in the dip-out process.

Hereinafter, the semiconductor device manufacturing process of the present invention having the above-described configuration will be described.

10A to 10D are cross-sectional views illustrating a semiconductor device manufacturing process corresponding to FIGS. 6 and 7, and correspond to cross sections taken along the line a-a 'and b-b' of FIG. 5.                     

First, as shown in FIG. 10A, a gate insulating film 101, a gate conductive film 102, and an insulating hard mask 103 are formed on a semiconductor substrate 100 on which various elements for forming semiconductor devices such as wells and transistors are formed. Form the stacked gate electrodes G1 and G2.

Meanwhile, spacers are formed on sidewalls of the gate electrodes G1 and G2, but the spacer forming process is omitted here.

Subsequently, an ion implantation process is performed to form an impurity diffusion region 104 such as a source / drain aligned with the gate electrodes G1 and G2.

Subsequently, the first etch stop layer 105a is formed along the profile in which the gate electrodes G1 and G2 are formed, and then the first insulating layer 106 is formed on the entire surface.

When the first insulating film 106 is used as an oxide-based material film, a BSG film, a BPSG film, a PSG film, a TEOS film, an HDP oxide film, an SOG film, or an APL film is used. Dielectric constant film can be used.

Subsequently, the first insulating layer 106 is selectively etched to form a contact hole exposing the impurity diffusion region 104, and then a conductive film for forming a plug is deposited and planarized to a target to which the insulating hard mask 103 is exposed. To form the isolated cell contact plug 107.

In the contact hole forming process, the etch stop layer 105a is etched to have a spacer shape as shown by reference numeral 105b on the side of the gate electrodes G1 and G2.

Subsequently, a first etch stop layer 108 is formed on the cell contact plug 107 and the first insulating layer 106 to prevent the cell contact plug 107 from being attacked in an etching process for forming a subsequent storage node contact. do. As the first etch stop layer 108, an insulating film of a nitride film series is used.

Subsequently, a second insulating layer 109 is formed on the first etch stop layer 108, and then a portion of the cell contact plug 107 is contacted (or contacted with the impurity diffusion region 104) through a bit line contact. ) Bit lines BL1 to BL3 are formed.

The bit lines BL1 to BL3 are formed of a stacked structure of the conductive film 110 and the insulating hard mask 111 and the spacers 112 on the sidewalls.

Subsequently, a third insulating film 113 is formed on the entire surface where the bit lines BL1 to BL3 are formed, and then a third chemical is generated through defects in the capacitor lower electrode during the subsequent dip-out process on the third insulating film 113. A first fence forming insulating film 114a is formed to prevent attack of the insulating film 113. The first fence forming insulating film 114a includes an insulating film of a nitride film series.

Subsequently, as illustrated in FIG. 10B, the first fence formation insulating layer 114a, the third insulating layer 113, and the second insulating layer 109 are selectively etched to stop the etch stop in the first etch stop layer 108. As a result, the first opening portion 115 exposing the upper portion of the cell contact plug 107 to which the storage node contact is to be formed is formed.

At this time, the first fence forming insulating film 114a is etched to form the first fence 114 at the top of the third insulating film 113.

Subsequently, the first etch stop layer 108 on the bottom surface of the first open part 115 is removed to expose the cell contact plug 107.

Subsequently, the third insulating layer 113 is prevented from being attacked by the chemical through the defect of the lower electrode of the capacitor during the subsequent dip-out process along the profile in which the first open portion 115 having the cell contact plug 107 is exposed. After the deposition of the second fence insulating film for the purpose of etching, the first side 114 of the first open portion 115 formed by etching the first fence 114, the third insulating film 113 and the second insulating film 109 by etching The spacer-shaped second fence 116 is formed. A nitride film-based insulating film is used as the second fence insulating film.

Subsequently, as illustrated in FIG. 10C, a conductive film is deposited to fill the first open part 115, and then the first fence 114 and the upper part thereof are planarized by performing a planarization process using an entire surface etching or CMP. A plurality of isolated contact plugs for storage nodes are formed.

The storage node contact plug 117 may include a configuration in which polysilicon alone or polysilicon is combined with Ti, TiN, Ta, TaN, and the like.

Subsequently, a second etching acts as an etch stop to prevent attack of the storage node contact plug 117 when forming an opening defining a storage node forming region of a subsequent capacitor on the front surface on which the storage node contact plug 117 is formed. The stop film 118 is formed.

The second etch stop layer 118 uses a nitride film-based material film such as a silicon nitride film or a silicon oxynitride film.

Subsequently, a sacrificial insulating layer 119 for forming a capacitor is formed on the second etch stop layer 118. As the sacrificial insulating film 119, a conventional oxide film-based material film can be used, and mainly a single structure of TEOS film or a stacked structure of TEOS film / PSG film is used.

Subsequently, as shown in FIG. 10D, a mask pattern (not shown) defining a storage node contact formation region of the capacitor is formed on the sacrificial insulating layer 119.

The mask pattern usually represents only a photoresist pattern, but in recent years, as the vertical height of the capacitor increases, the height of the sacrificial insulating layer 119 for determining this increases, and in order to realize high resolution, the thickness of the photoresist pattern is thin. Due to the load, there is a limit in etching the sacrificial insulating layer 119 using only the photoresist pattern. Therefore, a sacrificial hard mask to be used as an etch barrier is used under the photoresist pattern, the pattern is transferred to the sacrificial hard mask using the photoresist pattern, and then the etched layer and the sacrificial insulating layer 14 are removed using the sacrificial hard mask. Etching forms a desired pattern. As the sacrificial hard mask material, polysilicon, tungsten, a nitride film, and the like are used, and various kinds of sacrificial layers are used.

Subsequently, the sacrificial insulating layer 119 is selectively etched using the mask pattern as an etch mask to form a second open portion 120 exposing the second etch stop layer 118 on the storage node contact plug 117.

Here, the second open part 120 represents a capacitor formation region.

At this time, the etching profile of the second open portion 120 is aligned with the side of the bit lines BL1 to BL3, and an etching process by SAC is applied to secure the margin of the etching process due to the large etching target.

Next, the second etch stop layer 118 is removed to expose the storage node contact plug 117.

Subsequently, a cleaning process is performed to remove the etching residue resulting from the formation of the second open portion 120 and the interfacial oxide film formed on the bottom surface of the second open portion 120. The cleaning process uses a wet method, and the chemical uses HF or BOE.

Subsequently, the conductive film for the storage node is deposited along the profile in which the second open part 120 is formed, and is electrically connected to the storage plug contact plug 117 exposed according to the formation of the second open part 120.

Subsequently, the passivation layer is deposited to fill the empty portion of the open part 120, and then the bottom electrode 121, that is, the storage node, of the isolated capacitor is formed by performing a front etch or CMP process on the target to which the sacrificial insulating layer 119 is exposed. Form.

Here, the conductive film for the lower electrode includes a single or combined configuration of polysilicon, Ti, TiN, Ta, TaN, Ir, IrO ₂ , Ru, RuO ₂ , Pt and the like.

In addition, a barrier film having a single or combined configuration such as Ti, TiN, Ta, TaN, TiSi ₂ , or the like may be formed at an interface between the lower electrode 121 and the contact plug 117 for a storage node, and an interlayer insulating film and An adhesive layer may be further included between the storage node contact plug 117 and the barrier layer.

Subsequently, after the protective film is removed, the sacrificial insulating film 119 is removed by performing a dip-out process so that the lower electrode 121 has a cylindrical structure. In the dip-out process, chemicals such as HF or BOE are used.

Subsequently, the dielectric film 122 and the upper electrode 123 are sequentially formed on the lower electrode 121, thereby completing the cell capacitor forming process illustrated in FIGS. 6 and 7.

11A to 11D are cross-sectional views illustrating a semiconductor device manufacturing process corresponding to FIGS. 8 and 9 and correspond to cross sections taken along the line a-a 'and b-b' of FIG. 5.

First, as shown in FIG. 11A, gate electrodes G1 and G2 having the gate insulating film 101, the gate conductive film 102, and the insulating hard mask 103 stacked on the substrate 100 are formed. Subsequently, an ion implantation process is performed to form an impurity diffusion region 104 such as a source / drain aligned with the gate electrodes G1 and G2.

Subsequently, the first etch stop layer 105a is formed along the profile in which the gate electrodes G1 and G2 are formed, and then the first insulating layer 106 is formed on the entire surface.

Subsequently, the first insulating layer 106 is selectively etched to form a contact hole exposing the impurity diffusion region 104, and then a conductive film for forming a plug is deposited and planarized to a target to which the insulating hard mask 103 is exposed. To form the isolated cell contact plug 107.

In the contact hole forming process, the etch stop layer 105a is etched to have a spacer shape as shown by reference numeral 105b on the side of the gate electrodes G1 and G2.

Subsequently, a first etch stop layer 108 is formed on the cell contact plug 107 and the first insulating layer 106. As the first etch stop layer 108, an insulating film of a nitride film series is used.                     

Subsequently, a second insulating layer 109 is formed on the first etch stop layer 108, and then bit lines BL1 to BL3 are formed by contacting some of the cell contact plugs 107 through bit line contacts.

The bit lines BL1 to BL3 are formed of a stacked structure of the conductive film 110 and the insulating hard mask 111 and the spacers 112 on the sidewalls.

Subsequently, a third insulating film 113 is formed on the entire surface where the bit lines BL1 to BL3 are formed, and then a third chemical is generated through defects in the capacitor lower electrode during the subsequent dip-out process on the third insulating film 113. A first fence forming insulating film 114a is formed to prevent attack of the insulating film 113. The first fence forming insulating film 114a includes an insulating film of a nitride film series. Subsequently, a fourth insulating film 124 is formed on the first fence forming insulating film 114a by using an oxide-based insulating film.

Subsequently, as illustrated in FIG. 11B, the first etching stop layer may be selectively etched by selectively etching the fourth insulating layer 124, the first fence forming insulating layer 114a, the third insulating layer 113, and the second insulating layer 109. By etch stop at 108, the first open part 115 is formed to expose the upper portion of the cell contact plug 107 where the storage node contact is to be made.

In this case, the first fence formation insulating layer 114a is etched to form the first fence 114 between the fourth insulating layer 124 and the third insulating layer 113.

Subsequently, the first etch stop layer 108 on the bottom surface of the first open part 115 is removed to expose the cell contact plug 107.

Subsequently, the third insulating layer 113 is prevented from being attacked by the chemical through the defect of the lower electrode of the capacitor during the subsequent dip-out process along the profile in which the first open portion 115 having the cell contact plug 107 is exposed. After the deposition of the second fence insulating film for etching, the first etching formed by etching the fourth insulating film 124, the first fence 114, the third insulating film 113 and the second insulating film 109 by etching the entire surface A spacer-shaped second fence 116 is formed on the sidewall of the open portion 115. A nitride film-based insulating film is used as the second fence insulating film.

Subsequently, as illustrated in FIG. 11C, the conductive film is deposited to fill the first open portion 115, and then the first fence 114 and the upper portion thereof are planarized by performing a planarization process using front etching or CMP. A plurality of isolated contact plugs for storage nodes are formed.

Subsequently, a second etching stop layer 118 is formed on the entire surface where the contact plug 117 for the storage node is formed.

Subsequently, a sacrificial insulating layer 119 for forming a capacitor is formed on the second etch stop layer 118.

Subsequently, as illustrated in FIG. 11D, a mask pattern (not shown) defining a storage node contact formation region of the capacitor is formed on the sacrificial insulating layer 119.

Subsequently, the sacrificial insulating layer 119 is selectively etched using the mask pattern as an etch mask to form a second open portion 120 exposing the second etch stop layer 118 on the storage node contact plug 117.

Next, the second etch stop layer 118 is removed to expose the storage node contact plug 117.                     

Subsequently, a cleaning process is performed to remove the etching residue resulting from the formation of the second open portion 120 and the interfacial oxide film formed on the bottom surface of the second open portion 120.

Subsequently, the conductive film for the storage node is deposited along the profile in which the second open part 120 is formed, and is electrically connected to the storage plug contact plug 117 exposed according to the formation of the second open part 120.

Subsequently, the passivation layer is deposited to fill the empty portion of the open part 120, and then the bottom electrode 121, that is, the storage node, of the isolated capacitor is formed by performing a front etch or CMP process on the target to which the sacrificial insulating layer 119 is exposed. Form.

Subsequently, after the protective film is removed, the sacrificial insulating film 119 is removed by performing a dip-out process so that the lower electrode 121 has a cylindrical structure. In the dip-out process, chemicals such as HF or BOE are used.

Meanwhile, the fourth insulating layer 124 may be removed at the same time in the dip-out process.

Subsequently, the dielectric film 122 and the upper electrode 123 are sequentially formed on the lower electrode 121, thereby completing the cell capacitor forming process illustrated in FIGS. 8 and 9.

According to the present invention made as described above, a nitride film-based material film is formed on the upper or middle portion of the contact plug for the storage node and the oxide film-based insulating film to be planarized. By having a spacer-shaped fence using a material film, it is possible to block chemical penetration through the fence even if there is a defect in the lower electrode or the step coverage of the lower electrode is poor in the dip-out process.

In addition, even if a misalignment occurs when the second open portion defining the capacitor formation region is formed, the etching profile may be induced by the first and second fences in a desired direction, thereby reducing the occurrence of defects due to the misalignment. It was found through the examples.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above, by preventing the penetration of the chemical due to the dip-out of the sacrificial insulating film to reduce the occurrence of defects, there is an effect to improve the yield of the semiconductor device.

Claims (15)

An insulating film having an open portion exposing a lower conductive region; A contact plug filling the open portion and electrically connected to the conductive region; And An electrode disposed on the contact plug, The insulating film, And a second fence formed on the sidewall of the open portion of the insulating layer including the first fence and having a first fence at the top thereof to prevent attack of the chemical penetrating through the defect of the electrode. . An insulating film having an open portion exposing a lower conductive region; A contact plug filling the open portion and electrically connected to the conductive region; And An electrode disposed on the contact plug, The insulating film, A first insulating film for interlayer insulation, a first fence formed on the first insulating film, and a second insulating film formed on the first fence to prevent attack of chemicals penetrating through the defect of the electrode; And a second fence formed on sidewalls of the open portion of the insulating film including one fence. The method according to claim 1 or 2, The electrode is a semiconductor device, characterized in that the cylindrical capacitor lower electrode. The method according to claim 1 or 2, The insulating layer is an oxide film-based, the semiconductor device, characterized in that the first fence and the second fence is made of an insulating film of the nitride film series. The method according to claim 1 or 2, And the contact plug is a contact plug for a storage node, and the conductive region is an impurity diffusion region of a substrate. The method according to claim 1 or 2, And the contact plug is a contact plug for a storage node, and the conductive region is a cell contact plug in contact with an impurity diffusion region of a substrate. Forming a first insulating film on the lower structure including the conductive region; Forming a first fence on the first insulating layer to prevent attack by chemical; Selectively etching the first fence and the first insulating layer to form a first open part exposing the conductive region; Forming a spacer-shaped second fence on sidewalls of the first fence and the first insulating layer forming the first open portion; Forming a contact plug embedded in the first open portion; Forming a sacrificial insulating film for capacitor formation on the contact plug; Selectively etching the sacrificial insulating layer to form a second open portion exposing the contact plug; Forming a capacitor lower electrode in the second open portion; And Removing the sacrificial insulating layer so that the capacitor lower electrode has a cylindrical shape Semiconductor device manufacturing method comprising a. Forming a first insulating film on the lower structure including the conductive region; Forming a first fence on the first insulating layer to prevent attack by chemical; Forming a second insulating film on the first fence; Selectively etching the second insulating layer, the first fence and the first insulating layer to form a first open part exposing the conductive region; Forming a spacer-shaped second fence on sidewalls of the second insulating film, the first fence, and the first insulating film forming the first open portion; Forming a contact plug embedded in the first open portion; Forming a sacrificial insulating film for capacitor formation on the contact plug; Selectively etching the sacrificial insulating layer to form a second open portion exposing the contact plug; Forming a capacitor lower electrode in the second open portion; And Removing the sacrificial insulating layer so that the capacitor lower electrode has a cylindrical shape Semiconductor device manufacturing method comprising a. The method according to claim 7 or 8, The first insulating layer is an oxide film-based, the first fence and the second fence is a semiconductor device manufacturing method, characterized in that the nitride film-based. The method according to claim 7 or 8, The sacrificial insulating film is a semiconductor device manufacturing method characterized in that the oxide film series. The method of claim 10, The removing of the sacrificial insulating film, the semiconductor device manufacturing method, characterized in that using a dip-out process using HF or BOE. The method according to claim 7 or 8, The contact plug is a storage node contact plug, and the conductive region is a semiconductor device manufacturing method, characterized in that the impurity diffusion region of the substrate. The method according to claim 7 or 8, And the contact plug is a contact plug for a storage node, and the conductive region is a cell contact plug in contact with an impurity diffusion region of a substrate. The method of claim 7, wherein And forming an etch stop layer on the first fence to stop etching when the first open portion is formed. The method of claim 8, And forming an etch stop layer on the second insulating layer to stop etching when the first open portion is formed.

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