KR100732175B1 - plasma display panel - Google Patents

Abstract

The present invention maximizes the discharge space by improving the partition structure in the cell structure related to the fabrication of low power, high brightness, high efficiency plasma display panel, increases the amount of visible light, and at the same time changes the shape of the front electrode. The present invention provides a plasma display panel which can improve light efficiency by reducing energy loss required for discharging.

The plasma display panel displays a plurality of electrode groups consisting of X electrodes and Y electrodes formed on one side of the front substrate, and the intersections of the electrode groups on the front substrate and the address electrodes on the rear substrate. A plurality of address electrodes formed on one surface of an opposite rear substrate of the front substrate, partition walls partitioning adjacent display cells between the front substrate and the rear substrate, and R formed between the partition walls; A plasma display panel including phosphor layers of G and B, wherein the phosphor layers of R, G and B are formed in a triangle structure, and the display cells of the phosphor layers of R, G and B in the triangle structure are formed. Partition walls are formed in a matrix structure completely surrounding each.

Description

Plasma display panel

1 is a schematic partial plan view showing the shape of an electrode and a partition of a three-electrode plasma display panel;

2 is a schematic partial cross-sectional view for explaining the configuration of a three-electrode plasma display panel;

3 is a schematic partial plan view similar to FIG. 1 showing a barrier rib and an electrode structure of a plasma display panel according to an embodiment of the present invention;

4 is a schematic partial plan view similar to FIG. 1 showing a barrier rib and an electrode structure of a plasma display panel according to another embodiment of the present invention;

FIG. 5 is a schematic partial plan view similar to FIG. 1 showing a barrier rib and an electrode structure of a plasma display panel according to another embodiment of the present invention; FIG.

<Description of the symbols for the main parts of the drawings>

1: front board 2: back board

3: X electrode 3 ', 4': bus electrode

3 ", 4": black matrix 4: Y electrode

5: address electrode 6, 7: dielectric layer

8: bulkhead 9: fluorescent layer

The present invention relates to a plasma display panel, and more particularly, to a cell structure related to fabrication of a plasma display panel having low power, high brightness, and high efficiency, the partition structure is improved to maximize discharge space, and the amount of visible light is increased to provide breakthrough luminance. In addition, the present invention relates to a plasma display panel which can improve the light efficiency by reducing the energy loss required for discharging by modifying the shape of the front electrode.

Recently, PDP has emerged as a promising candidate ahead of the popularization of HDTV and digital broadcasting. Since it is much lower than existing CRTs in terms of efficiency, PDP development is being carried out with the aim of increasing efficiency worldwide.

1 and 2 show a schematic plan view and a partial sectional view for explaining the structure of the plasma display panel. As shown in FIG. 2, the plasma display panel includes an X electrode 3 and a Y electrode 4. The front electrode group is formed on the front substrate 1, the dielectric layer 6 is formed thereon. In addition, an address electrode 5 is formed on the opposite rear substrate 2 of the front substrate 1, a dielectric layer 7 is formed thereon, and a fluorescent layer 9 is formed between the partitions 8. .

In the driving method of the plasma display panel configured as described above, one field is divided into, for example, first to eighth subfields for gray scale display, and each subfield is composed of a reset section, an address section, and a sustain discharge section. In addition, a specific sustain discharge section is set for each subfield, and the gradation of the video screen is displayed by the combination of these subfields.

1 shows a conventional arrangement of electrodes, barrier ribs, and phosphor layers, and a delta structure of Fujitsu is shown as a plan view, and the arrangement of the phosphor layers is a triangular-color driving method. The partition wall has a hexagonal structure in contact with the front electrode. As the partition wall contacts the front electrode as described above, after the front electrode discharges, charged particles (electrons and ions) are lost to the partition wall, causing energy loss. Therefore, there is a problem that the actual discharge is not efficient.

In addition, although illustration is abbreviate | omitted, the Pioneer waffle structure consists of square partition structure, and R, G, and B fluorescent substance layers are each stripe-shaped. However, this structure has a limited discharge space due to the stripe shape, and thus there is a problem that the entire discharge space cannot be used efficiently.

 Accordingly, the present invention is to solve this problem, in the cell structure related to the fabrication of low power, high brightness, high efficiency plasma display panel to improve the partition structure to maximize the discharge space, increase the amount of visible light to increase the breakthrough brightness At the same time, the object of the present invention is to provide a plasma display panel capable of improving the light efficiency by reducing the energy loss required for discharging by modifying the shape of the front electrode.

In order to achieve this object, a plasma display panel according to an embodiment of the present invention includes a plurality of electrode groups including X electrodes and Y electrodes formed on one surface of a front substrate, and electrode groups on the front substrate. A plurality of address electrodes formed on one side of an opposite rear substrate of the front substrate to form display (discharge) cells at intersections of the address electrodes on the rear substrate and adjacent display cells between the front substrate and the rear substrate. A plasma display panel comprising partition walls and phosphor layers of R, G and B formed between the partition walls, wherein the phosphor layers of R, G and B are formed in a triangle structure, and the triangle A partition wall is formed in a matrix structure completely surrounding each of the display cells of the phosphor layers of R, G, and B structures.

Double barrier ribs may be formed on both sides of the address electrode of the portion with a space on the address electrodes between the display cells of the phosphor layers of the respective R, G, and B layers, and the phosphor layers of the respective R, G, and B layers. The barrier ribs in the X electrode and Y electrode directions may be disconnected along the address electrode so that the spaces on the address electrodes between the display cells of the cell communicate with each other. In this case, the display cells of the phosphor layers of R, G, and B are preferably composed of asymmetric cells to increase the color temperature.

Further, the partition walls of the matrix structure are formed on the X electrode and the Y electrode in the X electrode and Y electrode directions, and the X electrode and the Y electrode are the display cells of the phosphor layers of R, G, and B for discharge. It is also preferably formed to protrude in a range not in contact with the partition wall in the address direction.
In addition, the front electrodes formed in the display cells formed of the partition walls of the matrix structure may use one scan electrode in common for two adjacent driving lines.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 shows a partition and electrode structure of a plasma display panel according to an embodiment of the present invention as a schematic partial plan view. A plasma display panel according to a preferred embodiment of the present invention is called a matrix-type triangle-color arrangement (MTA).

3, the electrode structure of the plasma display panel of the present invention is similar to the conventional X electrode and Y electrodes formed on one side of the front substrate is formed in the XYXY structure, and cross the X electrode and the Y electrode on the back substrate Address electrodes are formed at, and at the intersections, display (discharge) cells of the phosphor layers of R, G, and B are formed.

The display cells of the phosphor layers of R, G and B are formed in a triangle structure, and each of the display cells of the phosphor layers of R, G and B in the triangle structure is completely surrounded by a partition wall. The partition wall forms a matrix structure.

In addition, as shown in FIG. 3, the partition walls of the matrix structure may be formed on the X electrode and the Y electrode in the X electrode and Y electrode directions, and in this case, the X electrode and the Y electrode may be formed by the ITO electrode for discharge. In the display cells of the phosphor layers of G and B, they are formed so as to protrude in a range not in contact with the partition wall in the address electrode direction.
As shown in FIG. 3, the address electrodes of the present invention are formed in a straight line throughout the panel while passing through a cell center in a discharge line and passing through a partition wall in a non-discharge line. That is, in the case of the drive line in which the address electrode contributes to the discharge, it is formed to pass through the center of the cell, and in the case of the drive line that does not contribute to the discharge, it passes through the bottom of the partition wall.
In addition, the front electrode group (X electrode and Y electrode) of the present invention is configured to be commonly used among display cells arranged in adjacent lines. That is, in the present invention, two driving lines share one scan electrode, and the first driving line (row 1) and the second driving line (row 2) share the scan electrode of Yn-1, and the third The drive line (row 3) and the fourth drive line (row 4) are constructed in such a manner that they share a Yn scan electrode. In addition, in the X electrode, the second drive line (2 rows) and the third drive line (3 rows) share a single sustain electrode, and the fourth drive line (4 rows) and the fifth drive line (5 rows) are single. It is configured in such a way that it shares a sustain electrode.

In the driving method of the plasma display panel having such a structure, for example, when the Yn electrode is selected as the scanning electrode, each data pulse is applied to the address electrode, and discharge occurs, so that wall charges are accumulated on the Yn electrode and the address electrode. .

In the next step, discharge occurs between the Yn electrode and two neighboring common X electrodes during the sustain period (maintenance discharge period), so that wall charges are accumulated on the Yn electrode and two neighboring X electrodes, and the gray is repeatedly displayed. do.

In the present invention, since the display cells of the phosphor layers of each of R, G, and B are surrounded by the partition walls of the matrix structure, discharge is not generated in the portion where the address electrode passes over the partition walls, so that accurate addressing is achieved.
More specifically, in the driving method of FIG. 3, scan lines are sequentially selected to the scan electrodes in the order of Yn-1, Yn, and Yn + 1 in the addressing process, and data is selected through the address electrodes when the corresponding lines are selected. Is sent to specify the address. First, in order to perform an address on the first driving line (row 1), a scan pulse is applied to a scan electrode of Yn-1 without a signal being applied to scan electrodes except Yn-1, and in this state a1 and a3 When a corresponding data pulse is applied to an address electrode such as, a5..., an address operation is performed on the first driving line (line 1) in accordance with data.
Next, in order to perform an address on the second driving line (line 2), a scan pulse is applied only to the scan electrode of Yn-1, and in this state, a corresponding data pulse is applied to the address electrodes of a2, a4, a6, etc. In this case, an address operation is performed on the second driving line (line 2) according to the data. Therefore, even though two adjacent driving lines share a common scan electrode, the address electrode is clearly separated, and thus address work can be selectively performed only on the driving line to be scanned.

In this embodiment, a much larger discharge space is ensured. In a specific embodiment, when the VGA pitch is 1080 μm, the size of one subpixel in the x-axis direction is 720 μm, and the scan electrode (Y electrode) is used. ) And the center-to-center distance between neighboring X electrodes is 540 µm. Therefore, in the conventional stripe-type matrix type structure, the size of one subpixel in the x-axis direction is 360 μm and the discharge space can be secured much longer than that of the front electrode center distance of 410 μm. By enabling discharge, it is possible to significantly increase the brightness and efficiency.

Further, in the present invention, the area of the discharge electrode can be greatly reduced. That is, in this structure, the ITO shapes of the scan electrode and the X electrode participating in the actual discharge are convexly projected on the center of the display cell so as not to contact the partition walls of the matrix structure in the vertical direction, thereby greatly reducing the area of the electrode. In this way, the ITO area involved in the discharge can be reduced to reduce the discharge current, and the energy dissipation portion passing through the partition can be removed due to the structure separated from the partition, thereby greatly increasing the discharge efficiency.                     

4 illustrates a partition wall and an electrode structure of a plasma display panel according to another exemplary embodiment of the present invention.

In FIG. 4, double partitions are formed on both sides of the address electrodes of the portion with a space on the address electrodes between the display cells of the phosphor layers of each of R, G, and B. The other configuration is similar to that in FIG.

The driving method of the plasma display panel configured as described above is similar to that of the above-described embodiment, and the structure of the display cells of the phosphor layers of R, G, and B is similar to that of the above-described embodiment in terms of structure. Since the partition wall in the electrode direction is doubled, a rear electrode (address electrode) exists between the partition wall and the partition wall in the address electrode direction, thereby improving alignment and exhaust problems.

In addition, in the present embodiment, it is possible to configure the display cells of the phosphor layers of R, G, and B as an asymmetric cell to increase the color temperature. That is, in the above-described embodiment, it is difficult to fabricate the asymmetric display cell. However, in this embodiment, the distance between the partition walls in the address electrode direction can be adjusted according to the display cells of the phosphor layers of R, G, and B. It is possible to increase the color temperature by varying the area between the different phosphor layers. Other effects are the same as in the above-described embodiment. That is, when driving, if there are n Y electrodes (scan electrodes), n + 1 electrodes are needed, and the luminance / efficiency is improved by increasing the rear length (for example, from 360 to 720 mu m in VGA class). being). In addition, the luminance / efficiency is increased by expanding the front discharge area (eg, from 410 μm to 540 μm in the VGA class). In addition, the fluorescent surface increases due to the partition wall of the matrix structure, thereby increasing brightness and improving efficiency. Since the ITO region related to the discharge is separated from the partition wall, the energy loss along the partition wall during discharge is small, so that the efficiency is improved. As the length of the ITO electrode related to the discharge is reduced, the discharge current is reduced and the efficiency is improved.

5 shows a partition and an electrode structure of a plasma display panel according to another embodiment of the present invention.

Compared with the structure of the other embodiment described above, in this embodiment, the X electrode and Y electrode directions along the address electrode are arranged so that the space on the address electrode between the display cells of the phosphor layers of each of R, G, and B is in communication with each other. The bulkheads are cut off.

In this manner, the driving method is similar to the above-described embodiments, but the partition wall does not exist in the direction of the address electrode, so that the exhaust gas can be well discharged. The other structures and functions are the same as those of the above-described embodiments.

According to the configuration and operation of the plasma display panel according to the embodiment of the present invention described above, a plasma display panel having a low power, high brightness and high efficiency by a matrix-type triangle-color arrangement (MTA) In the cell structure related to fabrication, the partition structure is improved to maximize the discharge space, and the visible light amount is increased to achieve a dramatic increase in brightness, and the shape of the front electrode is modified to reduce the energy loss required for discharge to improve the light efficiency. It can be effective.

Claims (5)

A plurality of electrode groups composed of X electrodes and Y electrodes formed on one side of the front substrate, and a front side to form display (discharge) cells at intersections of the electrode groups on the front substrate and the address electrodes on the back substrate; A plurality of address electrodes formed on one surface of the opposite rear substrate of the substrate, barrier ribs partitioning adjacent display cells between the front substrate and the rear substrate, and phosphors of R, G, and B formed between the barrier ribs; Including a layer, the phosphor layers of the R, G, B are formed in a triangle (triangle) structure, and a matrix structure that completely surrounds each display cell of the phosphor layers of R, G, B of the triangle structure A plasma display panel having a partition wall formed therein; The address electrodes are formed in a straight line to pass through the center of the cell in the discharge line, pass through the partition wall in the non-discharge line, A plasma display panel, characterized in that one Y electrode (scan electrode) is formed in common for two adjacent driving lines so that two drive lines share one Y electrode (scan electrode). The plasma display panel of claim 1, wherein a double partition wall is formed on both sides of the address electrode of the portion with a space on the address electrode between the display cells of the phosphor layers of each of R, G, and B. The barrier ribs of the X electrode and the Y electrode direction are disconnected along the address electrode such that spaces on the address electrodes between the display cells of the phosphor layers of each of R, G, and B communicate with each other. Plasma display panel. The plasma display panel of claim 2 or 3, wherein the display cells of the phosphor layers of R, G, and B are configured as an asymmetric cell to increase the color temperature. 2. The matrix structure according to claim 1, wherein the partition walls of the matrix structure are formed on the X electrode and the Y electrode in the X electrode and Y electrode directions, and the X electrode and the Y electrode are phosphors of R, G, and B for discharge. A plasma display panel which protrudes in a range not in contact with a partition wall in an address direction in a display cell of layers.

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