KR100728986B1 - A duty checking circuit of internal clock - Google Patents

Abstract

A duty checking circuit of an internal clock is provided to implement a high speed operation by checking a twisted direction and amplitude of a clock duty generated in a semiconductor device and then outputting the checking result to a data pin by sensing first and second internal clock signals using a test mode. A first clock buffer part(10) generates a first internal clock signal synchronized to a rising edge by buffering a clock signal inputted from the outside. A second clock buffer part(20) is enabled by a test mode signal, and generates a second internal clock signal synchronized to a falling edge by buffering the clock signal. A clock duty sensing part(30) compares the first internal clock signal with the second internal clock signal and then outputs the corresponding result, when the test mode signal is enabled.

Description

A duty checking circuit of internal clock

1 is a diagram showing a state of an internal clock generated inside a semiconductor.

2 is a block circuit diagram for checking an internal clock duty according to an embodiment of the present invention.

3 is a circuit diagram of a clock duty detector of FIG. 2.

4A is a waveform diagram illustrating a case where the high pulse whiskey and the low pulse whiskey of the internal clock are the same.

FIG. 4B is a waveform diagram showing when the high pulse whisker of the internal clock is wider than the low pulse whisker. FIG.

FIG. 4C is a waveform diagram showing when the high pulse whisker of the internal clock is shorter than the low pulse whisker. FIG.

The present invention relates to an internal clock duty check circuit, and more particularly, a design and process for implementing high-speed operation by checking a wrong direction and magnitude of a clock duty generated inside a semiconductor device using a test mode and outputting the result to a data pin. The present invention relates to a clock duty check circuit capable of efficiently responding to changes.

1 is a diagram illustrating a state of an internal clock generated inside a semiconductor.

As shown in FIG. 1, a clock generated in a semiconductor may be classified into three types. Assuming that a clock with a high pulse width and a low pulse width of 50 to 50 is input from the outside, the internal clock passing through the clock buffer has a high pulse whistle and a low pulse whistle. The most ideal case (case1) outputted in 50 to 50, the high pulse whisker is wider than the low pulse whisker (case2), and the high pulse whisker is shorter than the low pulse whisker (case3).

However, even when a clock having an ideal clock duty ratio, that is, a clock duty ratio of 50 to 50 is input from the outside, a clock having an internal clock duty ratio or an externally shifted clock duty ratio is input by the size of the internal clock generation buffer. When the internal clock duty is shifted, such as when the internal clock duty ratio is shifted, malfunction of the semiconductor occurs, which causes the high speed operation to be restricted.

However, there is a problem in that the method for checking the duty of the internally generated clock is not presented in detail.

Accordingly, an object of the present invention is to check the twisted direction and magnitude of the clock duty generated inside the semiconductor device using the test mode and output the result to the data pin to efficiently cope with the design and process change that implements high speed operation. To provide a clock duty check circuit.

In order to achieve the above object, the internal clock duty check circuit of the present invention comprises: a first clock buffer unit for buffering a clock signal input from an external source to generate a first internal clock signal synchronized with a rising edge; A second clock buffer unit enabled by a mode signal and configured to buffer the clock signal to generate a second internal clock signal synchronized to a falling edge, and the test mode signal enabled; And a clock duty detector for comparing the duty of the signal with the second internal clock signal and outputting a result corresponding thereto.

Here, the second clock buffer unit is configured in the same manner as the first clock buffer unit, and receives the clock signal opposite to the first clock buffer unit.

The clock duty detector may be configured to determine whether there is a section in which the first internal clock signal and the second internal clock signal remain the same at the same level and simultaneously output a first detection signal corresponding thereto. A comparator, and a second comparator configured to determine whether there is a section in which the first internal clock signal and the second internal clock signal remain the same at the same time in the second level state and output a second detection signal corresponding thereto. It is characterized by.

The clock duty detector outputs the first sense signal and the second sense signal to a data pin.

The first level is a period in which the first internal clock signal and the second internal clock signal are kept in a high state at the same time, and the first detection signal is a signal output in a high state at the first level.

The second level is a period in which the first internal clock signal and the second internal clock signal are kept in a low state at the same time, and the second detection signal is a signal output in a high state at the second level.

The first comparator includes a NAND gate for logically combining the first internal clock signal and the second internal clock signal, an inverter for inverting the output of the NAND gate, a first CMOS inverter for inverting the output of the inverter, And a first latch unit for latching an output of the second CMOS inverter.

Here, in the first CMOS inverter, a PMOS transistor and an NMOS transistor are connected in series between a power supply voltage and a ground voltage, a test mode signal is applied to a gate of the PMOS transistor, and an output of the inverter is applied to a gate of the NMOS transistor. Receive.

The second comparator latches a noah gate for logically combining the first internal clock signal and the second internal clock signal, a second CMOS inverter for inverting the output of the noah gate, and an output of the second CMOS inverter. It characterized in that it comprises a second latch portion.

In the second CMOS inverter, a PMOS transistor and an NMOS transistor are connected in series between a power supply voltage and a ground voltage, a test mode signal is applied to a gate of the PMOS transistor, and an output of the NOA gate is applied to a gate of the NMOS transistor. .

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. The same number is given to the same member as much as possible.

2 is a block circuit diagram for checking an internal clock duty according to an embodiment of the present invention.

As shown in FIG. 2, the internal clock duty check circuit includes a first clock buffer unit 10, a second clock buffer unit 20, and a clock duty detector 30.

The first clock buffer unit 10 receives a clock signal clk and a clock bar signal clkb, which are input from the outside, to the input units A and B and buffers the first internal clock signal Clk_out1 applied to the semiconductor internal circuit. )

The second clock buffer unit 20 has the same configuration as the first clock buffer unit 10. On the other hand, the clock signal input to the input units A and B is opposite to the first clock buffer unit 10. That is, the clock bar signal clkb is input to the input unit A, and the clock signal clk is input to the input unit B. Then, the second internal clock signal Clk_out2 that is compared with the internal clock Clk_out1 is generated by the test mode signal Test mode.

Since the first clock buffer unit 10 and the second clock buffer unit 20 have the same configuration, but the input signals are opposite to each other, the first internal clock signal Clk_out1 may be a rising edge of the external clock signal clk. The second internal clock signal Clk_out2 is output in synchronization with a riging edge and synchronized with a falling edge of the external clock clk.

The clock duty detector 30 compares the first internal clock signal Clk_out1 and the second internal clock signal Clk_out2 with the test mode signal enabled, and compares the result with the data pin DQ1 pin, DQ2 pin).

Here, the test mode signal is initially in a low state and is enabled in a high state when the clock duty is checked.

3 is a circuit diagram of the clock duty detector of FIG. 2.

The clock duty detector of FIG. 3 performs a logical combination of the first internal clock signal Clk_out1 and the second internal clock signal Clk_out2 to check the high pulse whiskey of the first internal clock signal Clk_out1, and output the result to the data pin DQ1. a first comparator 33 for outputting to the pin) and a second comparator 36 for checking the low pulse whistle of the first internal clock signal Clk_out1 and outputting the result to the data pin DQ2 pin. It is composed.

The first comparator 33 includes a NAND gate NAND1 that logically combines the first internal clock signal Clk_out1 and the second internal clock signal Clk_out2, and an inverter INV1 that inverts the output of the NAND gate NAND1. ) And a first latch unit configured to latch and output the outputs of the first CMOS inverter 31 and the first CMOS inverter 31 to which the output of the inverter INV1 and the test mode signal are applied, to the data pin DQ1 pin. 32).

Here, in the first CMOS inverter 31, a PMOS transistor P1 and an NMOS transistor N1 are connected in series between a power supply voltage VDD and a ground voltage VSS. The test mode signal is applied to the gate, and the output of the inverter INV1 is applied to the gate of the NMOS transistor N1.

The second comparator 36 includes a noar gate NOR1, a second CMOS inverter 34, and a second CMOS inverter 34 that logically combine the first internal clock signal Clk_out1 and the second internal clock signal Clk_out2. And a second latch portion 35 for latching the output of the output signal to the data pin DQ2 pin.

Here, the second CMOS inverter 34 is configured in the same manner as the first CMOS inverter 31. That is, the PMOS transistor P2 and the NMOS transistor N2 are connected in series between the voltage VDD and the ground voltage VSS. The test mode signal is applied to the gate of the PMOS transistor P2, and the output of the NOR gate NOR1 is applied to the gate of the NMOS transistor N2.

Each of the first and second latch units 32 and 35 includes two inverters INV2 and INV3; INV4 and INV5.

4A to 4C are waveform diagrams of an internal clock signal output from the clock duty detector.

Here, the node A is a waveform of checking the high pulse whiskey of the first internal clock signal Clk_out1 outputted to the data pin DQ1 pin, and the node B is a first internal clock signal outputted to the data pin DQ2 pin. The waveform of the low pulse whiskey of Clk_out1) is checked.

First, the test mode signal is initially low. Thus, initially Node A and Node B are low. The test mode signal remains high.

4A illustrates a case where the high pulse whiskey and the low pulse whiskey of the first internal clock signal Clk_out1 are equal to 50 to 50.

In this case, the second internal clock signal Clk_out2 outputs high pulse whiskey and low pulse whiskey 50 to 50 in synchronization with the falling edge of the external clock signal clk.

Since the first comparator 33 has no section in which the first internal clock signal Clk_out1 and the second internal clock signal Clk_out2 are simultaneously in a high state, the output of the NAND gate NAND1 is always in a high state, and the inverter INV1 Is inverted and becomes low. As a result, since the NMOS transistor N1 of the first CMOS inverter 31 is turned off, the output of the first CMOS inverter 31 becomes high, and is inverted in the first latch portion 32 to be the node A, that is, the data. The pin (DQ1 pin) is output low.

Since the second comparator 36 has no section in which the first internal clock signal Clk_out1 and the second internal clock signal Clk_out2 are in a low state at the same time, the output of the NOA gate NOR1 is in a low state. As a result, since the NMOS transistor N2 of the second CMOS inverter 34 is turned off, the output of the second CMOS inverter 34 becomes high, and is inverted in the second latch portion 35, thereby inverting the node B, that is, data. Pin (DQ2 pin) is output low.

Therefore, when both node A and node B are output in the low state, it can be seen that the duty ratio of the first internal clock signal is 50 to 50.

4B illustrates a case where the high pulse whisker of the first internal clock signal Clk_out1 is wider than the low pulse whisker.

In this case, the second internal clock signal Clk_out2 is synchronized with the falling edge of the external clock so that the high pulse whiskey is output wider than the low pulse whiskey in the same manner as the first internal clock signal.

Since the first comparator 34 has a section in which the first internal clock signal Clk_out1 and the second internal clock signal Clk_out2 are simultaneously in a high state, the output of the NAND gate NAND1 is low during this period. Is inverted through the inverter INV1 and becomes high. As a result, since the NMOS transistor N1 of the first CMOS inverter 31 is turned on, the output of the first CMOS inverter 31 becomes low and inverted in the first latch portion 32 so that the node A is in a high state. Transition.

The second comparator 36 outputs a low state to the node B since there is no section in which the internal clock signal Clk_out1 and the comparison clock signal Clk_out2 are in a low state at the same time.

Accordingly, when the node A transitions to the high state and the node B maintains the low state, the duty of the first internal clock signal is shifted, and the high pulse whisker is wider than the low pulse whisker. .

In contrast to FIG. 4B, FIG. 4C illustrates a case where the high pulse whisker of the first internal clock Clk_out1 is shorter than the low pulse whisker.

In this case, the comparison clock signal Clk_out2 is synchronized with the falling edge of the external clock clk so that the high pulse whiskey is shorter than the low pulse whiskey in the same manner as the first internal clock Clk_out1.

The first comparator 34 outputs a low state to the node A since there is no section in which the first internal clock signal Clk_out1 and the second internal clock signal Clk_out2 are simultaneously in a high state.

Since the second comparator 36 generates a section in which the first internal clock signal Clk_out1 and the second internal clock signal Clk_out2 are simultaneously low, the output of the NOA gate NOR1 is high by this period. It becomes a state. As a result, since the NMOS transistor N2 of the second CMOS inverter 34 is turned on, the output of the second CMOS inverter 34 becomes low and inverted in the second latch portion 35 so that the node B becomes high. Transition.

Therefore, when the node A is in the low state and the node B transitions to the high state, the duty of the first internal clock signal is shifted and the high pulse is narrower than the whis low pulse whistle.

Accordingly, according to the present invention, a high speed memory is realized by detecting a first internal clock signal and a second internal clock signal using a test mode signal, detecting a skewed direction and magnitude of the internal clock duty, and outputting a result to a data pin. It is effective to provide an internal clock duty check circuit that can respond to design and process changes.

Claims (12)

A first clock buffer unit configured to generate a first internal clock signal synchronized with a rising edge by buffering an externally input clock signal; A second clock buffer unit enabled by a test mode signal and configured to buffer the clock signal to generate a second internal clock signal synchronized with a falling edge; And A clock duty detector configured to compare the duty of the first internal clock signal with the second internal clock signal and output a result corresponding thereto when the test mode signal is enabled; And a clock duty check circuit. The method of claim 1, And the second clock buffer unit is configured in the same manner as the first clock buffer unit, and receives the clock signal opposite to the first clock buffer unit. The method of claim 1, The clock duty detector, A first comparator configured to determine whether there is a section in which the first internal clock signal and the second internal clock signal remain the same at the same level and simultaneously output a first detection signal corresponding thereto; And A second comparator configured to determine whether there is a section in which the first internal clock signal and the second internal clock signal remain the same at the same time in a second level state and output a second detection signal corresponding thereto; And a clock duty check circuit. The method of claim 3, wherein And the clock duty detector outputs the first sense signal and the second sense signal to a data pin. The method of claim 3, wherein And the first level is a period in which the first internal clock signal and the second internal clock signal are simultaneously maintained in a high state. The method of claim 3, wherein And the first sensing signal is a signal output in a high state at the first level. The method of claim 3, wherein And the second level is a period in which the first internal clock signal and the second internal clock signal are kept in a low state at the same time. The method of claim 3, wherein And the second detection signal is a signal output in a high state at the second level. The method of claim 3, wherein The first comparison unit, A NAND gate for logically combining the first internal clock signal and the second internal clock signal; An inverter for inverting the output of the NAND gate; A first CMOS inverter for inverting the output of the inverter; And A first latch unit for latching an output of the second CMOS inverter; Clock duty check circuit comprising a. The method of claim 9, The first CMOS inverter, A clock duty check circuit comprising a PMOS transistor and an NMOS transistor connected in series between a power supply voltage and a ground voltage, a test mode signal is applied to a gate of the PMOS transistor, and an output of the inverter is applied to a gate of the NMOS transistor . The method of claim 3, wherein The second comparison unit, A noah gate for logically combining the first internal clock signal and the second internal clock signal; A second CMOS inverter for inverting the output of the noble gate; And A second latch unit for latching an output of the second CMOS inverter; Duty check circuit comprising a. The method of claim 11, The second CMOS inverter, A clock duty check, characterized in that a PMOS transistor and an NMOS transistor are connected in series between a power supply voltage and a ground voltage, a test mode signal is applied to a gate of the PMOS transistor, and an output of the NOA gate is applied to a gate of the NMOS transistor. Circuit.

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