KR100728960B1 - Device for driving the sense amplifier of a memory chip - Google Patents

Abstract

A driving device of a sense amplifier for a memory device of the present invention includes a voltage divider for outputting a second voltage by dropping a first voltage by a predetermined voltage, a gate for receiving the second voltage, and a power supply voltage of the memory device. And a driving voltage generator including a drain having a drain and a source for outputting a clamp voltage, wherein the clamp voltage is supplied at an initial stage of sensing operation of the sense amplifier to supply a driving voltage for overdriving the sense amplifier.

According to the present invention, the overdriving voltage can be lowered to prevent malfunction of a sense amplifier composed of a transistor having a low threshold voltage.

Description

Device for driving the sense amplifier of a memory chip

1 illustrates a general method of driving a sense amplifier.

2 is an example of a driving voltage generator conventionally used.

3A and 3B illustrate an embodiment of a driving voltage (clamp voltage) generator according to the present invention.

4 is a graph illustrating a change in clamp voltage according to a change in power supply voltage VDD.

FIG. 5 is a graph showing variation of voltage levels of the RTO terminal and the SB terminal (supply voltage terminal of the sense amplifier) when the control signals SAP1 and SAP2 described in the circuit of FIG. 1 are enabled.

The present invention relates to a memory device, and more particularly to a driving device of a sense amplifier.

As is well known, a memory device may be classified into a memory cell array that stores data and a peripheral circuit having a function of reading data from or writing data to the memory cell array.

The memory cell array may include a plurality of bit lines, a plurality of bit lines perpendicular to the bit lines, a sensing amplifier for amplifying data on the bit lines, and an operation mode (precharge, active, read or write operation) of the memory device. ) Is a concept that basically includes a circuit unit for adjusting the voltage level of the bit line.

This specification discusses, among others, a device for driving the sense amplifier.

As is well known, the sense amplifier amplifies the data on the bit line by receiving a driving voltage applied from the driving device in a read or write operation.

Hereinafter, a driving apparatus of a conventional sense amplifier will be described with reference to FIG. 1.

1 illustrates a general method of driving a sense amplifier.

In FIG. 1, the transistor T1 turned on / off by the control signal SAP1 applies the voltage VDDCLP to the RTO terminal of the sense amplifier 100, and the transistor T1 turned on / off by the control signal SAP2. T2) applies the voltage VCORE to the RTO terminal of the sense amplifier 100, and the transistor T3 turned on / off by the control signal SAN applies a ground ground voltage to the SB terminal of the sense amplifier.

 Here, the control signal SAP1 is a control signal that increases the RTO terminal voltage of the sense amplifier in a short time, that is, a control signal for overdriving, and is enabled at the initial stage of sensing operation of the sense amplifier, thereby enabling the RTO terminal of the sense amplifier. Supply the voltage VDDCLP. For reference, the voltage VDDCLP is a voltage supplied only at the beginning of a sensing operation and is higher than the core voltage VCORE, which is a normal driving voltage of the sense amplifier.

Next, the control signal SAP2 is enabled after the control signal SAP1 is disabled to enable the control signal SAP2 to supply the core voltage VCORE, which is a normal driving voltage, to the RTO terminal of the sense amplifier. Here, the RTO terminal is a supply voltage terminal of the sense amplifier.

Next, the control signal SAN serves to lower the SB terminal voltage of the sense amplifier to the ground level during the sensing operation. Here, the SB terminal is a supply voltage terminal of the sense amplifier.

In FIG. 1, initially supplying a voltage VDDCLP higher than the core voltage VCORE (ie, overdriving) and then supplying a stable core voltage VCORE afterwards to improve the operating speed of the sense amplifier. will be.

Hereinafter, the method of forming the voltage VDDCLP for overdriving will be described.

2 is an example of a driving voltage generator conventionally used.

In FIG. 2, the voltage VPP represents an internal high voltage generated by power pumping and is used to activate a word line, and the voltage VDD represents a supply voltage level supplied to the memory device from the outside.

As can be seen from Fig. 2, conventionally, the voltage VDD is applied to the drain of the transistor, and the ice voltage VPP is applied to the gate to output the clamp voltage VDDCLP. In general, when the voltage VDD is higher than the voltage VPP, the level of the clamp voltage VDDCLP is VPP-Vt (Vt is the threshold voltage of the transistor), and vice versa, approximately.

In general, the voltage VPP is considerably higher than the voltage VDD, so the clamp voltage VDDCLP is at the VDD level.

Therefore, when the control signal SAP1 of FIG. 1 is enabled high, a voltage is applied to the VDD level to the RTO terminal of the sense amplifier.

However, recently, a high speed memory device has been implemented, and a sense amplifier is implemented using a transistor having a low threshold voltage. For this reason, when a relatively high voltage (VDD) is applied to the RTO terminal of the sense amplifier, leakage of the sense amplifier itself is achieved. This causes the current to increase. This in turn causes a malfunction of the sense amplifier.

The present invention has been made to solve the above-described problem, and provides a sense amplifier driving apparatus capable of supplying a stable driving voltage (overdriving voltage) to the sense amplifier.

The present invention also provides a sense amplifier driving apparatus capable of supplying a stable driving voltage (overdriving voltage) to a sense amplifier composed of a transistor having a low threshold voltage.

A driving device of a sense amplifier for a memory device according to a first embodiment of the present invention includes a voltage divider for outputting a second voltage by a predetermined partial voltage drop, a gate for receiving the second voltage, And a driving voltage generator including a drain for receiving a power supply voltage and a transistor having a source for outputting a clamp voltage, wherein the clamp voltage is applied at an initial stage of sensing operation of the sense amplifier to supply a driving voltage for overdriving the sense amplifier. to be.

In the first embodiment, the clamp voltage is cut off when a predetermined time elapses from the initial application of the sensing operation.

In the first embodiment, the voltage divider is composed of a plurality of NMOS transistors connected in series with a diode between the first voltage and ground, and the second voltage is output from a terminal connecting the plurality of NMOS transistors to each other. Do. Here, the voltage magnitude relationship between the first voltage, the second voltage, and the clamp voltage is first voltage> second voltage> clamp voltage.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

For reference, the circuit of FIG. 1 applies equally to the embodiment of the present invention. Therefore, hereinafter, a circuit for supplying a stable clamp voltage will be described.

3A is an embodiment of a drive voltage (clamp voltage) generator according to the present invention.

The driving voltage generator of FIG. 3A includes a diode-type NMOS transistor T1 connected between a high voltage VPP and a terminal A, and a plurality of NMOS transistors T2 connected in series of a diode type between the terminal A and ground. , T3, and a gate connected to the terminal A, a drain connected to the voltage VDD, and an NMOS transistor T4 outputting a voltage VDDCLP to the source. Here, the diode type NMOS transistor refers to a transistor having a gate and a drain connected to each other.

As can be seen in FIG. 3A, the transistors T1, T2, T3 function similar to voltage dividers. In addition, the transistor T4 receives the voltage of the voltage drop terminal A as a gate and outputs the clamp voltage VDDCLP through the source.

Hereinafter, the operation of FIG. 3A will be described in more detail.

When the high voltage VPP is applied to the drain of the diode transistor T1, the voltage of the terminal A is VPP-Vt. Since the transistor T4 receives the voltage VPP-Vt of the terminal A through the gate, the clamp voltage VDDCLP output through the source of the transistor T4 is approximately VPP-2Vt. Here, although the threshold voltages of the transistors T1 and T4 are assumed to be the same, the threshold voltages may be different.

Here, the transistors T2 and T3 serve as resistors for stably maintaining the voltage of the terminal A. Therefore, it may not be necessary if necessary.

In another embodiment, when the gate of the terminal B and the transistor T4 is connected instead of the gate of the terminal A and the transistor T4, the clamp voltage VDDCLP is approximately VPP-3Vt. Will be. As such, embodiments of the present invention may be variously modified (see FIG. 3B).

The clamp voltage VDDCLP output from the embodiment of the driving voltage generator according to the present invention shown in FIG. 3A (or FIG. 3B) is applied to the clamp voltage terminal VDDCLP mentioned in FIG. 1.

Since the clamp voltage of the present invention is a relatively low voltage as compared with the conventional case, even if the threshold voltage is applied to the RTO terminal of the low sense amplifier, the possibility of leakage current is reduced. Thus, stable operation of the sense amplifier is possible. For reference, it should be noted that the clamp voltage VDDCLP of the present invention is still higher than the core voltage VCORE. This is because the clamp voltage is a voltage applied for overdriving at the beginning of the operation of the sense amplifier.

4 is a graph illustrating a change in clamp voltage according to a change in voltage VDD.

As shown, it can be seen that the clamp voltage output from the circuit of FIG. 3, which is an embodiment of the present invention, has a level lower than the conventional clamp voltage and higher than the core voltage VCORE.

FIG. 5 is a graph illustrating changes in voltage levels of the RTO terminal and the SB terminal according to the enable timing of the control signals SAP1 and SAP2 described in the circuit of FIG. 1.

As shown in the figure, a clamp voltage is applied in a section where the control signal SAP1 is maintained at a high level for overdriving the RTO terminal, and a core voltage is applied thereafter to maintain a stable RTO voltage. .

For reference, section a represents an overdriving section, section b represents a section in which the sense amplifier is qualitatively active (a read or write operation is performed during this section), and section c represents a precharge section.

When the clamp voltage, which is the output voltage of the driving voltage generator according to the present invention, is used as the RTO terminal voltage of the sense amplifier, malfunction of the sense amplifier can be reduced.

In addition, as described above, the clamp voltage of the present invention can be selected in various ways using the voltage division function. Accordingly, the embodiments that can be modified by those skilled in the art based on the disclosed embodiments should be considered to be within the technical scope of the present application.

Claims (4)

delete A drive device for a sense amplifier for a memory device, A voltage divider configured to output a second voltage by dropping the first voltage by a predetermined voltage; and A driving voltage generator comprising a transistor having a gate for receiving the second voltage, a drain for receiving a power supply voltage of a memory device, and a source for outputting a clamp voltage; The clamp voltage is a supply voltage for overdriving the sense amplifier that is applied at the beginning of a sensing operation of the sense amplifier and is cut off when a predetermined time elapses after being applied at the beginning of the sensing operation. Driving device. The method of claim 2, The voltage divider includes a plurality of NMOS transistors connected in series with a diode between the first voltage and ground, And the second voltage can be output from a terminal connecting the plurality of NMOS transistors to each other. The method of claim 2, And a voltage magnitude relationship between the first voltage, the second voltage, and the clamp voltage is a first voltage> a second voltage> a clamp voltage.

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