KR100728946B1 - Redundancy circuit in semiconductor memory device - Google Patents

Abstract

The present invention relates to a redundancy circuit of a semiconductor memory device, and more particularly, to a redundancy circuit of a semiconductor memory device capable of preventing an error operation caused by a resistance of a fuse.

The redundancy circuit of the semiconductor memory device of the present invention has a fuse-free decoder unit for pre-decoding the repair address detected by the programming state of the fuse, a repair address pre-decoded signal and a normal address signal received from the fuse-free decoder unit. A semiconductor memory comprising a pre-decoded signal input unit for receiving a pre-decoded signal, a comparator for comparing and detecting whether the received address pre-decoded signal is a repair address signal, and an initialization unit for initializing the output terminal of the comparator by a reset signal. It provides a redundancy circuit of the device.

Description

REDUNDANCY CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE}

1 is a circuit diagram for explaining a redundancy circuit of a conventional semiconductor memory device.

2 is a circuit diagram illustrating a redundancy circuit of the semiconductor memory device according to the present invention.

3 is an operation timing diagram of the redundancy circuit of FIG.

Explanation of symbols on the main parts of the drawings

100: address comparison unit 200: pre-decoding signal input unit

300: fuse predecoder section 310: first latch section

320: second latch portion 330: third latch portion

400: initialization unit

The present invention relates to a redundancy circuit of a semiconductor memory device, and more particularly, to a redundancy circuit of a semiconductor memory device capable of preventing an error operation caused by a fuse resistor.

In general, a fuse used in a circuit for determining a redundant redundant address is connected to a junction portion of a MOS, and serves to block or provide an electrical path between a source and a drain of the MOS according to the cut state. It is possible to compare the input predecoded address with the address based on the value of the fuse ROM based on the state of the fuse.

1 is a redundancy circuit diagram of a semiconductor memory device according to the prior art.

As shown in the drawing, a PMOS transistor P0 used as a pull-up device with the redundancy enable signal F_EVALB as a gate input, and a reset NMOS transistor RN for resetting the redundancy circuit part while gated in the redundancy enable signal are provided. do.

The redundancy enable signal F_EVALB is a fuse box enable signal. The redundancy enable signal F_EVALB is a signal that enables a fuse box by checking a fail / normal when an address is input. In this specification, a redundancy enable signal is described.

The pre-decoded address signal (three-bit address signal is pre-decoded and six decoded signals are input) is commonly connected to the drain terminal of the PMOS transistor P0 and the drain terminal of the reset NMOS transistor RN. An address comparator 10 comprising first to sixth NMOS (N1 to N6) transistors as inputs, and respective fuses F0 to F6 connected to the source terminals of the first to sixth NMOS transistors, and grounded. And a pre-decoded signal input unit 30 for inputting a pre-decoded signal. At this time, the drain terminal of the PMOS transistor P0 and the drain terminal of the reset NMOS transistor RN are referred to as output nodes OUT.

Briefly, the operation thereof is as follows.

Pre-decoded addresses input to the pre-decoding signal input unit 30 are input to the plurality of NMOS transistors N1 to N6 to maintain the turn-on or turn-off states of the respective NMOS transistors according to the addresses. In addition, the on / off state of each of the fuses F1 to F6 is cut to match the address to be repaired.

When the pulse signal of the redundancy enable signal F_EVALB transitions from the high potential to the low potential, the PMOS transistor P0 is turned on at the PO to transfer the power supply voltage level Vdd to the output node OUT.

In this case, if at least one electrical path between the output node OUT and the ground potential Vss is formed, that is, any one of the first to sixth NMOS transistors N1 to N6 is turned on and connected to the transistor. If there is a passage where the fuse is not cut, current from the power supply voltage level delivered to the output node OUT is transferred to the ground potential, and the value of the output node maintains the low level.

In addition, the fuses of the passages connected to the NMOS transistors turned on according to the gated pre-decoding address signal among the first to sixth NMOS transistors are all cut, so that an electrical passage between the output node OUT and the ground potential Vss is generated. In the case of being blocked, the output of the output node OUT outputs a high potential value through the PMOS transistor P0.

However, when the electrical path between the output node OUT and the ground potential Vss is formed, and the output node OUT maintains the 'low' level, the resistance of the fuse designed by the Rs (Sheet Resistance) of the material of the fuse layer is high. If the process is done, it may cause a malfunction. That is, the resistance value of the fuse has a problem that the output node (OUT) may have a value close to the high potential.

Accordingly, an object of the present invention for solving the above problems is to add a MOS to the address comparison unit to use a low resistance value in the operating region, which is one of the resistance characteristics of the MOS, thereby preventing a malfunction of the conventional redundancy circuit. It is to provide a redundancy circuit of a memory device.

The redundancy circuit of the semiconductor memory device of the present invention for achieving the above object is, a fuse-free decoder unit for pre-decoding the repair address detected by the programming state of the fuse, a repair address pre-decoded signal received from the fuse-free decoder unit and A pre-decoding signal input unit for receiving a normal address signal pre-decoded signal, a comparator for detecting whether the received address pre-decoded signal is a repair address signal, and an initialization unit for initializing the output terminal of the comparator by a redundancy enable signal. It is characterized by providing a redundancy circuit of a semiconductor memory device configured.

In this case, the fuse predecoder unit includes first to Nth latch units each having a pair of first and second output nodes output to the address comparison unit, and each of the latch units and a power supply voltage source. A parallel connection with each of the NMOS transistors and the respective NMOS transistors for discharging the power supply voltage level output from the respective fuses to the ground potential while the first to Nth fuses and the potential of the first node are respectively gate inputs. Each capacitor is characterized by including.

The address comparison unit may be a gate input of the pre-decoded address signal, and a plurality of predecoding signal reception NMOS transistors having a drain terminal commonly connected to the pull-up device and the pull-down device, and the NMOS transistors for receiving the pre-decoding signal. And a fuse predecoding signal receiving NMOS transistor connected in series and configured to discharge each of the first and second output nodes from the fuse predecoder unit as a gate input to the ground potential.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

2 is a circuit diagram of a redundancy circuit of a semiconductor memory device according to an embodiment of the present invention.

 As shown, an externally input address for accessing a memory cell outputs a pre-decoded address signal through a predecoder, which is input to the predecoded signal input unit 200 to provide an address comparison unit. Is passed to 100.

After the repair determines the state of the fuse in accordance with the required address, the output of the fuse address is transferred to the address comparison unit 100 via the fuse predecoder 300.

In addition, an initialization unit 400 for initializing the output terminal of the address comparison unit 100 with a reset signal is provided.

Looking at the specific configuration of the redundancy circuit having such a configuration as follows.

First, the initialization unit 400 uses a redundancy enable signal F_EVALB as a gate input and a PMOS transistor P0 used as a pull-up device, and a redundancy circuit part used as a pull-down device while gated a redundancy redundancy enable signal. A reset NMOS transistor RN having a function of resetting is provided.

The pre-decoded address signal (three-bit address signal is pre-decoded and six decoded signals are input) is commonly connected to the drain terminal of the PMOS transistor P0 and the drain terminal of the reset NMOS transistor RN. The first to sixth NMOS (N1 to N6) transistors as inputs and the output signals of the fuse predecoder unit 300 are gate inputs, and are respectively connected in series with the first to sixth NMOS transistors to discharge to ground potentials; The address comparison unit 200 includes seventh to twelfth NMOS transistors N7 to N12.

In this case, the fuse-free decoder unit 300 input to the gate terminal of each of the seventh to twelfth NMOS transistors N7 to N12 may include the first to third latch units 310 and 320 having a pair of output nodes. 330 and each of the first to third fuses F1 to F3 connecting the latch unit to the power supply voltage source Vdd. Here, the first to third latch units are two inverters, that is, the first latch unit 310 is a first inverter 312 that inverts the output signal of the first fuse F1 connected to the power source voltage source Vdd and the inversion thereof. A second inverter 314 for reversing the received signal is latched. In this case, output signals of the first inverter 312 and the second inverter 314 are input to the gates of the seventh and eighth NMOS transistors of the address comparison unit 100, respectively. In addition, the second latch portion 320 and the third latch portion 330 also have the same configuration as the first latch portion 310, and the third and fourth inverters 322 and 324 and the fifth and sixth inverters, respectively. 332, 334.

In addition, the fuse pre-coder unit 300 uses the output signals of the first, third, and fifth inverters 314, 324, 334 as gate inputs, respectively, and grounds the power voltage level output from each fuse. Thirteenth to fifteenth NMOS transistors N13 to N15 to be discharged to each other; and first to third capacitors C1 to C3 connected in parallel with the thirteenth to fifteenth NMOS transistors, respectively.

The operation of this is as follows.

The address signal is input to the address comparison unit 100 by the pre-decode signal input unit 200 and the fuse predecoder unit 300, and the address output from the fuse predecoder unit 300 is set when the fuse ROM is set. After the determination, the value is maintained unless the semiconductor memory device is powered off. Whenever the input of the external normal address is changed, the comparison circuit of the address comparison section 100 operates. Here, the operation time point of the address comparison unit 100 is determined by turning on the PMOS transistor P0 while the redundancy enable signal F_EVALB transitions from the 'high' level to the 'low' level.

When the PMOS transistor P0 is turned on, the voltage level from the power supply voltage source Vdd is transmitted to the output node OUT of the address comparison unit 100. At this time, each NMOS transformer (for example, N1 and N7, N2, N8, etc.) connected in series by the combination of the pre-inputted normal predecoded address of the predecoded signal input unit 200 and the fuse predecoded address is connected. When at least one is turned on, its voltage level transitions to high potential at ground potential.

The state at this time indicates that the normal address and the address set in the fuse ROM are different from each other. On the contrary, when each NMOS transistor mode connected in series is turned off, this means that all of the input external address and the address by the fuse are turned off. It means that the bits are all the same. At this time, the output node of the address comparison unit 100 maintains the state of the high potential transmitted from the power supply voltage source Vdd.

In more detail, it will be described below on the assumption that the first to third fuses F1 to F3 are connected to each other. The power supply voltage level is then inverted to the 'low' level by the first, third, and fifth inverters 312, 322, 332, and accordingly the eighth, tenth, and twelfth NMOS transistors N8 and N10 ( N12) is turned off. In addition, the seventh, ninth, and eleventh NMOS transistors may be inverted to the 'high' level by the second, fourth, and sixth inverters 314, 324, 334. N7, N9, and N11 are turned on to set the fuse predecoder unit 300.

In this case, a pre-decoded signal of 010101 for address 111 to be input to the predecoder to perform a redundancy operation is input to the predecoding signal input unit 200. Then, the first, third, and fifth NMOS transistors N1, N3, and N5 are turned off, and the second, fourth, and sixth NMOS transistors N2, N4, and N6 are turned on. Therefore, the output node OUT of the address comparison unit 100 outputs a 'high' level as soon as the redundancy enable signal F_EVALB transitions from a high level to a low level, and this signal is a redundancy enable signal F_EVALB. Redundant operation is performed until the transition to the 'high' level again.

3 is a timing diagram illustrating the above-described operation.

As shown, when the pre-decoded address signal is input, if the signal is a normal address signal, even if the redundancy enable signal F_EVALB is enabled at a low level, the output node OUT of the address comparison unit 100 is' The low level is maintained, the redundancy address signal is pre-decoded and inputted, and the output node OUT of the address comparison unit 100 becomes 'high' when the redundancy enable signal F_EVALB transitions from the high level to the low level. 'Transition to the level to perform the redundancy operation.

In the above-described embodiment, the input of the address is illustrated as 3 bits, but this may vary depending on the size of the memory device.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

 According to the redundancy circuit of the semiconductor memory device of the present invention described above, by arranging the fuse-free decoder unit 300, a stable output can be expected regardless of variations in resistance of the fuse layer that may occur in the process of using the fuse layer. The number of fuses can be reduced, effectively reducing the area of the device.

Claims (7)

In the redundancy circuit of a semiconductor memory device, A fuse-free decoder section for pre-decoding the repair address detected by the programming state of the fuse; A pre-decoded signal input unit configured to receive a repair address pre-decoded signal and a normal address signal pre-decoded signal received from the fuse-free decoder unit; A comparison unit for comparing and detecting whether the received address pre-decoded signal is a repair address signal; And an initialization unit for initializing the output terminal of the comparator by a redundancy enable signal. The method of claim 1, The initialization unit is a redundancy circuit of the semiconductor memory device, characterized in that consisting of pull-up and pull-down elements. The method of claim 2, The pull-up device is a redundancy circuit of a semiconductor memory device, characterized in that the PMOS transistor. The method of claim 2, The pull down device is an NMOS transistor, redundancy circuit of a semiconductor memory device. The method of claim 1, The fuse predecoder unit includes first to Nth latch units including a pair of first and second output nodes output to the address comparison unit; First to Nth fuses connecting the respective latch units and a power supply voltage source; Respective NMOS transistors for discharging the power supply voltage level output from the respective fuses to ground potentials, respectively, with the potential of the first node as a gate input; And a respective capacitor connected in parallel with each of the NMOS transistors. The method of claim 5, Each latch unit, A first inverter for inverting each fuse output signal connected to the power supply voltage source; And a second inverter for reversing the inverted signal to form a latch. The method of claim 1, The address comparison unit, A plurality of NMOS transistors for receiving a pre-decoded address signal having a gate input and having a drain terminal commonly connected to the pull-up element and the pull-down element; And a fuse predecoding signal receiving NMOS transistor connected in series with each of the NMOS transistors for receiving a predecoding signal and discharging each of the first and second output nodes from the fuse predecoder unit as a gate input to a ground potential. A redundancy circuit of a semiconductor memory device.

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