KR100713641B1 - Liquid Crystal Display Device And Method of Fabricating The Same - Google Patents

Abstract

The present invention is to prevent the opening of the test lead line occurs at the intersection of the test lead line connected to the odd-numbered gate line and the even-numbered gate line when inspecting the thin film transistor array to enable the verification of the TFT array yield A liquid crystal display device and a method for manufacturing the same.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: a first test pad unit supplying a first scan signal to odd-numbered gate lines; A second test pad part supplying a second scan signal to even-numbered gate lines; A first test lead line connecting the odd-numbered gate line and the first test pad part; A second test lead line connecting the even-numbered gate line and the second test pad part and crossing the first test line, wherein a cross region of the first and second test lead lines is formed on a substrate; An electrode; A gate insulating film formed on the gate electrode; An active layer formed on the gate insulating film; A metal electrode formed on the active layer; A passivation layer formed to overlap the metal electrode; A transparent electrode is formed on the passivation layer, and the transparent electrode contacts the side surface of the metal electrode exposed to the outside.

According to an embodiment of the present invention, both sides of a metal electrode formed at an intersection portion of an inspection gate line connected to an odd-numbered gate line and an even-numbered gate line are connected to a transparent electrode, thereby preventing the opening of the transparent electrode by arcing to scan a signal The opening of the transmission line can be prevented.

Description

Liquid crystal display device and method for manufacturing the same {Liquid Crystal Display Device And Method of Fabricating The Same}             

1 is a plan view showing a conventional liquid crystal display device.

FIG. 2 is a plan view showing in detail an enlarged portion "A" shown in FIG.

3 is a cross-sectional view taken along the line "B-B '" of the test lead line shown in FIG.

4 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

  1 substrate 5 thin film transistor array

  7,9: test pad 11: thin film transistor

  13: gate line 15: data line

  17,18: inspection lead line 21,37: contact hole

  23,41: transparent substrate 25,39: gate electrode

  27,43 gate insulating film 29,45 active layer

  31,47 metal electrode 33,49 passivation layer

  35,51: transparent electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same. In particular, in the inspection of a TFT array, an inspection lead line generated at a portion where an inspection gate line connected to an odd-numbered gate line and an even-numbered gate line intersect each other is prevented. The present invention relates to a liquid crystal display device and a method of manufacturing the same for preventing the yield of a TFT array from being prevented.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter, referred to as TFT) as a switching element. Such liquid crystal display devices can be miniaturized compared to CRTs, and are widely used in personal computers and notebook computers, as well as office automation devices such as photocopiers, portable devices such as cell phones and pagers. .

In general, a liquid crystal display device corresponds to a video signal such as a television signal in a pixel matrix (Picture Element Matrix or Pixel Matrix) in which pixels are arranged at respective intersections of the gate lines 13 and the data lines 15 as shown in FIG. 1. The image to be displayed is displayed. Each of the pixels includes a liquid crystal cell 12 for adjusting the amount of transmitted light according to the voltage level of the data signal from the data line 15 and a liquid crystal cell from the data line 15 in response to a scan signal from the gate line 13. A thin film transistor (hereinafter referred to as "TFT") 11 for switching the data signal to be transmitted to (12). As described above, the liquid crystal display in which the TFTs 11 and the liquid crystal cells 12 are formed at the intersection where the data lines 15 and the gate lines 13 intersect is inspected for abnormality through an inspection process.

Briefly describing the inspection process, first, a voltage level corresponding to the data signal is applied to the data lines 15 so that the data signal is transferred to the liquid crystal cells 12 through the TFTs 11 positioned in the TFT array unit 5. To be transmitted continuously. At the same time, the first test pad unit 7 and the even gate line connected to the odd-numbered gate lines X1, X3, X5 ... among the gate lines 13 and the first test lead line 17. The voltage level corresponding to the scan signal is sequentially applied to the second test pad unit 9 connected to the (X2, X4, X6, ..., Xn) and the second test lead line 18. As such, the TFTs 11 connected to the odd-numbered gate lines X1, X3, X5... Are turned on by the scan signal applied to the first test pad unit 7, and at the same time, the data lines are turned on. Data signals applied to (Y1 to Yn) are transmitted to the liquid crystal cells 12 to drive the liquid crystal cells 12. Similarly, the liquid crystal cells 12 connected to the even-numbered gate lines X2, X4, X6,..., Xn are driven by the scan signal applied to the second test pad unit 9. Here, when any one of the gate line 13 and the data line 15 is shorted or open, the liquid crystal cells 12 corresponding to the line are not driven.

By such a method, it is possible to inspect a defect of the liquid crystal display device such as a short circuit or an open state of lines generated in the TFT array unit.                         

However, the first test lead lines 17 and the second test lead line 18, which are connected to the first test pad part 7 and the second test pad part 9, such as the portion “A” shown in FIG. 1. ), An overlapping portion is formed, and due to the arcing occurring in the overlapping portion, odd-numbered gate lines (X1, X3, X5 ...) and even-numbered gate lines (X2, X4, X6) Any one of ..., Xn becomes an open state, which causes a problem that the gate signal transmitted to the TFT array unit 5 is blocked.

This will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 is a plan view showing the portion "A" shown in FIG. 1 in detail, and FIG. 3 is a cross-sectional view taken along the line "B-B '" of the test lead line shown in FIG.

Referring to FIG. 2, first, the second test lead line 18 extending from the second test pad part 9 is connected to the even-numbered gate line X2 through the contact hole 21, and the odd-numbered gate line It is formed like FIG. 3 so that it may not be connected with (X1).

Referring to FIG. 3, the odd-numbered gate lines X1 and even-numbered gate lines X2 may include a gate electrode 25 formed on the transparent substrate 23 and a gate insulating film 27 formed on the gate electrode 25. And an active layer 29 formed on the gate insulating film 27, a metal electrode 31 formed on the active layer 29, a passivation layer 33 formed to cover the metal electrode 31, and a passivation layer 33. ) And a transparent electrode 35 formed thereon. In addition, the even-numbered gate line X2 is formed such that the transparent electrode 35 and the metal electrode 31 are connected through the contact hole 21. The gate electrode 25 is made of a metal material such as aluminum (Al) or copper (Cu). The gate insulating film 27 is made of silicon nitride or silicon oxide. The active layer 29 is formed of amorphous silicon or polycrystalline silicon that is not doped with impurities. The metal electrode 31 is formed of a metal such as chromium (Cr), molybdenum (Mo), titanium or tantalum, or a molybdenum alloy (Mo alloy) such as MoW, MoTa or MoNb. The passivation layer 33 is formed of an inorganic insulating material such as silicon oxide or silicon nitride, or an organic insulating material such as acryl-based organic compound, β-stagged-divinyl-siloxane benzocyclobutene (BCB) or perfluorocyclobutane (PFCB). . A contact hole 21 exposing the metal electrode 31 is formed in the passivation layer 33 included in the even-numbered gate line X2, and the metal electrode (through the contact hole 21 on the passivation layer 33) is formed. A transparent electrode 35 in contact with 31 is formed. The transparent electrode 35 is formed of indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO), which are transparent conductive materials.

However, the gate lines X1 and X2 in which the gate insulating layer 27, the active layer 29, the metal electrode 31, and the passivation layer 33 are sequentially formed have a high level difference. For this reason, the transparent electrode 35 of the high stepped portion is formed thinner than the transparent electrode 35 formed in the portion having a different thickness. In addition, the portion where the metal electrode 31 and the transparent electrode 35 are not directly connected, such as the portion “C”, is spaced at a predetermined interval and arced by a Schottky effect due to a current included in an externally applied gate signal. (Arching) occurs. As a result, the transparent electrode 35 having a thin thickness, such as the "C" portion, is opened by arcing, and thus it is impossible to transmit a scan signal to a gate line of the next stage, so that after verification of the TFT array, the yield verification becomes impossible.

Accordingly, an object of the present invention is to prevent the opening of the test lead line generated at the portion where the test lead lines connected to the odd-numbered gate line and the even-numbered gate line intersect each other, thereby verifying the yield of the TFT array. To provide a liquid crystal display and a method for manufacturing the same.

In order to achieve the above object, a liquid crystal display according to the present invention includes a first test pad unit for supplying a first scan signal to the odd-numbered gate lines; A second test pad part supplying a second scan signal to even-numbered gate lines; A first test lead line connecting the odd-numbered gate line and the first test pad part; A second test lead line connecting the even-numbered gate line and the second test pad part and crossing the first test line, wherein a cross region of the first and second test lead lines is formed on a substrate; An electrode; A gate insulating film formed on the gate electrode; An active layer formed on the gate insulating film; A metal electrode formed on the active layer; A passivation layer formed to overlap the metal electrode; A transparent electrode is formed on the passivation layer, and the transparent electrode contacts the side surface of the metal electrode exposed to the outside.
The transparent electrode is in contact with the gate insulating layer, the active layer, and the metal electrode laterally, and is formed on the passivation layer.
A contact hole exposing the metal electrode is formed in the passivation layer included in the even-numbered gate line, and the transparent electrode contacts the metal electrode through the contact hole.
The gate electrode includes at least one of aluminum or copper.
The gate insulating film includes at least one of silicon nitride or silicon oxide.
The active layer includes at least one of amorphous silicon or polycrystalline silicon.
The metal electrode includes any one of chromium, molybdenum, titanium, tantalum or molybdenum alloy.
The passivation layer includes any one of silicon oxide, silicon nitride, or an acryl-based organic compound, β-stagged-divinyl-siloxane benzocyclobutene (BCB), and perfluorocyclobutane (PFCB).
The transparent electrode includes any one of indium tin oxide, tin oxide or indium zinc oxide.
A method of manufacturing a liquid crystal display device according to the present invention includes forming odd and even gate lines on a substrate; Forming a first test pad part supplying a first scan signal to the odd-numbered gate lines and a second test pad part supplying a second scan signal to the even-numbered gate lines; Forming a first test lead line electrically connecting the odd-numbered gate line and the first test pad part, and electrically connecting the even-numbered gate line and the second test pad part and crossing the first test lead line. Forming an inspection lead line, wherein forming the first and second inspection lead lines comprises: forming a gate electrode at an intersection of the first and second inspection lead lines; Forming a gate insulating film on the gate electrode; Forming an active layer on the gate insulating film; Forming a metal electrode on the active layer; Forming a passivation layer to overlap the metal electrode; Forming a transparent electrode to be in contact with the side surface of the metal electrode exposed to the outside.
The transparent electrode contacts the gate insulating layer, the active layer, and the metal electrode laterally, and is formed on the passivation layer.
A contact hole for exposing the metal electrode is formed in the passivation layer included in the even-numbered gate line, and the transparent electrode is formed to contact the metal electrode through the contact hole.
The gate electrode includes at least one of aluminum or copper.
The gate insulating film is formed to include at least one of silicon nitride and silicon oxide.
The active layer is formed to include at least one of amorphous silicon or polycrystalline silicon.
The metal electrode is formed by including any one of chromium, molybdenum, titanium, tantalum or molybdenum alloy.
The passivation layer is formed of any one of silicon oxide, silicon nitride, or acrylic (Acryl) -based organic compounds, BCB (β-stagged-divinyl-siloxane benzocyclobutene), PFCB (perfluorocyclobutane).
The transparent electrode is formed to include any one of indium tin oxide, tin oxide or indium zinc oxide.

delete

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIG. 4.

4 is a cross-sectional view illustrating a liquid crystal display device according to an exemplary embodiment of the present invention. It is sectional drawing which cut | disconnected the inspection lead line shown in FIG. 2 at "B-B '".

Referring to FIG. 4, the odd-numbered gate lines X1 and even-numbered gate lines X2 may include a gate electrode 39 formed on the transparent substrate 41 and a gate insulating layer 43 formed on the gate electrode 39. And an active layer 45 formed on the gate insulating film 43, a metal electrode 47 formed to face the entire surface on the active layer 45, a passivation layer 49 formed to cover the metal electrode 47, and passivation. A transparent electrode 51 formed on the layer 49 is provided. In addition, the transparent electrode 51 is formed to be connected to one side surface of the gate insulating film 43, the active layer 45, the metal electrode 47, and the passivation layer 49.

In addition, the even-numbered gate line X2 is formed so that the transparent electrode 51 and the metal electrode 47 are connected through the contact hole 37. The gate electrode 39 is made of a metal material such as aluminum (Al) or copper (Cu). The gate insulating film 43 is made of silicon nitride or silicon oxide. The active layer 45 is formed of amorphous silicon or polycrystalline silicon that is not doped with impurities. The metal electrode 47 is formed of a metal such as chromium (Cr), molybdenum (Mo), titanium or tantalum, or a molybdenum alloy (Mo alloy) such as MoW, MoTa or MoNb. The passivation layer 49 is formed of an inorganic insulating material such as silicon oxide or silicon nitride, or an organic insulating material such as acryl-based organic compound, β-stagged-divinyl-siloxane benzocyclobutene (BCB) or perfluorocyclobutane (PFCB). . In the passivation layer 49 included in the even-numbered gate line X2, a contact hole 37 exposing the metal electrode 47 is formed, and the metal electrode (through the contact hole 37 on the passivation layer 49) is formed. A transparent electrode 51 in contact with 47 is formed. The transparent electrode 51 is formed of indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO), which are transparent conductive materials.

As described above, in the present invention, both sides of the metal electrode formed at a portion where the test lead lines connected to the odd-numbered gate line and the even-numbered gate line intersect each other are connected to the transparent electrode as shown by "D".

As described above, the liquid crystal display according to an exemplary embodiment of the present invention and a method of manufacturing the transparent electrode are formed on both sides of a metal electrode formed at a portion where test leads connected to odd-numbered gate lines and even-numbered gate lines cross each other. By being connected to, the opening of the scan signal transmission line can be prevented by preventing opening of the transparent electrode by arcing.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (18)

A first test pad part supplying a first scan signal to odd-numbered gate lines; A second test pad part supplying a second scan signal to even-numbered gate lines; A first test lead line connecting the odd-numbered gate line and the first test pad part; A second test lead line connecting the even-numbered gate line to the second test pad part and crossing the first test line; The intersection of the first and second test lead lines is A gate electrode formed on the substrate; A gate insulating film formed on the gate electrode; An active layer formed on the gate insulating film; A metal electrode formed on the active layer; A passivation layer formed to overlap the metal electrode; A transparent electrode formed on the passivation layer, And the transparent electrode is in contact with a side surface of the metal electrode exposed to the outside. According to claim 1, And the transparent electrode is formed on the passivation layer in contact with the gate insulating layer, the active layer, and the metal electrode in a side surface. According to claim 1, A contact hole exposing the metal electrode is formed in the passivation layer included in the even-numbered gate line, And the transparent electrode is in contact with the metal electrode through the contact hole. According to claim 1, And the gate electrode comprises at least one of aluminum or copper. According to claim 1, And the gate insulating film comprises at least one of silicon nitride and silicon oxide. According to claim 1, And the active layer comprises at least one of amorphous silicon and polycrystalline silicon. According to claim 1, The metal electrode is any one of chromium, molybdenum, titanium, tantalum or molybdenum alloy. According to claim 1, The passivation layer comprises any one of silicon oxide, silicon nitride or an acrylic organic compound, BCB (β-stagged-divinyl-siloxane benzocyclobutene), PFCB (perfluorocyclobutane). According to claim 1, And the transparent electrode includes any one of indium tin oxide, tin oxide, and indium zinc oxide. Forming odd and even gate lines on the substrate; Forming a first test pad part supplying a first scan signal to the odd-numbered gate lines and a second test pad part supplying a second scan signal to the even-numbered gate lines; Forming a first test lead line electrically connecting the odd-numbered gate line and the first test pad part, and electrically connecting the even-numbered gate line and the second test pad part and crossing the first test lead line. 2 forming a test lead line, Forming the first and second test lead lines Forming a gate electrode at an intersection of the first and second test lead lines; Forming a gate insulating film on the gate electrode; Forming an active layer on the gate insulating film; Forming a metal electrode on the active layer; Forming a passivation layer to overlap the metal electrode; And forming a transparent electrode to contact the side surface of the metal electrode exposed to the outside. The method of claim 10, And the transparent electrode is formed in contact with the gate insulating layer, the active layer and the metal electrode on the side surface and formed on the passivation layer. The method of claim 10, Forming a contact hole exposing the metal electrode in the passivation layer included in the even-numbered gate line, And the transparent electrode is in contact with the metal electrode through the contact hole. The method of claim 10, The gate electrode may include at least one of aluminum and copper. The method of claim 10, And the gate insulating film is formed of at least one of silicon nitride and silicon oxide. The method of claim 10, And the active layer is formed of at least one of amorphous silicon and polycrystalline silicon. The method of claim 10, The metal electrode may be formed of any one of chromium, molybdenum, titanium, tantalum or molybdenum alloy. The method of claim 10, The passivation layer may be formed of any one of silicon oxide, silicon nitride, or an acryl-based organic compound, BCB (β-stagged-divinyl-siloxane benzocyclobutene), or PFCB (perfluorocyclobutane). Manufacturing method. The method of claim 10, The transparent electrode may be formed of any one of indium tin oxide, tin oxide, and indium zinc oxide.

Images