KR100711347B1 - Controller for power converter - Google Patents

Abstract

In the present invention, the voltage vector control unit 11 determines the voltage vector output by the power converter within one control period of the PWM control and the time for outputting the voltage vector based on the voltage command values Vu, Vv, and Vw to the power converter. And a voltage vector adjusting unit 12 for adjusting the output time of the voltage vector input from the voltage vector control unit 11, and a semiconductor switch constituting the power converter based on the output time of the voltage vector adjusted by the voltage vector adjusting means. A firing pulse generator 13 for generating a signal for turning on and off the device, and the voltage vector adjusting unit 12 outputs a zero voltage vector without changing the relative ratio of the output time of voltage vectors other than the zero voltage vector. Adjust to secure the time above a certain value. As a result, a high voltage exceeding twice the DC bus voltage is suppressed. Can be controlled in three phases collectively.

Description

Control device of power converter {CONTROLLER FOR POWER CONVERTER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a power converter driven by PWM (pulse width modulation) control. In particular, an abnormal high voltage generated at a cable connection end of a load when the connection cable between the power converter and the load becomes long (hereinafter, It relates to a control device for suppressing "surge voltage".

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure explaining the connection cable of the inverter which is a power converter driven by PWM control, and a motor. In FIG. 1, a motor 2 is connected to an inverter 1 as a power converter via a connecting cable 3. The inverter 1 is a three-phase in which the switching operation of a semiconductor switch element (for example, an IGBT element) to be configured is controlled by PWM control by a control device (not shown) and is changed from a DC power supply of voltage Vdc into a step shape. The voltage uvw is generated and output to the motor 2 via the connection cable 3.

By the way, when the connection cable 3 between the inverter 1 and the motor 2 is long, a surge voltage exceeding twice the DC bus voltage Vdc may occur at the cable connection end of the motor 2. That is, the connecting cable 3 can be considered as a resonant circuit composed of wiring inductance and floating capacitance. However, when the connecting cable 3 becomes longer, the wiring inductance and floating capacitance increase together, so that the resonance frequency of the resonance circuit decreases. . As a result, since the voltage change of the next step shape is repeatedly applied while the resonance excited in the resonance circuit is not attenuated by the voltage change of the step shape generated by the inverter 1, the resonance is increased and the motor 2 The surge voltage which is higher than a normal voltage generate | occur | produces in the cable connection end of ().

With reference to FIG. 2 and FIG. 3, the content of the surge voltage which generate | occur | produces in the cable connection end of the motor 2 is demonstrated. 2 and 3 are diagrams showing line voltage waveforms at both ends of the connecting cable 3 shown in FIG. 1.

In Fig. 2A, the case where the voltage between the inverter terminals Vuv_inv is changed into a step shape of Vdc → 0 → Vdc is shown. At this time, if the pulse width of the voltage change coincides with 1/2 of the resonance period, as shown in Fig. 2B, the motor line line voltage Vuv_motor becomes a high voltage three times the DC bus voltage Vdc at the maximum.

In addition, in FIG. 3A, the case where the inverter line line voltage Vuv_inv changes from 0 to Vdc → -Vdc → 0 is shown. At this time, as shown in FIG.3 (b), the voltage between the motor end lines Vuv_motor becomes the high voltage of 4 times the DC bus voltage Vdc at maximum.

2 and 3, when the pulse width of the voltage change is sufficiently wide, the voltage change of the next step shape is applied after the resonance generated by the voltage change of the step shape is attenuated. It can be seen that no surge voltage over twice occurs.

In order to solve the problem of this surge voltage, for example, in Patent Documents 1 and 2, the firing pulse width of each IGBT element based on the line voltage pulse width of the inverter is monitored, and the maximum value of the firing pulse width is fixed. The technique which limits below a value and limits the minimum value of a firing pulse width to more than a fixed value is disclosed. Patent Document 1: US Patent No. 571130, Patent Document 2: US Patent No. 5990658.

For example, in patent documents 3 and 4, each phase voltage command value input to the PWM controller which produces | generates the firing pulse of each IGBT element is monitored, and the maximum value of each phase voltage command value is below a fixed value. The technique which limits and the minimum value of each phase voltage command value to more than a fixed value is disclosed. Patent Document 3: US Patent No. 5912813, Patent Document 4: US Patent No. 6014497.

However, since the firing pulse width or voltage command value is different for each phase, the limitation of the firing pulse width or voltage command value needs to be executed separately for each phase. That is, in order to suppress the surge voltage exceeding 2 times of the DC bus voltage Vdc by applying the technique disclosed in the above patent document, the maximum and minimum values of the firing pulse width of each IGBT element or each phase voltage command value are limited. If so, a plurality of control means for individually limiting the maximum and minimum values of each phase are required.

In this configuration, there is a problem in that the influence on other phases cannot be taken into consideration when the pulse width or the voltage command value of one phase is limited. In addition to this problem, there is a problem in that it is not possible to perform optimal limitation by treating all the images collectively.

This invention is made | formed in view of the above, and an object of this invention is to obtain the control apparatus of the power converter which can handle all phases collectively and can suppress the surge voltage exceeding 2 times of DC bus voltage optimally. do.

Disclosure of the Invention

In the present invention, in the power converter control device in which the output voltage is controlled by pulse width modulation control, the power converter outputs a voltage vector output within one control period of the pulse width modulation control and a time for outputting the voltage vector. Voltage vector control means for determining on the basis of the voltage command value to the power converter and voltage vector adjusting means for adjusting the output time of the voltage vector input from the voltage vector control means, wherein the output time of the zero voltage vector is zero; A voltage vector adjusting means for adjusting the output time of each voltage vector so as not to be below a predetermined value except for the exclusion, and a semiconductor switch element constituting the power converter based on the output time of the voltage vector adjusted by the voltage vector adjusting means; And a firing pulse generating means for generating a signal to be turned off.

According to the present invention, the surge voltage which is a high voltage exceeding twice the DC bus voltage can be effectively suppressed.

The following invention is characterized in that in the above invention, the voltage vector adjusting means adjusts the zero voltage vector output time to a predetermined value or more.

According to the present invention, since the resonance phenomenon due to switching of the semiconductor switch element can be attenuated during the output of the zero voltage vector by always ensuring the zero voltage vector output time at a predetermined value or more, the voltage exceeding twice the DC bus voltage. The surge voltage which is a high voltage can be suppressed effectively.

In the invention described above, in the invention described above, the voltage vector adjusting means adjusts the output time of the zero voltage vector to a predetermined value or more when the output time of the zero voltage vector is longer than a predetermined value. Is characterized by adjusting the output time of the zero voltage vector to zero.

According to the present invention, a surge voltage that is higher than twice the DC bus voltage by selecting a zero voltage vector output time of a predetermined value or zero voltage vector output time in a rounded manner is selected. It can be suppressed.

In the above invention, in the above invention, when the voltage vector adjusting means inputs, as a unit, a voltage vector within two or more control cycles of the pulse width modulation control from the voltage vector control means. When the sum of the output time of all zero voltage vectors in more than one control period is shorter than a fixed value, the output time of the zero voltage vector which exists in the middle of two adjacent periods is adjusted to zero, and that much is set to 2 And to distribute to the output time of the zero voltage vector present at both ends of the period.

According to the present invention, when two or more control cycles of pulse width modulation control are controlled as one unit, the remaining zero voltage vector is removed by eliminating zero voltage vectors existing in the middle of two adjacent cycles. The output time can be doubled. As a result, in one control cycle, since the sum of the output time of non-zero voltage vectors other than the zero voltage vector does not need to be changed until the sum of the output time of the zero voltage vector is less than the predetermined value, It can be made small. According to this method, either a zero voltage vector output time of a predetermined value or more is provided or a zero voltage vector output time is zero. Therefore, as in the above invention, a surge voltage that is a high voltage exceeding twice the DC bus voltage as described above. Can be suppressed.

In the above invention, in the above invention, when the voltage vector adjusting means inputs, as a unit, a voltage vector within two or more control cycles of the pulse width modulation control from the voltage vector control means. When the sum of the output time of all zero voltage vectors in more than one control period is shorter than a fixed value, it adjusts so that the output time of the same voltage vector in two or more control periods may be combined together. do.

According to the present invention, in the case where two or more control cycles of the pulse width modulation control are controlled as one unit, the zero voltage vector is obtained by summing the output time of the same voltage vector in the two or more control cycles into one. The output time of each voltage vector can be doubled, including. As a result, in one control cycle, since the sum of the output time of non-zero voltage vectors other than the zero voltage vector does not need to be changed until the sum of the output time of the zero voltage vector is less than the predetermined value, It can be made small. According to this method, since the zero voltage vector output time more than a fixed value is always ensured, the surge voltage which is a high voltage exceeding twice the DC bus voltage like the said invention can be suppressed.

In the invention described above, the above invention is provided with delay means for delaying the voltage vector output by the voltage vector adjusting means to the voltage vector adjusting means after one control period delay, and the voltage vector adjusting means is zero. If the output time of the voltage vector is shorter than a predetermined value, the current vector is received from the delay means for the adjustment before one control period, and this vector period is output according to whether or not the vector output at the end of the previous period is the zero voltage vector. It is characterized by adjusting the output time of one of both zero voltage vectors at to zero and distributing the same to the output time of the other.

According to the present invention, since the voltage vector is adjusted to combine the zero voltage vectors existing at the beginning and the end of the pulse width modulation control period into one, the output time of the zero voltage vector can be doubled. As a result, since it is not necessary to change the sum of the output time of nonzero voltage vectors other than a zero voltage vector until the sum of the output time of a zero voltage vector is less than a predetermined value, an error can be made small. According to this method, either a zero voltage vector output time of a predetermined value or more is provided or a zero voltage vector output time is zero. Therefore, as in the above invention, a surge voltage that is a high voltage exceeding twice the DC bus voltage as described above. Can be suppressed.

In the above invention, the invention further comprises delay means for outputting the voltage vector output by the voltage vector adjusting means and the output time of the completion of the adjustment to the voltage vector adjusting means by delaying the one control period. The voltage vector adjusting means receives, from the delay means, the voltage vector used in the adjustment before one control period and its output time, and outputs the zero voltage vector adjusted and outputted last in the previous period and the voltage vector in this period. If the sum with the output time of the zero voltage vector first inputted from the control means is shorter than the fixed value, the output time of the zero voltage vector initially output in this period is adjusted and outputted from the constant value to the end of the previous period. It is characterized by adjusting so that the output time of one zero voltage vector may be subtracted.

According to the present invention, since the output time of the zero voltage vector output in this period is determined using the adjusted output time of the zero voltage vector output last in the previous pulse width modulation control period, the zero voltage vector Even in the case where the pulse width modulation control period is over, the output time of the zero voltage vector can be secured more than a certain value. Therefore, similarly to the above invention, it is possible to suppress the surge voltage which is a high voltage exceeding twice the DC bus voltage.

In the above invention, in the above invention, there is provided a delay means for delaying the error according to the output time adjustment of the voltage vector output by the voltage vector adjusting means to the voltage vector adjusting means by delaying the one control period. The voltage vector adjusting means has a function of calculating an error in accordance with the output time adjustment of the voltage vector, and the voltage vector adjusting means has a function of calculating the error calculated in the previous period inputted from the delay means in the output time of the voltage vector input from the voltage vector controlling means. If the output time of the zero voltage vector is longer than the predetermined value with respect to the output time of the corrected voltage vector, the output time of the zero voltage vector is adjusted to be secured to a fixed value or more. It is characterized by adjusting the time to zero.

According to the present invention, it is possible to suppress the surge voltage which is a high voltage exceeding twice the DC bus voltage as in the above invention, but outputs in this cycle by using the adjustment error in the previous pulse width modulation control cycle. Since the output time of the voltage vector is corrected to eliminate the influence of the previous adjustment, the end point of the current magnetic flux vector trajectory can be matched to a desired point, thereby minimizing fluctuations in the magnetic flux vector trajectory due to suppression of the surge voltage. can do.

In the following invention, in the above invention, the vector adjusting means adjusts the output time of the zero voltage vector to a predetermined value or more without changing the relative ratio of the output time of the voltage vectors other than the zero voltage vector. It is characterized by.

According to the present invention, the fluctuation of the magnetic flux vector trajectory due to the suppression of the surge voltage can be minimized by devising the voltage vector adjustment.

In the following invention, in the above invention, in the case where the voltage vector adjusting means adjusts the output time of the zero voltage vector to zero, the output time of voltage vectors other than the zero voltage vector is also equal to or higher than a predetermined value or zero. It is characterized in that the adjustment as possible.

According to the present invention, when the output time of a zero voltage vector is adjusted to zero, a surge voltage may be generated depending on the output time of a non-zero voltage vector other than the zero voltage vector, but a limitation can be applied to the surge voltage. As a result, the surge voltage, which is a high voltage exceeding twice the DC bus voltage, can be suppressed reliably.

In the following invention, in the above invention, the voltage vector adjusting means outputs the voltage vector output at the end of the previous period and the first time in this period when the output time of the zero voltage vector is adjusted to zero. When the voltage vector to be different is different, the voltage vector output first in this period is changed to the voltage vector output last in the previous period.
According to the present invention, when the output time of a zero voltage vector is adjusted to zero, a surge voltage may be generated depending on the output time of a non-zero voltage vector other than the zero voltage vector, but a limitation can be applied to the surge voltage. As a result, the surge voltage, which is a high voltage exceeding twice the DC bus voltage, can be suppressed reliably.
According to each of the above inventions, the adjustment of the voltage vector output time is based on the output time of the voltage vector, which is a common parameter of three phases generated based on the three-phase voltage command, and therefore, all phases are adjusted in one adjustment. The suppression effect of the surge voltage can be obtained.

1 is a view for explaining a connection cable between an inverter and a motor, which is a power converter driven by PWM control;

FIG. 2 is a diagram showing line voltage waveforms at both ends of the connecting cable shown in FIG. 1; FIG.

3 is a diagram showing a line voltage waveform at both ends of the connecting cable shown in FIG. 1;

4 is a block diagram showing a configuration of a control device of a power converter according to the first embodiment of the present invention;

5 is a circuit diagram showing the basic configuration of a three-phase voltage inverter used in this embodiment as a power converter driven by PWM control;

FIG. 6 is a diagram for explaining a relationship between an IGBT element and a voltage vector that are turned on in eight control states of the inverter shown in FIG. 5; FIG.

7 is a diagram illustrating a voltage vector,

8 is a diagram illustrating a relationship between a phase and a voltage vector;

9 is a flowchart for explaining the operation of the voltage vector adjusting unit shown in FIG. 4;

10 is a diagram for explaining a trajectory of a magnetic flux vector when the voltage vector is adjusted;

11 is a time chart for explaining the operation of the firing pulse generator shown in FIG. 4;

12 is a diagram illustrating a relationship between a trend of a voltage vector and line voltage;

FIG. 13 is a diagram showing line voltage patterns extracted by focusing on pulse polarity, zero voltage vector output time, and vector output time other than zero voltage; FIG.

FIG. 14 is a diagram for explaining surge voltage generated by the line voltage shown in FIG. 13; FIG.

15 is a flowchart for explaining the operation of the voltage vector adjusting unit included in the control device of the power converter according to the second embodiment of the present invention;

16 is a block diagram showing a configuration of a control device of a power converter according to a third embodiment of the present invention;

17 is a flowchart for explaining the operation of the voltage vector adjusting unit shown in FIG. 16;

18 is a flowchart for explaining the operation of the voltage vector adjusting unit included in the control device of the power converter according to the fourth embodiment of the present invention;

19 is a block diagram showing a configuration of a control device of a power converter according to a fifth embodiment of the present invention;

20 is a flowchart for explaining the operation of the voltage vector adjusting unit shown in FIG. 19;

21 is a flowchart for explaining the operation of the voltage vector adjusting unit included in the control device of the power converter according to the sixth embodiment of the present invention;

Fig. 22 is a block diagram showing the construction of a control device of a power converter according to a seventh embodiment of the present invention;

FIG. 23 is a flowchart for explaining the operation of the voltage vector adjusting unit shown in FIG. 22;

24 is a view for explaining an operation of an error operation performed by the voltage vector adjusting unit shown in FIG. 22;

25 is a flowchart for explaining the operation of the voltage vector adjusting unit included in the control device of the power converter according to the eighth embodiment of the present invention;

Fig. 26 is a flowchart for explaining the operation of the voltage vector adjusting unit included in the control device of the power converter according to the ninth embodiment of the present invention.

Best Mode for Carrying Out the Invention

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the control device of the power converter according to the present invention will be described in detail.

(Example 1)

4 is a block diagram showing a configuration of a control device of a power converter according to the first embodiment of the present invention. The control device shown in FIG. 4 includes a voltage vector control unit 11, a voltage vector adjusting unit 12, and a firing pulse generator 13.

The voltage vector control unit 11 selects a voltage vector that the power converter outputs within one control period of the PWM control from the voltage command values Vu, Vv, and Vw of each phase of the power converter (V0, V1, V2, V7 in the illustrated example). ), The output time t0, t1, t2, t7 is calculated.

The voltage vector adjusting unit 12 outputs the voltage vector (V0, V1, V2, V7) input from the voltage vector control unit 11 as it is, and also outputs the times of the voltage vector (t0, t1, t2). , t7) is adjusted so that the zero voltage vector output time becomes a predetermined value or more (t0 ', t1', t2 ', t7').

The firing pulse generator 13 turns on and off each semiconductor switch element constituting the power converter based on the voltage vector input from the voltage vector adjuster 12 and the output time of the voltage vector adjusted by the voltage vector adjuster 12. The signals "PQ1, PQ2, PQ3, PQ4, PQ5, PQ6, and PQ7" are generated.

Hereinafter, specific operations of each block will be described. First, the operation of the voltage vector control unit 11 will be described with reference to FIGS. 5 to 8. 5 is a circuit diagram showing the basic configuration of a three-phase voltage inverter used in this embodiment as a power converter driven by PWM control. FIG. 6 is a diagram illustrating a relationship between an IGBT element and a voltage vector that are turned ON in eight control states of the inverter shown in FIG. 5. 7 is a diagram illustrating a voltage vector. 8 is a diagram illustrating a relationship between a phase and a voltage vector.

As shown in Fig. 5, the three-phase voltage inverter connects three sets of semiconductor switch elements Q1 and Q4, Q3 and Q6 and Q5 and Q2 connected in series to the DC power supply 15 in parallel. One configuration. Each semiconductor switch element has a built-in or attached flywheel diode. Each semiconductor switch element is, for example, an IGBT element, hereinafter referred to as an IGBT element. In the illustrated example, the IGBT elements Q1 and Q4 are u-phase, the IGBT elements Q3 and Q6 are v-phase, the IGBT elements Q5 and Q2 are w-phase, and three-phase voltage uvw is output from each connection terminal. .

Here, the on / off control state of the IGBT element is the upper arm IGBT element Q1, Q3, Q5 connected to the positive electrode side of the DC power supply 15 in each phase, or the lower arm IGBT element (connected to the negative electrode side). There are two kinds of states of Q4, Q6, and Q2) ON, and there are two kinds of states of 2x2x2 = 8 types in three phases.

Fig. 6 shows the relationship between these eight types, the on state of the IGBT element, and the voltage vector output by the three-phase voltage inverter. In FIG. 6, the voltage vector V0 is a vector when the IGBT elements Q4, Q6, and Q2 are on. The voltage vector V1 is a vector when the IGBT elements Q1, Q6, and Q2 are on. The voltage vector V2 is a vector when the IGBT elements Q1, Q3, and Q2 are on. The voltage vector V3 is a vector when the IGBT elements Q4, Q3, and Q2 are on. The voltage vector V4 is a vector when the IGBT elements Q4, Q3, and Q5 are on. The voltage vector V5 is a vector when the IGBT elements Q4, Q6, and Q5 are on. The voltage vector V6 is a vector when the IGBT elements Q1, Q6, and Q5 are on. The voltage vector V7 is a vector when the IGBT elements Q1, Q3, and Q5 are on.

The relationship between each phase and voltage vector V0-V7 is as showing in FIG. In Fig. 7, the voltage vectors V1 to V6 have a phase difference for each of [pi] / 3 [rad], and the magnitude is a vector equal to the voltage Vdc of the DC power supply 15. The voltage vectors V0 and V7 are vectors of magnitude 0 and are called zero voltage vectors. The phase of the voltage vector V1 coincides with the u phase, the phase of the voltage vector V3 coincides with the v phase, and the phase of the voltage vector V5 coincides with the w phase.

In the three-phase voltage inverter, voltages of arbitrary magnitude and phase can be output on average by changing the combination type and output time of the voltage vectors V0 to V7 to be output during the PWM control period T. The voltage vector control unit 11 selects the combination type of the voltage vectors V0 to V7 and determines the output time.

It is assumed that voltage commands Vu, Vv, and Vw of each phase are given by the equation (1).

The phase θ in this equation (1) increases with time, but can be considered constant during the short PWM control period T.

Selection of the combination type of the voltage vectors V0 to V7 is performed as shown in Fig. 8 in accordance with the value of the phase θ in the current PWM control period T. As shown in Fig. 8, the ranges of phase θ are 0 ≦ θ <π / 3, π / 3≤θ <2π / 3, 2π / 3≤θ <π, π≤θ <4π / 3, 4π / 3 6 of ≤θ <5π / 3 and 5π / 3≤θ <2π. The number of voltage vectors to select is four out of eight, but the combination is different for each range of phase θ. However, the zero voltage vectors V0 and V7 are included in all combinations.

In Fig. 8, when the phase θ in the current PWM control period T is in the range of, for example, 0 ≦ θ <π / 3, the combination of voltage vectors selected is V1, V2, V0, V7. The times t1, t2, t0, t7 for outputting the selected voltage vectors V1, V2, V0, V7 are given by equation (2), respectively.

That is, the output state of the voltage vector control part 11 shown in FIG. 4 has shown the output state when the phase (theta) in PWM control period T exists in the range of 0 <= (theta) <(pi) / 3. Hereinafter, it will be described using this. In the region where the phase θ in the PWM control period T is other than 0 ≦ θ <π / 3, the time for outputting the selected voltage vector is obtained by using the remainder obtained by dividing θ by π / 3 instead of θ in Equation (2). .

Next, the operation of the voltage vector adjusting unit 12 will be described with reference to FIGS. 9 and 10. 9 is a flowchart for explaining the operation of the voltage vector adjusting unit shown in FIG. 10 is a diagram for explaining the trajectory of the magnetic flux vector in the case where the voltage vector is adjusted.

In FIG. 9, if the phase θ is in the range of 0 ≦ θ <π / 3 as described above, the voltage vector adjusting unit 12 outputs the output time t1, t2, t0 of the voltage vector output from the voltage vector control unit 11. t7 is read (step ST10), and it is determined whether the total t0 + t7 of the output time of the zero voltage vector is longer than the minimum zero voltage vector output time Tz (step ST11).

As a result, when the total t0 + t7 of the output time of the zero voltage vector is longer than the minimum zero voltage vector output time Tz (step ST11: YES), the output time of adjusting the read output time t1, t2, t0, t7 as it is. t1 ', t2', t0 ', t7' (step ST12).

On the other hand, when the total t0 + t7 of the output time of the zero voltage vector is shorter than the minimum zero voltage vector output time Tz (step ST11: NO), the output time of the voltage vector is adjusted so that t0 '+ t7' = Tz. At this time, the output time t1 ', t2', t0 ', t7' of the adjusted voltage vector is obtained by the following equations (3) to (6) so as not to change the relative ratio of the output time of the voltage vectors V1 and V2 ( Step ST13).

Then, the output time t0 ', t1', t2 ', t7' of the voltage vectors V0, V1, V2, and V7 adjusted in step ST12 or step ST13 are output to the firing pulse generator 13 (step ST14). The voltage vectors V0, V1, V2, and V7 selected by the voltage vector control unit 11 are used as they are and output to the firing pulse generator 13.

As described above, when the voltage vector is adjusted, FIG. 10 is obtained by drawing the vector trajectory of the magnetic flux obtained by integrating the voltage. In Fig. 10A, the trajectory A of the magnetic flux vector for one cycle of the PWM control cycle before the adjustment of the voltage vector is displayed. In Fig. 10B, the trace A 'of the magnetic flux vector after the adjustment of the voltage vector is displayed. As the trajectory A of the previous magnetic flux vector secures the minimum zero voltage vector output time, the trajectory A 'becomes a trajectory A' and the trajectory is shortened. It is FIG. 10 (c) which overlapped and painted FIG. 10 (a) and (b).

10 (a) and 10 (b), the magnetic flux vectors φ0 and Φ7 are magnetic flux vectors corresponding to zero voltage vectors V0 and V7, respectively. Since the zero voltage vectors V0 and V7 have no magnitude, the magnetic flux vectors Φ0 and Φ7 stop at a point even if time passes. The magnetic flux vector φ1 is a magnetic flux vector corresponding to the voltage vector V1. The magnitude of the magnetic flux vector Φ1 is the product of the magnitude of the voltage vector V1 and the output time. The magnetic flux vector Φ2 is a magnetic flux vector corresponding to the voltage vector V2. The magnitude of the magnetic flux vector Φ 2 is the product of the magnitude of the voltage vector V 2 and the output time. The magnetic flux vectors? 1 and? 2 have a phase difference of? / 3 [rad] similarly to the voltage vectors V1 and V2.

When the voltage vector is output in the order of V0? V1? V2? V7, the traces A and A 'of the flux vector are in the order of? 0?? 1?? 2?? 7. When the load is an induction motor, since the magnetic flux vector corresponds to the stator magnetic flux, the trajectory A of the magnetic flux vector before the voltage vector adjustment unit 12 adjusts the voltage vector has a kind of voltage vector and an output time so that it smoothly follows the arc. It is selected, and even after adjusting the voltage vector in the voltage vector adjusting unit 12, it is required that the trace A 'of the magnetic flux vector smoothly follows the arc.

That is, when the output time of the zero voltage vectors V0 and V7 is increased so as not to change the relative ratios of the output times of the voltage vectors V1 and V2, the trace A (Fig. 10 (a)) of the flux vector before the adjustment is the trace A 'after the adjustment. 10 (b), but as shown in FIG. 10 (c), the triangle connecting the start point and the end point in the PWM control period T of the trajectory A 'is a triangle connecting the start point and the end point of the trajectory A'. Similar to each other. Therefore, in a state where the period T is sufficiently short and the arc can be seen in a straight line, the end point of the trajectory A 'also exists on the arc similarly to the trajectory A. For this reason, if the voltage vector is adjusted so as not to change the relative ratios of the output times of the voltage vectors V1 and V2, the trajectory A 'of the adjusted magnetic flux vector can also be smoothly shifted along the arc.

Next, the operation of the firing pulse generator 13 will be described with reference to FIGS. 6 and 11. 11 is a time chart for explaining the operation of the firing pulse generator shown in FIG. 4. The firing pulse generator 13 is configured for each IGBT from the voltage vectors V1, V2, V0, V7, which are outputs of the voltage vector adjuster 12, and the output time t1 ', t2', t0 ', t7' of the adjusted voltage vector. Generates on and off signals PQ1 to PQ6 of the device. That is, the relationship between the voltage vector and the IGBT device that is turned ON is shown in FIG. As shown in Fig. 11, the output time t1 ', t2', t0 ', t7' of the voltage vectors V1, V2, V0, and V7 is set by a timer or the like, so that the on and off signals PQ1 of the IGBT elements Q1 to Q6 are set. Can produce ~ PQ6.

Next, with reference to FIGS. 12-13, the surge voltage suppression effect by maintaining the output time of a zero voltage vector more than minimum zero voltage vector output time Tz is demonstrated. 12 is a diagram for explaining the relationship between the transition of the voltage vector and the line voltage. It is a figure which shows the line voltage pattern extracted by paying attention to pulse polarity, zero voltage vector output time, and vector output time other than zero voltage.

Here, the transition of the voltage vector in two cycles of the PWM control period T is considered. Because of the symmetry of the vector, when the phase θ is considered only in the range of 0 ≦ θ <π / 3, the transition of the voltage vector is represented by two kinds shown in the following (1) and (2).

(1) V0 → V1 → V2 → V7 → V2 → V1 → V0

(2) V7 → V2 → V1 → V0 → V1 → V2 → V7

And when phase (theta) moves to the range of (pi) / 3 <(theta) <2 (pi) / 3 from the range of 0 <(theta) <(pi) / 3, the following (3) and (4) different from said (1) and (2) The transition of the voltage vector represented by the two types shown in FIG.

(3) V0 → V1 → V2 → V7 → V2 → V3 → V0

(4) V7 → V2 → V1 → V0 → V3 → V2 → V7

FIG. 12 shows the transition of the four types of voltage vectors shown in the above (1) to (4) together with the line voltage waveform. 12, it can be understood that the pulses of the line voltage change to the same polarity with the zero voltage vector interposed therebetween, and to the different polarities with the zero voltage vector interposed therebetween. FIG. 13 shows the pattern of the line voltage extracted by focusing on the polarity of the pulse, the output time of the zero voltage vector, and the output time of voltage vectors other than the zero voltage vector. In Fig. 13, the line voltage pattern 1 and the line voltage varying in the same polarity with the zero voltage vector interposed between the long and short ends of the output time of the zero voltage vector and the output time of the voltage vectors other than the zero voltage vector. Line voltage pattern 2 that is changed to different polarities with a voltage vector in between is shown. All the line voltage changes shown in FIG. 12 are classified into eight types shown in FIG.

14 shows the magnitude of the surge voltage generated in each case of the line voltage change shown in FIG. As is apparent from Fig. 14, for (a-3), (a-4), (b-3) and (b-4) when the zero voltage vector output time is long, twice the DC bus voltage Vdc. Surge voltages in excess of do not occur. On the other hand, for (a-1), (a-2), (b-1), and (b-2) when the zero voltage vector output time is short, the surge exceeds twice the DC bus voltage Vdc. Voltage is occurring. Therefore, it can be seen that, when the output time of the zero voltage vector is appropriately selected, generation of a surge voltage exceeding twice the DC bus voltage Vdc can be suppressed.

As described above, in the first embodiment, when the sum of the two zero voltage vector output time is shorter than the minimum zero voltage vector output time, the relative ratio of the output time of two voltage vectors other than the zero voltage vector is not changed. Instead, the four voltage vector output times are adjusted so that the sum of the two zero voltage vector output times is equal to the minimum zero voltage vector output time.

Therefore, according to the first embodiment, since zero voltage vector output time is always obtained by a predetermined value or more, the resonance phenomenon due to switching of the IGBT element can be attenuated during the zero voltage vector output, which is twice the DC bus voltage Vdc. Surge voltages exceeding can be effectively suppressed.

In addition, since the adjustment of the voltage vector output time is based on the output time of the voltage vector, which is a common parameter of three phases generated based on the three-phase voltage command, the adjustment of the voltage vector output time provides a suppression effect of the surge voltage across all phases. Can be. Further, by devising the voltage vector adjustment, it is possible to minimize the fluctuation of the magnetic flux vector trajectory due to the suppression of the surge voltage.

(Example 2)

15 is a flowchart for explaining the operation of the voltage vector adjusting unit included in the control device of the power converter according to the second embodiment of the present invention. In the control device of the power converter according to the second embodiment, in the configuration shown in the first embodiment (FIG. 4), some functions are added to the voltage vector adjusting unit 12. As shown in FIG. That is, the voltage vector adjusting unit 12 according to the second embodiment adjusts the output time of the voltage vector output by the voltage vector control unit 11 in the order shown in FIG. 15, and adjusts the zero voltage vector output time of a predetermined value or more. Both adjustment operations for securing and zeroing are performed. Hereinafter, an operation of the voltage vector adjusting unit 12 according to the second embodiment will be described with reference to FIG. 15. In addition, in FIG. 15, the same code | symbol is attached | subjected to the process sequence which becomes the same as the process sequence shown in FIG. Here, a description will be given focusing on a part relating to the second embodiment.

15, when the sum t0 + t7 of the output time of the zero voltage vector is shorter than the minimum zero voltage vector output time Tz (step ST11: NO), in the second embodiment, the sum of the output time of the zero voltage vector is further reduced. It is determined whether t0 + t7 is longer than 1/2 of the minimum zero voltage vector output time Tz (step ST20).

When the total t0 + t7 of the output time of the zero voltage vector is longer than 1/2 of the minimum zero voltage vector output time Tz (step ST20: YES), similarly to the first embodiment, the process of step ST13 is executed. If the sum t0 + t7 of the output time of the zero voltage vector is shorter than 1/2 of the minimum zero voltage vector time Tz (step ST20: NO), the output time of the voltage vector is adjusted so that t0 '= t7' = 0. (Step ST21). Also in this case, the adjustment is performed so as not to change the relative ratio of the output time of the voltage vectors V1 and V2 according to the equation (3).

As a result, in step ST14, the output time t0 ', t1', t2 ', t7' of the voltage vectors V0, V1, V2, and V7 adjusted in any one of step ST12, step ST13, and step ST21 is converted into a firing pulse generator ( 13). In addition, the voltage vectors V0, V1, V2, and V7 selected by the voltage vector control unit 11 are used in the same manner as in the first embodiment and output to the firing pulse generator 13.

As described above, according to the second embodiment, when the total t0 + t7 of the output time of the zero voltage vector is shorter than the minimum zero voltage vector output time Tz, the output of the zero voltage vector is bounded by t0 + t7 = Tz / 2. The total value of the time is set to the minimum zero voltage vector output time Tz or zero. Therefore, in the second embodiment, the concept of rounding can be applied, so that the average error of zero voltage vector output time can be reduced even when the voltage vector is adjusted.

Next, with reference to FIGS. 13 and 14 used in Example 1, the surge voltage suppression effect by setting the output time of the zero voltage vector to zero will be described. In FIGS. 13 and 14 (a-1) and (a-2), outputting a short zero voltage vector itself causes a surge voltage exceeding twice the DC bus voltage Vdc. 14 (a-1) and (a-2), when the zero voltage vector disappears, (a-1) and (a-2) become one short pulse and one long pulse, respectively, (a-3 is equivalent to the waveform in the half period of

Therefore, although applicable, it is limited, but it turns out that the output time of a zero voltage vector is zero, and generation | occurrence | production of the surge voltage exceeding 2 times of DC bus voltage Vdc can be suppressed.

As described above, according to the second embodiment, twice the DC bus voltage Vdc by selecting the zero voltage vector output time of a predetermined value or zero or zero voltage vector output time in a rounded manner. Surge voltage exceeding can be suppressed. In addition, since the adjustment of the voltage vector output time is based on the output time of the voltage vector, which is a common parameter of three phases generated based on the three-phase voltage command, the adjustment of the voltage vector output time is suppressed in all phases. You can get it. Further, by devising the voltage vector adjustment, it is possible to minimize the fluctuation of the magnetic flux vector trajectory due to suppression of the surge voltage.

In the above description, the boundary between whether the total t0 + t7 of the zero voltage vector output time is the minimum zero voltage vector output time Tz or zero is Tz / 2, but the boundary is not particularly limited to Tz / 2. It goes without saying that it can be set freely in the range of 0 to Tz. In addition, from the description in the second embodiment, in the first embodiment, it is conceivable that the sum of the output time of the zero voltage vector is rounded up to the minimum zero voltage vector output time Tz with the boundary at zero. Conversely, it is also possible to round down the total value of the output time of the zero voltage vector to zero with the boundary at the minimum zero voltage vector output time Tz.

(Example 3)

Fig. 16 is a block diagram showing the configuration of a control device of a power converter according to the third embodiment of the present invention. In the third embodiment, the components are the same as those in the first embodiment, but a configuration example in the case of controlling two control cycles, for example, of one PWM control cycle as one unit is shown. Incidentally, the way of thinking of the control phase θ in each period is the same as that of the first embodiment, and the range of 0 ≦ θ <π / 3 is considered here.

In Fig. 16, the voltage vector control unit 21 selects the voltage vector outputted by the power converter in two control cycles of PWM control from the voltage command values Vu, Vv, and Vw of each phase of the power converter by the method described in the first embodiment. (In the example shown, (V0_1, V1_1, V2_1, V7_1) (V0_2, V1_2, V2_2, V7_2)) and its output time t0_1, t1_1, t2_1, t7_1 (t0_2, t1_2, t2_2, t7_2) are calculated.

The voltage vector adjusting unit 22 uses the method described later (FIG. 17) to input the voltage vector input from the voltage vector control unit 21 ((V0_1, V1_1, V2_1, V7_1) (V0_2, V1_2, V2_2, V7_2 in the illustrated example)). Is output as it is, and the output time t0_1, t1_1, t2_1, t7_1 (t0_2, t1_2, t2_2, t7_2) of the voltage vector is adjusted and output so that the zero voltage vector output time is equal to or greater than a predetermined value (t0_1 ' , t1_1 ', t2_1', t7_1 ') (t0_2', t1_2 ', t2_2', t7_2 ').

The firing pulse generator 23 uses the method described in Embodiment 1 to configure the power converter based on the voltage vector input from the voltage vector adjuster 22 and the output time of the voltage vector adjusted by the voltage vector adjuster 22. The on and off signals "PQ1, PQ2, PQ3, PQ4, PQ5, PQ6 and PQ7" of each semiconductor switch element are generated.

The voltage vector control unit 21 and the firing pulse generator 23 extend the voltage vector control unit 11 and the firing pulse generator 13 in the first embodiment (FIG. 4) to two cycles of the PWM control cycle. Since only a detailed description is omitted. Here, with reference to FIG. 17, operation | movement of the voltage vector adjustment part 22 is demonstrated. 17 is a flowchart for explaining the operation of the voltage vector adjusting unit 22 shown in FIG.

In FIG. 17, if the control phase θ is in the range of 0 ≦ θ <π / 3, the voltage vector adjusting unit 22 outputs the time t0_1, t1_1, t2_1, t7_1 of the voltage vector output from the voltage vector control unit 21. (t0_2, t1_2, t2_2, t7_2) is read (step ST31), and one or both of the sum (t0_1 + t7_1) (t0_2 + t7_2) of the output time of the zero voltage vector in each period is the minimum zero voltage vector output. It is determined whether it is longer than the time Tz (step ST32).

As a result, when the sum of the output times t0_1 + t7_1 (t0_2 + t7_2) of the zero voltage vector in each period is longer than the minimum zero voltage vector output time Tz (step ST32: YES), the read output time t1_1 The output time t1_1 ', t2_1', t0_1 ', t7_1', t1_2 ', t2_2', t0_2 ', t7_2' which adjusted t2_1, t0_1, t7_1, t1_2, t2_2, t0_2, and t7_2 as it is (step ST33).

On the other hand, when one or both of the sum (t0_1 + t7_1) (t0_2 + t7_2) of the output time of the zero voltage vector in each period is shorter than the minimum zero voltage vector output time Tz (step ST32: NO) It is determined whether the sum (t0_1 + t7_1 + t0_2 + t7_2) of the output time of the over zero voltage vector is longer than the minimum zero voltage vector output time Tz (step ST34).

As a result, when the sum (t0_1 + t7_1 + t0_2 + t7_2) of the output time of the zero voltage vector over the two periods is longer than the minimum zero voltage vector output time Tz (step ST34: YES), in step ST35, The output time of the zero voltage vector existing in the middle is zero (t7_1 '= t7_2' = 0), and the amount is divided by the output time of the zero voltage vector existing at both ends of the two cycles (t0_1 '= t0_2' = (t0_1 + t7_1 + t0_2 + t7_2) / 2). In addition, the output time of non-zero voltage vectors other than a zero voltage vector is made into the output time of the non-zero voltage vector adjusted as it is (t1_1 '= t1_1, t2_1' = t2_1, t1_2 '= t1_2, t2_2' = t2_2).

On the other hand, when the sum (t0_1 + t7_1 + t0_2 + t7_2) of the output time of the zero voltage vector over two cycles is shorter than the minimum zero voltage vector output time Tz (step ST34: NO), in step ST36, the middle of the two cycles is performed. The output time of the zero voltage vector present at 0 is zero (t7_1 '= t7_2' = 0), and the output times t0_1 'and t0_2' of the zero voltage vector present at both ends of the two cycles are the minimum zero voltage vector output time Tz. Adjust the output time of the voltage vector to be half (t0_1 '= t0_2' = Tz / 2).

At this time, the relative ratios of the output times of the voltage vectors V1_1, V2_1, V1_2, and V2_2 are adjusted so as not to change according to the equation (3). That is, t1_1 '= (T-Tz / 2) {t1_1 / (t1_1 + t2_1)}, t2_1' = (T-Tz / 2) {t2_1 / (t1_1 + t2_1)}, t1_2 '= (T-Tz / 2) {t1_2 / (t1_2 + t2_2)} and t2_2 '= (T-Tz / 2) {t2_2 / (t1_2 + t2_2)}.

Then, the output time t0_1 ', t1_1', t1_1 ', t2_1', t7_1 for the voltage vectors V0_1, V1_1, V2_1, V7_1, V0_2, V1_2, V2_2, and V7_2 for two cycles adjusted in any one of steps ST33, ST35, and ST36. ', t0_2', t1_2 ', t2_2' and t7_2 'are output to the firing pulse generator 23 (step ST37). In addition, the voltage vectors V0_1, V1_1, V2_1, V7_1, V0_2, V1_2, V2_2, and V7_2 for the two cycles selected by the voltage vector control unit 21 are used as they are and output to the firing pulse generator 23.

As described above, according to the third embodiment, since the voltage vector is adjusted as one unit of two cycles of the PWM control cycle, the remaining zero voltage is zero by setting the output time of the zero voltage vector existing at the end of each cycle to zero. The output time of the vector can be doubled. As a result, in one cycle of the PWM control cycle, it is necessary to change the sum of the output time of the non-zero voltage vector until the sum of the output time of the zero voltage vector is less than 1/2 of the minimum zero voltage vector output time Tz. Since there is no error, the error can be made small. According to this method, since the output time of the zero voltage vector is secured more than a certain value of the minimum zero voltage vector output time or zero, suppression of the surge voltage exceeding twice the DC bus voltage Vdc is suppressed. You can run

Since the adjustment of the voltage vector output time is based on the output time of the voltage vector, which is a common parameter of three phases generated based on the three-phase voltage command, the adjustment of the voltage vector output time provides a suppression effect of the surge voltage across all phases. Can be. Further, by devising the voltage vector adjustment, it is possible to minimize the fluctuation of the magnetic flux vector trajectory due to the suppression of the surge voltage.

In addition, in Example 3, although the case where the output time of a voltage vector was adjusted for two periods of a PWM control period was demonstrated in order to make understanding easy, the target period is not specifically limited to two periods, It goes without saying that it can be freely set in the range of two or more cycles.

Example 4

Fig. 18 is a flowchart for explaining the operation of the voltage vector adjusting unit included in the control device of the power converter according to the fourth embodiment of the present invention. In the control device of the power converter according to the fourth embodiment, in the configuration shown in the third embodiment (Fig. 16), some functions are added to the voltage vector adjusting unit 22. That is, the voltage vector adjusting unit 22 according to the fourth embodiment adjusts the output time of the voltage vector output by the voltage vector control unit 21 in two control cycles of PWM control according to the procedure shown in FIG. In this case, an adjustment operation such as adding output times of the same voltage vector is performed within two cycles. Hereinafter, the operation of the voltage vector adjuster 22 according to the fourth embodiment will be described with reference to FIG. 18. In addition, in FIG. 18, the same code | symbol is attached | subjected to the process sequence which becomes the same as the process sequence shown in FIG. Here, a description will be given focusing on a part relating to the fourth embodiment.

In Fig. 18, in the determination processing at step ST34, when the sum (t0_1 + t7_1 + t0_2 + t7_2) of the output time of the zero voltage vector over two cycles is longer than the minimum zero voltage vector output time Tz (step ST34: Example) In step ST41, the times for outputting the same voltage vector in two cycles are added together. That is, t1_1 '= t1_1 + t1_2, t2_1' = t2_1 + t2_2, t0_1 '= t7_1' = (t0_1 + t7_1 + t0_2 + t7_2) / 2. In addition, the output time of each voltage vector in the 2nd cycle is made into zero. That is, t1_2 '= t2_2' = t0_2 '= t7_2' = 0 is adjusted.

On the other hand, when the sum (t0_1 + t7_1 + t0_2 + t7_2) of the output time of the zero voltage vector over two cycles is shorter than the minimum zero voltage vector output time Tz (step ST34: NO), in step ST42, in two cycles, The time for outputting the same voltage vector is summed into one, and the voltages are made such that the output time t0_1 ', t7_1' of the zero voltage vector after the sum becomes half of the minimum zero voltage vector output time Tz (t0_1 '= t7_1' = Tz / 2). Adjust the output time of the vector.

At this time, the relative ratios of the output times of the voltage vectors V1_1, V2_1, V1_2, and V2_2 are not changed according to Equation (3). That is, t1_1 '= (2T- Tz) {(t1_1 + t1_2) / (t1_1 + t2_1 + t1_2 + t2_2)}, t2_1' = (2T-Tz) {(t2_1 + t2_2) / (t1_1 + t2_1 + t1_2 + t2_2)}. In addition, the output time of each voltage vector in the 2nd cycle is made into zero. That is, t1_2 '= t2_2' = t0_2 '= t7_2' = 0 is adjusted.

Then, the output time t0_1 ', t1_1', t1_1 ', t2_1', t7_1 for the voltage vectors V0_1, V1_1, V2_1, V7_1, V0_2, V1_2, V2_2, and V7_2 for two cycles adjusted in any one of steps ST33, ST41, and ST42. ', t0_2', t1_2 ', t2_2' and t7_2 'are output to the firing pulse generator 23 (step ST37). In addition, the voltage vectors V0_1, V1_1, V2_1, V7_1, V0_2, V1_2, V2_2, and V7_2 for the two cycles selected by the voltage vector control unit 21 are used as they are and output to the firing pulse generator 23.

As described above, according to the fourth embodiment, when adjusting the voltage vector using two cycles of the PWM control cycle as one unit, the time for outputting the same voltage vector in two cycles is summed into one to include the zero voltage vector. The output time of each voltage vector can be doubled. As a result, in one cycle of the PWM control cycle, it is necessary to change the sum of the output time of the non-zero voltage vector until the sum of the output time of the zero voltage vector is less than 1/2 of the minimum zero voltage vector output time Tz. Since there is no error, the error can be made small. According to this method, since the minimum zero voltage vector time is always ensured, it is possible to suppress surge voltages exceeding twice the DC bus voltage Vdc.

Since the adjustment of the voltage vector output time is based on the output time of the voltage vector, which is a common parameter of three phases generated based on the three-phase voltage command, the adjustment of the voltage vector output time has a suppression effect of the surge voltage across all phases. You can get it. Further, by devising the voltage vector adjustment, it is possible to minimize the fluctuation of the magnetic flux vector trajectory due to the suppression of the surge voltage.

In addition, in Example 4, the case where the output time of the voltage vector was adjusted for two cycles of the PWM control cycle for the sake of easy understanding was explained, but as in the third embodiment, the target cycle is particularly two cycles. It is needless to say that the present invention is not limited to this and can be freely set within a range of two or more cycles.

(Example 5)

19 is a block diagram showing a configuration of a control device of a power converter according to a fifth embodiment of the present invention. In addition, in FIG. 19, the same code | symbol is attached | subjected to the component same as or equivalent to the structure shown in FIG. Here, a description will be given focusing on a part relating to the fifth embodiment.

As shown in FIG. 19, in the 5th Embodiment, in the structure shown in FIG. 4, the voltage vector adjustment part 31 is provided instead of the voltage vector adjustment part 12, and the delay part 32 is added.

The delay unit 32 is configured to apply the voltage vector adjustment unit 31 with a delay of one voltage vector and its output time which are adjusted and output by the voltage vector adjustment unit 31. In the illustrated example, the delay unit 32 applies the voltage vectors V0_p, V1_p, V2_p, V7_p with one cycle delay and the output time t0_p, t1_p, t2_p, t7_p with one cycle delay to the voltage vector adjusting unit 31.

As described in the first embodiment, the voltage vector adjusting unit 31 adjusts and outputs the output time of the voltage vector output by the voltage vector control unit 11 so that the zero voltage vector output time is equal to or higher than a predetermined value. The adjustment time before one cycle of the PWM control cycle obtained through the delay unit 32 is also adjusted.

Next, with reference to FIG. 20, the operation | movement of the voltage vector adjustment part 31 with which the control apparatus of the power converter of 5th Embodiment is provided is demonstrated. 20 is a flowchart for explaining the operation of the voltage vector adjusting unit 31 shown in FIG. In FIG. 20, the same code | symbol is attached | subjected to the process sequence same or equivalent to the process sequence shown in FIG.

In FIG. 20, the voltage vector adjusting unit 31 is configured to output the output time t1, t2, t0, t7 of the voltage vector input from the voltage vector control unit 11, and one cycle before the PWM control period input from the delay unit 32. The voltage vector V1_p, V2_p, V0_p, V7_p, which is the adjustment output, and its output time t1_p, t2_p, t0_p, t7_p are read (step ST51), and the output time of the zero voltage vector may be zero. It is determined whether or not the vector output at the end of one period before the period is a zero voltage vector (step ST52).

As a result, if the last vector output last time is a zero voltage vector (step ST52: YES), this time branches to the sequence starting from the zero voltage vector, and the total t0 + t7 of the output time of the zero voltage vector is the minimum zero voltage. A determination is made as to whether it is longer than the vector output time Tz (step ST11).

When the total t0 + t7 of the output time of the zero voltage vector is longer than the minimum zero voltage vector output time Tz (step ST11: YES), the output time t1 in which the output time t1, t2, t0, t7 is adjusted as it is. It is assumed that ', t2', t0 'and t7' (step ST12).

On the other hand, in step ST11, when the sum t0 + t7 of the output time of the zero voltage vector is shorter than the minimum zero voltage vector output time Tz (step ST11: No), the sum t0 + t7 of the output time of the zero voltage vector is the minimum zero. It is determined whether it is longer than 1/2 of the voltage vector output time Tz (step ST53). As a result, when the total t0 + t7 of the output time of the zero voltage vector is longer than 1/2 of the minimum zero voltage vector output time Tz (step ST53: YES), the output time of the zero voltage vector V0 output at the beginning of the period t0 'is adjusted to the sum t0 + t7 of the output time of the zero voltage vector (t0' = t0 + t7), and the output time of the zero voltage vector V7 output at the end of the period is zero (t7 '= 0). The output time t1, t2 of the non-zero voltage vector is set as the output time t1 ', t2' adjusted as it is (step ST54).

Further, in step ST53, when the total t0 + t7 of the output time of the zero voltage vector is shorter than 1/2 of the minimum zero voltage vector output time Tz (step ST53: NO), in step ST55, the output is performed at the beginning of the period. The output time of the zero voltage vector V0 is adjusted to 1/2 of the minimum zero voltage vector output time Tz, and the output time of the zero voltage vector V7 output at the end of the period is zero (t7 '= 0). Further, the output times t1 and t2 of the non-zero voltage vectors V1 and V2 are adjusted so as not to change the relative ratios of the output times of the voltage vectors V1 and V2 according to equation (3). That is, t1 '= (T-Tz / 2) {t1 / (t1 + t2)} and t2' = (T-Tz / 2) {t2 / (t1 + t2)} are adjusted.

If the last vector outputted last time is not a zero vector (step ST52: NO), this time branches to a sequence starting from a non-zero voltage vector, and in step ST56, the sum of the output time of the zero voltage vector t0 + t7. If the minimum zero voltage vector output time Tz is longer than 1/2 (step ST56: YES), the output time of the zero voltage vector V0 output at the beginning of the cycle is zero (t0 '= 0), and the end of the cycle is zero. The output time of the zero voltage vector V7 outputted to is adjusted to t0 + t7 of the total output time of the zero voltage vector (t7 '= t0 + t7). The output time of the non-zero voltage vectors V1 and V2 is set to the output times t1 'and t2' in which the output times t1 and t2 are adjusted as they are (step ST57).

Then, in step ST56, when the total t0 + t7 of the output time of the zero voltage vector is shorter than 1/2 of the minimum zero voltage vector output time Tz (step ST56: NO), in step ST58, the output is performed at the beginning of the period. The output time of the zero voltage vector V0 is zero (t0 '= O), and the output time of the zero voltage vector V7 output at the end of the period is adjusted to 1/2 of the minimum zero voltage vector output time Tz (t7' = Tz / 2). At this time, the output time of the non-zero voltage vectors V1 and V2 is adjusted so as not to change the relative ratio of the output time of the voltage vectors V1 and V2 according to equation (3). That is, t1 '= (T-Tz / 2) {t1 / (t1 + t2)} and t2' = (T-Tz / 2) {t2 / (t1 + t2)} are adjusted.

The output pulses t0 ', t1', t2 ', and t7' of the voltage vectors V0, V1, V2, and V7 adjusted in any one of steps ST12, ST54, ST55, step ST57, and step ST58 are firing pulse generators. Output to 13 (step ST14). The voltage vectors V0, V1, V2, and V7 selected by the voltage vector control unit 11 are used as they are and output to the firing pulse generator 13.

As described above, according to the fifth embodiment, the output time of the zero voltage vector can be doubled by adjusting the output time of the voltage vector to combine the zero voltage vectors existing at the beginning and the end of the PWM control period into one. . As a result, it is not necessary to change the sum of the output time of the non-zero voltage vector until the sum of the output time of the zero voltage vector is less than 1/2 of the minimum zero voltage vector output time Tz, so that the error can be made small. have. According to this method, since the output time of the zero voltage vector is secured more than a fixed value of the minimum zero voltage vector time or zero, suppression of the surge voltage exceeding twice the DC bus voltage Vdc is performed. Can be.

Since the adjustment of the voltage vector output time is based on the output time of the voltage vector, which is a common parameter of three phases generated based on the three-phase voltage command, the adjustment of the voltage vector output time has a suppression effect of the surge voltage across all phases. You can get it. Further, by devising the voltage vector adjustment, it is possible to minimize the fluctuation of the magnetic flux vector trajectory due to the suppression of the surge voltage.

(Example 6)

21 is a flowchart for explaining the operation of the voltage vector adjusting unit included in the control device of the power converter according to the sixth embodiment of the present invention. In the control apparatus of the power converter according to the sixth embodiment, in the configuration shown in the fifth embodiment (Fig. 19), some functions are added to the voltage vector adjusting unit 31. That is, the voltage vector adjusting unit 31 according to the sixth embodiment outputs the zero voltage vector to be output at the beginning of this PWM control cycle by using the output time of the zero voltage vector output at the end of the previous PWM control cycle. An adjustment operation for determining the time is performed. Hereinafter, the operation of the voltage vector adjusting unit 31 according to the sixth embodiment will be described with reference to FIG. 21. In addition, in FIG. 21, the same code | symbol is attached | subjected to the process sequence which becomes the same as the process sequence shown in FIG. Here, a description will be given focusing on a part relating to the sixth embodiment.

In FIG. 21, the voltage vector adjusting unit 31 is configured to output the output time t1, t2, t0, t7 of the voltage vector input from the voltage vector control unit 11 and one cycle before the PWM control period input from the delay unit 32. When the voltage vectors V1_p, V2_p, V0_p, and V7_p that are the adjustment outputs and their output times t1_p, t2_p, t0_p, and t7_p are read (step ST51), the zero voltage outputted at the end of the previous time (before one cycle of the PWM control cycle) is read. It is determined whether the total time between the output time t0_p of the vector and the output time t0 of the zero voltage vector to be output at this time is longer than the minimum zero voltage vector output time Tz (step ST61).

As a result, when the total t0_p + t0 of the output time of the zero voltage vector is longer than the minimum zero voltage vector output time Tz (step ST61: YES), the output time of adjusting this output time t1, t2, t0, t7 as it is. t1 ', t2', t0 ', t7' (step ST12). On the other hand, when the sum t0_p + t0 of the output time of the zero voltage vector is shorter than the minimum zero voltage vector output time Tz (step ST61: NO), the sum t0_p + t0 + t7 of the output time of the zero voltage vector is the minimum zero voltage. It is determined whether it is longer than the vector output time Tz (step ST62).

When the total t0_p + t0 + t7 of the output time of the zero voltage vector is longer than the minimum zero voltage vector output time Tz (step ST62: YES), the output time t0 'of the zero voltage vector V0 output at the beginning of the period is determined. Adjust the sum t0_p + t0 of the output time of the zero voltage vector to be equal to the minimum zero voltage vector output time Tz (t0 '= Tz-t0_p), and adjust the output time t7' of the zero voltage vector V7 output at the end of the period. Adjust the remaining time t0 + t7-t0 '(t7' = t0 + t7-t0 '). The output times t1 and t2 of the non-zero voltage vector are taken as adjusted output times t1 'and t2' as they are (step ST63).

On the other hand, when the sum t0_p + t0 + t7 of the output time of the zero voltage vector is shorter than the minimum zero voltage vector output time Tz (step ST62: No), the output time t0 'of the zero voltage vector V0 output at the beginning of the period is Adjust the sum t0_p + t0 of the output time of the zero voltage vector to be equal to the minimum zero voltage vector output time Tz (t0 '= Tz-t0_p), and zero the output time of the zero voltage vector V7 output at the end of the period. (T7 '= 0). In addition, the output time t1, t2 of a nonzero voltage vector is adjusted so that the relative ratio of the output time of the voltage vectors V1, V2 may not be changed according to Formula (3). That is, t1 '= (T-Tz + t0_p) {t1 / (t1 + t2)} and t2' = (T-Tz + t0_p) {t2 / (t1 + t2)} are adjusted (step ST64).

The output time t0 ', t1', t2 ', and t7' of the voltage vectors V0, V1, V2, and V7 adjusted in any one of step ST12, step ST63, and step ST64 are output to the firing pulse generator 13. (Step ST14). The voltage vectors V0, V1, V2, and V7 selected by the voltage vector control unit 11 are used as they are and output to the firing pulse generator 13.

As described above, according to the sixth embodiment, since the output time of the zero voltage vector output at the beginning of this PWM control cycle is determined using the output time of the zero voltage vector output at the end of the previous PWM control cycle, Even when the zero voltage vector spans the PWM control period, the minimum zero voltage vector time can be assuredly ensured. For this reason, suppression of the surge voltage more than twice the DC bus voltage Vdc can be reliably performed.

Since the adjustment of the voltage vector output time is based on the output time of the voltage vector, which is a common parameter of three phases generated based on the three-phase voltage command, the adjustment of the voltage vector output time has a suppression effect of the surge voltage across all phases. You can get it. Further, by devising the voltage vector adjustment, it is possible to minimize the fluctuation of the magnetic flux vector trajectory due to the suppression of the surge voltage.

(Example 7)

Fig. 22 is a block diagram showing the construction of a control device of a power converter according to the seventh embodiment of the present invention. In addition, in FIG. 22, the same code | symbol is attached | subjected to the component same as or equivalent to the structure shown in FIG. Here, a description will be given focusing on a part relating to the seventh embodiment.

As shown in FIG. 22, in the 7th Embodiment, in the structure shown in FIG. 4, the voltage vector adjustment part 41 is provided instead of the voltage vector adjustment part 12, and the delay part 42 is added.

As described in the first embodiment, the voltage vector adjusting unit 41 adjusts and outputs the output time of the voltage vector output by the voltage vector control unit 11 so that the zero voltage vector output time is equal to or greater than a predetermined value. In Fig. 7, the function has a function of outputting the error Err according to the adjustment, and the error Err_p before one cycle of the PWM control cycle input through the delay unit 42 is used for voltage vector adjustment after one cycle.

Next, with reference to FIGS. 22-24, operation | movement of the voltage vector adjustment part 41 in the control apparatus of the power converter which concerns on 7th Embodiment is demonstrated. 23 is a flowchart for explaining the operation of the voltage vector adjusting unit 41 shown in FIG. It is a figure explaining the operation | movement of the error calculation which the voltage vector adjustment part shown in FIG. 22 performs.

First, in FIG. 23, the voltage vector adjusting unit 41 calculates the previous time (before one cycle of the PWM control period) together with the output time t1, t2, t0, t7 of the voltage vector output by the voltage vector control unit 11. One error Err_p is read (step ST71), and the output time t1, t2, t0, t7 of the voltage vector is corrected to correct the previous error Err_p (step ST72).

That is, in step ST72, the output time t1 is corrected to t1 (1 + Err_p). Correct the output time t2 to t2 (1 + Err_p). After that, using the new output time t1, t2, the output time t0, t7 is corrected to (T-t1-t2) / 2. Next, in the order described in the second embodiment (Fig. 15), the minimum zero voltage vector output time Tz is secured or the zero voltage vector output time is deleted (steps ST11 to ST21).

Next, the error Err between the obtained output time t1 'and t2' of the adjusted voltage vectors V1 and V2 and the output time t1 and t2 of the voltage vectors V1 and V2 modified in step ST72 described above is calculated. That is, the operation of Err = (t1 + t2-t1'-t2 ') / (t1 + t2) is executed (step ST73). Then, the output time t1 ', t2', t0 ', t7' and the error Err of the obtained adjusted voltage vectors V1, V2, V0 and V7 are output (step ST74). The same applies to the point that the voltage vectors V0, V1, V2, and V7 selected by the voltage vector control unit 11 are used as they are and output to the firing pulse generator 13.

Next, with reference to FIG. 24, the calculation method of the error Err is demonstrated. In Fig. 24A, the traces A and B of the magnetic flux vector for two cycles of the PWM control period before the adjustment of the voltage vector are displayed. Trace A is the previous period, and trace B is this period. In Fig. 24B, the traces A 'and B' of the magnetic flux vectors after the adjustment of the voltage vectors are shown. As the trajectory A of the previous magnetic flux vector secures the minimum zero voltage vector output time, the trajectory A 'becomes the trajectory A' and the trajectory is shortened. It is FIG.24 (c) which overlaps and shows FIG.24 (a) and (b).

Here, in this PWM control cycle, by plotting the locus represented by the locus B ', it is considered that the end point of the magnetic flux vector locus before and after adjustment is coincident. As described in Embodiment 1 (Fig. 10), when the adjustment of the voltage vector is performed in accordance with equation (3) so as not to change the relative ratio of the output time of the voltage vectors other than the zero voltage vector, the triangle of the trace A and the trace A 'Triangles are similar to each other. Similarly, the triangle of trace B and the triangle of trace B 'are similar.

If the angle Δθa and the angle Δθb are sufficiently small, the arc can be seen as a straight line. Therefore, the difference between the trajectories A and B and the trajectories A 'and B' is only that the division ratio when dividing the straight line that is the arc is different. I can think of it. Since the division ratio between the trajectory A and the trajectory B before the adjustment is 1: 1, the ratio between the trajectory A and the trajectory A 'can be known when the shortened portion of the trajectory A' is added to the trajectory B 'to equalize the sum value. It is good if there is. Therefore, the error Err obtained by either of the following formulas (7) to (9) is used.

When this error Err is introduced, the previous error Err_p is used to multiply the output time t1 and t2 of the voltage vector by (1 + Err_p), thereby eliminating the influence of the previous adjustment, and thus desiring the end point of the current magnetic flux vector trajectory. Can be matched to a point.

As described above, according to the seventh embodiment, since the adjustment error can be corrected when providing a zero voltage vector output time equal to or greater than a predetermined value or adjusting the zero voltage vector output time to zero, the DC bus voltage It is possible to surely suppress the surge voltage exceeding twice of Vdc, and to suppress the fluctuation of the magnetic flux vector trajectory due to the suppression of the surge voltage to a minimum. In addition, since the adjustment of the voltage vector output time is based on the output time of the voltage vector, which is a common parameter of three phases generated based on the three-phase voltage command, the suppression effect of the surge voltage is applied to all phases in one adjustment. Can be obtained.

(Example 8)

25 is a flowchart for explaining the operation of the voltage vector adjusting unit included in the control device of the power converter according to the eighth embodiment of the present invention. In addition, in FIG. 25, the same code | symbol is attached | subjected to the order same or equivalent to the process sequence shown in FIG. 9 (Example 1). Here, a description will be given focusing on a part relating to the eighth embodiment.

In the eighth embodiment, in the control device of the power converter shown in the first embodiment (Fig. 4), the case where the output time of the zero voltage vector described in the second embodiment (Fig. 15) is adjusted to zero is not considered as an exception. An example of countermeasures against the matter (defective point) is shown (steps ST81 to ST85).

That is, referring to Fig. 12A, when the zero voltage vector V7 is removed, there is no problem with the line voltages Vvw and Vwu, but the line voltage Vuv has two pulses of the voltage vector V1 with the voltage vector V2 interposed therebetween. It is in a form to say. This is the case of Fig. 14A-2 when the voltage vector V2 is replaced with a zero voltage vector. That is, in the case where the output time of the zero voltage vector is adjusted to zero, there may be a generation of a surge voltage depending on the output time of the non-zero voltage vector. In the eighth embodiment, in such a case, the concept of securing the minimum zero voltage vector output time is applied. A description with reference to FIG. 25 is as follows.

In Fig. 25, when the output time of the zero voltage vector is adjusted to zero (step ST21), it is determined whether the adjusted output time t1 'of the voltage vector V1 is shorter than 1/2 of the minimum zero voltage vector output time Tz. (Step ST81). As a result, when the output time t1 'in which the voltage vector V1 is adjusted is shorter than 1/2 of the minimum zero voltage vector output time Tz (step ST81: YES), the output time t1' is readjusted so that t1 '= Tz / 2. do. The adjusted output time t2 'of the voltage vector V2 is readjusted to t2' = T-Tz / 2 (step ST82).

On the other hand, when the adjusted output time t1 'of the voltage vector V1 is longer than 1/2 of the minimum zero voltage vector output time Tz (step ST81: NO), the adjusted output time t2' of the voltage vector V2 is the minimum zero voltage vector. It is determined whether it is shorter than 1/2 of the output time Tz (step ST83).

As a result, when t2 'of the adjusted output time of the voltage vector V2 is shorter than 1/2 of the minimum zero voltage vector output time Tz (step ST83: YES), t2' of the adjusted output time is t2 '= Tz / Readjust to 2 At this time, the adjusted output time t1 'of the voltage vector V1 is readjusted to t1' = T-Tz / 2 (step ST84).

When the adjusted output time t2 'of the voltage vector V2 is longer than 1/2 of the minimum zero voltage vector output time Tz (step ST83: NO), the output time t1', t2 ', adjusted in steps ST11 to ST21, The readjustment of t0 'and t7' is not performed (step ST85).

In addition, in the above description, when the output time of voltage vectors other than a zero voltage vector is less than 1/2 of the minimum zero voltage vector output time Tz, it rounds up to Tz / 2, However, as demonstrated in Example 2, it rounds up You may also descend.

As described above, according to the eighth embodiment, it is possible to limit the surge voltages related to the voltage vector output time other than the zero voltage vector that may occur when the output time of the zero voltage vector is adjusted to zero, so that the DC bus voltage is assured. Surge voltages in excess of twice Vdc can be suppressed. In addition, suppression of the surge voltage can obtain the effect over all the phases only by adjusting the voltage vector output time which is a common parameter of three phases. Alternatively, by devising a voltage vector adjustment, it is possible to minimize fluctuations in the magnetic flux vector trajectory due to suppression of the surge voltage.

(Example 9)

Fig. 26 is a flowchart for explaining the operation of the voltage vector adjusting unit included in the control device of the power converter according to the ninth embodiment of the present invention. In addition, in FIG. 26, the same code | symbol is attached | subjected to the order same or equivalent to the process sequence shown in FIG. 20 (Example 5). Here, a description will be given focusing on a part relating to the ninth embodiment.

In the ninth embodiment, in the control device of the power converter shown in the fifth embodiment (Fig. 19), matters not considered as an exception when the output time of the zero voltage vector described in Fig. 20 is adjusted to zero (defective point) A countermeasure example is shown (steps ST90 to ST93).

That is, when the surge voltage generation pattern becomes (a-1) and (a-2) of FIG. 14, even when the zero voltage vector is removed, the surge voltage of the voltage between the motor ends is not suppressed. Therefore, focusing on (c) and (d) of FIG. 12, the phenomenon of (b-1) and (b-2) of FIG. 14 occurs in (d) of FIG. 12, but in (c) of FIG. It can be seen that it does not occur. The transition of the voltage vector when the phase θ shifts from a range of 0 ≦ θ <π / 3 to a range of pi / 3 ≦ θ <2π / 3 is described again below.

(3) V0 → V1 → V2 → V7 → V2 → V3 → V0

(4) V7 → V2 → V1 → V0 → V3 → V2 → V7

Here, when zero voltage vector is removed, it becomes as follows.

(3) 'V0 → V1 → V2 → (V7) → V2 → V3 → V0

(4) 'V7 → V2 → V1 → (V0) → V3 → V2 → V7

From the comparison between (3) 'and (4)', if the voltage vector before and after the zero voltage vector is removed is the same, the phenomenon of FIGS. 14B and 14B is eliminated and the surge voltage is reduced. It can be seen that it can be suppressed.

By the way, in FIG. 26, in step ST90 which replaced the first step ST51 shown in FIG. 20, the voltage vectors V1, V2, V0, V7 input from the voltage vector control part 11, and the output time t1, t2, t0, t7, voltage vectors V1_p, V2_p, V0_p, V7_p, which are adjustment outputs before one cycle of the PWM control cycle input from the delay unit 32, and their output times t1_p, t2_p, t0_p, t7_p are read. When the output time of the zero voltage vector is adjusted to zero in step ST57 or step ST58, it is determined whether or not the voltage vector outputted last last time is the same as the voltage vector outputted first time (step ST91). .

As a result, if the voltage vector outputted last last time is the same as the voltage vector outputted first this time (step ST91: YES), since it is the case of (3) 'above, the process goes to step ST93 without doing anything. On the other hand, if the voltage vector output at the last last time is different from the voltage vector output at the first time (step ST91: No), it is the case of (4) ', so that the voltage vector output at the first time is transferred. Change to the last output voltage vector (step ST92) and proceed to step ST93. In step ST93, the output times t1 ', t2', t0 ', t7' and the voltage vectors V1 ', V2', V0 'and V7' of the adjusted voltage vector are output. When the process proceeds from step ST12, ST54, ST55 to step ST93, the voltage vectors V0, V1, V2, and V7 selected by the voltage vector control unit 11 are the voltage vectors V0 ', V1', V2 ', and V7' as they are. As output to the firing pulse generator 13. As shown in FIG.

As described above, according to the ninth embodiment, the cases of Figs. 14B and 14B, which occur when the output time of the zero voltage vector is adjusted to zero, can be avoided, so that the DC bus voltage is assured. Surge voltages in excess of twice Vdc can be suppressed. In addition, in suppressing a surge voltage, the suppression effect of a surge voltage can be acquired over all the phases only by adjusting the output time of the voltage vector which is a parameter common to three phases.

Here, although the description of Examples 1-9 has demonstrated the individual method of suppressing generation | occurrence | production of the surge voltage exceeding twice the DC bus voltage Vdc, it is also possible to use combining two or more of Examples 1-9. It is possible. Although the description of the configuration in that case is omitted, even in combination, a surge voltage exceeding twice the DC bus voltage Vdc is obtained by securing or setting the output time of the zero voltage vector to a constant value or zero at least. It can be suppressed. In addition, since the adjustment of the voltage vector output time is based on the output time of the voltage vector, which is a common parameter of three phases generated based on the three-phase voltage command, the adjustment of the voltage vector output time provides a suppression effect of the surge voltage across all phases. Can be. Further, by devising the voltage vector adjustment, it is possible to minimize the fluctuation of the magnetic flux vector trajectory due to the suppression of the surge voltage.

In addition, in description of Examples 1-9, adjustment is made so that the relative ratio of the output time of voltage vectors other than a zero voltage vector may be changed in order to suppress the fluctuation | variation of the magnetic flux vector trace accompanying suppression of surge voltage to the minimum. If only the suppression of the surge voltage is the purpose, the relative ratio may be changed. This is apparent from the description of Example 1 regarding the suppression of the surge voltage.

Also in this case, the surge voltage exceeding twice the DC bus voltage Vdc can be suppressed by securing the output time of a zero voltage vector more than a fixed value or making it zero. In addition, since the adjustment of the voltage vector output time is based on the output time of the voltage vector, which is a common parameter of three phases generated based on the three-phase voltage command, the adjustment of the voltage vector output time provides a suppression effect of the surge voltage across all phases. Can be.

The present invention is preferable as a control device of a power converter in the case where the connection cable between the power converter and the load is long.

Claims (18)

A control apparatus of a power converter in which an output voltage is controlled by pulse width modulation control, Voltage vector control means for determining a voltage vector output by the power converter within one control period of the pulse width modulation control and a time for outputting the voltage vector based on a voltage command value to the power converter; Voltage vector adjusting means for adjusting an output time of a voltage vector input from said voltage vector control means, said voltage vector adjusting means for adjusting an output time of each voltage vector such that an output time of a zero voltage vector becomes zero or a predetermined value or more; , A firing pulse generating means for generating a signal for turning on and off a semiconductor switch element constituting the power converter based on the output time of the voltage vector adjusted by the voltage vector adjusting means. Control device for a power converter, characterized in that provided. The method of claim 1, And the voltage vector adjusting means adjusts the zero voltage vector output time to a predetermined value or more. The method of claim 1, If the output time of the zero voltage vector is longer than the predetermined value, the voltage vector adjusting means adjusts to ensure the output time of the zero voltage vector to a predetermined value or more, and if it is short, adjusts the output time of the zero voltage vector to zero. To do Control device of a power converter, characterized in that. The method of claim 1, When the voltage vector adjusting means inputs, as a unit, a voltage vector within two or more control cycles of the pulse width modulation control from the voltage vector control means, all zero voltages within the two or more control cycles. If the sum of the output times of the vectors is shorter than a certain value, the output time of the zero voltage vectors existing in the middle of two adjacent cycles is adjusted to zero, and the output of the zero voltage vectors existing at both ends of the two cycles is adjusted. Adjusted to distribute in time Control device of a power converter, characterized in that. The method of claim 1, When the voltage vector adjusting means inputs, as a unit, a voltage vector within two or more control cycles of the pulse width modulation control from the voltage vector control means, all zero voltages within the two or more control cycles. When the sum of the output times of a vector is shorter than a fixed value, it adjusts so that the output time of the same voltage vector in two or more control periods may be put together. Control device of a power converter, characterized in that. The method of claim 1, A delay means for delaying the voltage vector output by the voltage vector adjusting means and outputting the voltage vector to the voltage vector adjusting means, wherein the voltage vector adjusting means includes a case in which the output time of the zero voltage vector is shorter than a predetermined value. Obtains the voltage vector used in the adjustment before one control period from the delay means, and outputs one of both zero voltage vectors in this period depending on whether or not the vector output last in the previous period is a zero voltage vector. To zero and distribute it to the output time of the other side Control device of a power converter, characterized in that. The method of claim 1, A delay means for outputting the voltage vector output by the voltage vector adjusting means and the output time of the completion of the adjustment to the voltage vector adjusting means by delaying the one control period, wherein the voltage vector adjusting means is 1 from the delay means. The output time of the zero voltage vector which was adjusted at the end of the previous cycle and the output time of the zero voltage vector which was first inputted from the voltage vector control means in this cycle by receiving the voltage vector used in the adjustment before the control period and its output time. If the sum with the output time is shorter than the fixed value, the time obtained by subtracting the output time of the zero voltage vector adjusted and outputted from the constant value at the end of the previous cycle from the fixed value at the end of this period. Adjusted to Control device of a power converter, characterized in that. The method of claim 1, A delay means for outputting the error according to the output time adjustment of the voltage vector output by the voltage vector adjusting means to the voltage vector adjusting means by delaying the one control period, wherein the voltage vector adjusting means outputs the voltage vector. With respect to the output time of the voltage vector which has a function of calculating the error according to time adjustment, and corrected the error calculated in the previous period input from the delay means to the output time of the voltage vector input from the voltage vector control means. If the output time of the zero voltage vector is longer than the predetermined value, adjust the output time of the zero voltage vector to a fixed value or more, and if it is short, adjust the zero voltage vector output time to zero. Control device of a power converter, characterized in that. The method of claim 1, The voltage vector adjusting means adjusts the output time of the zero voltage vector to a predetermined value or more without changing the relative ratio of the output time of the voltage vectors other than the zero voltage vector. Control device of a power converter, characterized in that. The method of claim 1, The voltage vector adjusting means adjusts the output time of a voltage vector other than the zero voltage vector to be equal to or higher than a predetermined value when the output time of the zero voltage vector is adjusted to zero. Control device of a power converter, characterized in that. The method of claim 1, In the case where the voltage vector adjusting means adjusts the output time of the zero voltage vector to zero, if the voltage vector output at the end of the previous period is different from the voltage vector initially output at this period, this period Changing the voltage vector initially output from to the voltage vector output last in the previous period Control device of a power converter, characterized in that. The method of claim 1, The adjustment by the voltage adjusting means compares the output time of the zero voltage vector with a predetermined time larger than zero, and adjusts the output time of the zero voltage vector based on the comparison result. controller. delete delete delete delete delete delete

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