KR100709767B1 - Fsk detector circuit - Google Patents

Abstract

The present invention applies the AFC signal to the LC parallel resonant circuit 14, and connects the voltage varactor diode [15 (3)] for level compensation in which the AFC signal is applied to the circuit 15 over 90 degrees. It is to provide an FSK detection circuit that minimizes changes.

To this end, a circuit of at least 90 degrees is connected between the first input terminal and the second input terminal, and a first input terminal FSK modulation signal is inputted to the second input terminal, and an FSK modulation signal of at least 90 degrees is transmitted to the second input terminal via the circuit angle of at least 90 degrees. LC parallel resonant circuit 13 connected to a supplied multiplication circuit 13 and a second input terminal and connected in parallel with a ceramic delimiter 14 (1) and a varactor diode 14 (3) to which an AFC signal is applied ( 14), the parallel connection circuit of the level compensation varactor diode 15 (3) and the capacitor 15 (4) to which the AFC signal is applied is connected to the circuit 15 or more by 90 degrees.

Description

FSK detection circuit {FSK DETECTOR CIRCUIT}

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the configuration of main parts of a receiver as an embodiment of a receiver using an FSK detection circuit according to the present invention.

FIG. 2 is a characteristic diagram showing the level change characteristic of the FSK detection signal level sent by the quadrature detector circuit shown in FIG. 1;

3 is a block diagram showing the configuration of main parts of a receiver disclosed in Japanese Patent Laid-Open No. 2002-27004.

※ Explanation of code for main part of drawing

1: High frequency signal input terminal

2: Bandpass Filter (BPF) 3: Low Noise High Frequency Amplifier (LNA)

4: high frequency filter (RF-FIL) 5: first mixer stage (MIX 1)

6: 1st intermediate frequency filter (IF-FIL1) 7: 2nd mixer stage (MIX 2)

8: 2nd intermediate frequency filter (IF-FIL2) 9: PLL circuit (PLL)

10: crystal oscillator 11: intermediate frequency amplifier stage (IFA)

12 Limiter amplifier (LM) 13 Multiplication circuit (MPX)

13 (1): first input terminal 13 (2): second input terminal

14: LC parallel resonant circuit 14 (1): ceramic disc limiter

14 (2): DC blocking capacitor 14 (3): Varactor diode

15: Circuit over 90 ° 15 (1), 15 (2), 15 (4): Condenser

15 (3): Varactor diode for level compensation

16: first operation amplifier (OA1)

17: comparator (COM)

18: second operation amplifier (OA2)

19: low pass filter (LF)

20: Data output terminal 21: Quadrature detector circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FSK (frequency shift keying) detection circuit having a quadrature demodulator comprising a multiplication circuit and an LC parallel resonant circuit, wherein the FSK detection is performed to increase the dynamic range (use signal bandwidth) of the LC parallel resonant circuit. It is about a circuit.

In a mobile vehicle such as an automobile, a door lock is provided to lock the door in order to prevent the vehicle from being stolen or the vehicle is intruded and the internal device is damaged. Conventionally, the locking or unlocking of the door lock has been performed by inserting a key for starting the engine into the key hole. However, in terms of convenience, the door lock is locked and unlocked by operating a switch of the portable transmitter without inserting the key into the key hole. A so-called active keyless entry device for performing the above is used. In recent years, a so-called passive keyless entry device has been used, which has a predetermined portable transceiver and does not operate a switch and, when located in a predetermined area, automatically locks or unlocks the door lock.

The passive keyless entry device comprises a vehicle-mounted transceiver mounted on a vehicle and a portable transceiver held by a user or the like. The passive keyless entry device transmits and receives radio signals between the vehicle-mounted transceiver and the portable transceiver during use. If the radio signal transmitted / received is a normal signal, predetermined control of the controlled device on the vehicle side, for example, the door lock is unlocked, enables the vehicle to be used immediately. If both signals are not normal signals, predetermined control of the controlled device on the vehicle side, for example, unlocking of the door lock is not performed, and therefore the vehicle cannot be used immediately.

At the time of operation of such a passive keyless entry device, a request signal including an ID unique to one's vehicle is wirelessly transmitted from a vehicle-mounted transceiver at a predetermined time. At this time, when the portable transceiver receives the request signal, it compares the ID of the vehicle included in the request signal with the ID of the regular vehicle already registered, and if the IDs match, the portable transceiver responds to the request signal. A radio signal is transmitted to the transceiver including a unique ID and a command signal for controlling a controlled device of the vehicle. This radio signal may be referred to as a response signal or an answer signal. Then, when the on-board transceiver receives this radio signal, the ID of the on-board transceiver included in the radio signal is compared with the ID of the on-board transceiver already registered, and when the IDs of the on-board transceiver match, the radio signal is matched. The command signal is extracted from the control unit, and predetermined control of the controlled device on the vehicle side, for example, the door lock is unlocked, in accordance with the extracted command signal.

By the way, in the keyless entry device, it is more convenient to have both of the passive operation and the active operation, but in the passive operation, the door is locked and unlocked unintentionally. It is required to operate at a position, so that the low frequency signal is transmitted from the vehicle side so as to shorten the communication reach distance. In active operation, on the other hand, considering the intended operation, a long communication arrival time is desired. Therefore, it is common that the transmission signal from the portable transceiver transmits a high frequency signal. In the communication using a high frequency signal, an FSK signal obtained by frequency-modulating a high frequency carrier wave by a signal or an ASK signal amplitude-modulated is transmitted.

By the way, when the high frequency radio signal transmitted from the portable transceiver includes an FSK modulated signal, a receiver capable of receiving and processing the FSK modulated signal, particularly a receiver having an FSK detection circuit, may be used as the receiver of the on-board transceiver. As an example of such a receiver, there is a receiver disclosed in Japanese Patent Laid-Open No. 2002-27004.

3 is a block diagram showing the configuration of main parts of a receiver disclosed in Japanese Patent Laid-Open No. 2002-27004.

As shown in Fig. 3, the receiver includes a reception antenna 41, a bandpass filter (BPF) 42, a high frequency amplification stage (RF-A) 43, a mixer stage 44, and a local oscillator ( 45), intermediate frequency filter (IF-F) 46, limiter amplifier (LM-A) 47, multiplier circuit 48 (1), LC parallel resonant circuit 48 (2), and 90 Quadrature detection circuit 48 consisting of a condenser [48 (3)], a low pass filter (LF) 49, an amplifier stage (AMP) 50, a comparator 51, and a use circuit ( 52). In this case, the quadrature detection circuit 48 includes a multiplier circuit 48 (1) having a first input terminal and a second input terminal, an LC parallel resonant circuit 48 (2) having an inductor and a capacitor connected in parallel, and 90 And a capacitor 48 (3) or more, wherein a capacitor 48 (3) of 90 degrees or more is connected between the first input terminal and the second input terminal of the multiplication circuit 48 (1) to multiply. The LC parallel resonant circuit 48 (2) is connected between the second input terminal of the circuit 48 (1) and the ground point.

This receiver having the above configuration operates as follows schematically.

When a high frequency radio signal including a FSK modulated signal (hereinafter, a high frequency radio signal including a modulated signal is referred to as a high frequency signal) is received by the reception antenna 41, the received high frequency signal is received by the band pass filter 42. Unnecessary frequency components outside the signal band are removed, and then amplified to a predetermined signal level in the high frequency amplifier stage 43, and then supplied to the first input stage of the mixer stage 44. At this time, the local oscillation signal output from the local oscillator 45 is supplied to the second input terminal of the mixer stage 44, whereby the high frequency signal and the local oscillation signal are frequency-mixed in the mixer stage 44, and the mixer stage 44 is provided. Frequency mixed signal is outputted. As for the output frequency mixed signal of the mixer stage 44, the intermediate frequency filter 46 which is the difference frequency of these two signals is extracted by the intermediate frequency filter 46, and the extracted intermediate frequency signal is the limiter amplifier 47. After the limited amplification at, it is supplied to the first input terminal of the multiplication circuit 48 (1) of the quadrature detection circuit 48 which follows. At the same time, the intermediate frequency signal is 90 degrees or more by the capacitor 48 (3) or more by 90 degrees and is supplied to the second input terminal of the multiplication circuit 48 (1).

The quadrature detection circuit 48 multiplies an intermediate frequency signal supplied to the first input terminal by an intermediate frequency signal of 90 ° or more supplied to the second input terminal in the multiplication circuit 48 (1). As a result, the FSK detection signal is output from the multiplication circuit 48 (1). This FSK detection signal is amplified to remove unnecessary signal components other than the FSK detection signal in the low pass filter 49, and subsequently amplified to the required signal level in the amplifying stage 50. Supplied. The comparator 51 generates coded data from the amplified FSK detection signal, supplies the obtained coded data to the use circuit 52, and performs control of the use circuit 52.

In the quadrature detection circuit 48 used in the receiver as described above, AFC (automatic) derived from the output of the amplifier stage 50 is used as the voltage variable capacitor as the capacitor of the LC parallel resonant circuit 48 (2). Frequency control) signal is applied to the voltage variable capacitor of the LC parallel resonant circuit 48 (2), that is, the capacitance value of the voltage variable capacitor of the LC parallel resonant circuit 48 (2) is AFC. By changing according to a signal, a means for changing the parallel resonant frequency and increasing the signal bandwidth of the FSK signal detectable in the quadrature detector circuit 48, i.e., the receivable bandwidth in the receiver, is known.

[Patent Document 1]

Japanese Patent Application Laid-Open No. 2002-27004

However, in the quadrature detection circuit of the type which applies the AFC signal to the LC parallel resonant circuit, the FSK detection output level is changed by the magnitude of the AFC voltage applied to the voltage variable capacitor of the LC parallel resonant circuit. Since the gain of the limiter amplifier 47 of the front end is hardly improved, the quadrature detector circuit with such a small level change is desired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above technical background, and an object thereof is to connect an AFC signal to an LC parallel resonant circuit and to connect a voltage compensating voltage compensating element for applying an AFC signal to a circuit of 90 ° or more. An object of the present invention is to provide an FSK detection circuit capable of minimizing changes in the FSK detection output level.

In order to achieve the above object, in the FSK detection circuit according to the present invention, a 90 ° or more circuit is connected between a first input terminal and a second input terminal, and an FSK modulation signal is supplied to the first input terminal, and a 90 ° or more circuit is provided to the second input terminal. A multiplier circuit to which an FSK modulation signal of 90 ° or more is supplied through the same, and an LC parallel resonant circuit connected to a second input terminal and a varactor diode to which an AFC signal is applied in parallel are connected. The circuit includes a parallel connection circuit in which a level compensation varactor diode to which the AFC signal is applied and a capacitor are connected in parallel.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

Fig. 1 is a block diagram showing the configuration of main parts of a receiver as an embodiment of a receiver using an FSK detection circuit according to the present invention.

As shown in FIG. 1, the receiver according to this embodiment includes a high frequency signal input terminal 1, a band pass filter (BPF) 2, a low noise high frequency amplifier stage (LNA) 3, and a high frequency filter (RF−). FIL) (4), first mixer stage (MIX 1) (5), first intermediate frequency filter (IF-FIL1) (6), second mixer stage (MIX 2) (7), second The intermediate frequency filter (IF-FIL2) 8, the PLL circuit (PLL) 9, the crystal oscillator 10, the intermediate frequency amplifier stage (IFA) 11, the limiter amplifier (LM) 12, A multiplication circuit (MPX) 13, an LC parallel resonant circuit 14, a 90 ° or more circuit 15, a first operation amplifier (OA1) 16, a comparator (COM) 17, A second operation amplifier (OA2) 18, a low pass filter (LF) 19, and a data output terminal (20). 1, the part enclosed by the dotted line is a part which consists of integrated circuits (IC), and the various elements which are outside the dotted line are the elements externally attached to the integrated circuit.

The circuit portion composed of the multiplication circuit 13, the LC parallel resonant circuit 14, and the 90 ° or more circuit 15 constitutes the quadrature detector circuit 21 as a whole. In this case, the LC parallel resonant circuit 14 includes a ceramic delimiter 14 (1), a DC blocking capacitor 14 (2) connected in series, and a varactor diode 14 (3) connected in parallel. Thus, the varactor diode 14 (3) is supplied with the AFC signal derived from the second operation amplifier 18 through the buffer resistor 14 (4). The 90 ° or more circuit 15 includes two capacitors 15 (1) and 15 (2), a level compensation varactor diode [15 (3)] and a capacitor [15 (4)] connected in series with them. And a parallel connection circuit of the circuit and the return resistance [15 (5)] of the AFC signal. The low pass filter 19 is composed of two resistors 19 (1) and 19 (2) and two capacitors 19 (3) and 19 (4), respectively.

In the band pass filter 2, the input terminal is connected to the high frequency signal input terminal 1, and the output terminal is connected to the input terminal of the low noise high frequency amplifier stage 3. The low noise high frequency amplifying stage 3 is connected to the first input terminal of the first mixer stage 5 while being connected to the ground via the high frequency filter 4. The first mixer stage 5 has an output stage connected to the first input stage of the second mixer stage 7 and grounded through the first intermediate frequency filter 6, and the second input stage is connected to the first input stage of the PLL circuit 9. 1 is connected to the output terminal. In the second mixer stage 7, the output stage is connected to the input terminal of the intermediate frequency amplifier stage 11 via the second intermediate frequency filter 8, and the second input stage is connected to the second output terminal of the PLL circuit 9. In the PLL circuit 9, a crystal oscillator 10 is connected to a reference signal input terminal.

In the intermediate frequency amplifier stage 11, the output terminal is connected to the input terminal of the limiter amplifier 12, and the limiter amplifier 12 is connected directly to the first input terminal [13 (1)] of the multiplication circuit 13. At the same time, it is connected to the second input terminal 13 (2) of the multiplication circuit 13 via a condenser 15 of 90 ° or more. In the multiplication circuit 13, the second input terminal 13 (2) is grounded via the LC parallel resonant circuit 14, and the output terminal is connected to the input terminal of the first operation amplifier 16. The first operation amplifier 16 is connected directly to the input of the comparator 17 and to the input of the second operation amplifier 18 through the low pass filter 19 at the same time. In this case, the active low pass filter is configured by the second operation amplifier 18 and the low pass filter 19. The comparator 17 has an output terminal connected to the data output terminal 20. The second operation amplifier 18 has an output terminal connected to the cathode of the varactor diode 14 (3) and the cathode of the level compensation varactor diode 15 (3) via the buffer resistor 14 (5). The level compensating varactor diode 15 (3) has an anode connected to ground via a return resistor 15 (5).

Here, the operation of the receiver according to this embodiment shown in FIG. 1 will be described.

When a high frequency radio signal (hereinafter, also referred to as a high frequency radio signal including a modulated signal) received from a receiving antenna (not shown in FIG. 1) is supplied to the high frequency signal input terminal 1, it is supplied. The undesired frequency components outside the signal band are removed by the band pass filter 2 and then amplified so as to reach a predetermined signal level in the low noise high frequency amplifying stage 3. The high frequency signal output from the low noise high frequency amplifier stage 3 extracts only a predetermined signal frequency component from the high frequency filter 4 and is supplied to the first input stage of the first mixer stage 5. At this time, the first local oscillation signal outputted from the first output end of the PLL circuit 9 is supplied to the second input end of the first mixer stage 5, whereby the high frequency signal and the first signal are generated in the first mixer stage 5. One local oscillation signal is frequency-mixed, and a first frequency mixed signal is output from the first mixer stage 5.

As for the 1st frequency mixed signal output from the 1st mixer stage 5, the 1st intermediate frequency signal which is the difference frequency of these 2 signals is extracted by the 1st intermediate frequency filter 6, and the extracted 1st intermediate frequency The signal is supplied to the first input terminal of the second mixer stage 7. At this time, the second local oscillation signal output from the second output terminal of the PLL circuit 9 is supplied to the second input terminal of the second mixer stage 7, whereby the first intermediate frequency in the second mixer stage 7 is supplied. The signal and the second local oscillation signal are frequency mixed, and the second frequency mixed signal is output from the second mixer stage 7. As for the output second frequency mixed signal of the second mixer stage 7, the second intermediate frequency signal, which is the difference frequency of those two signals, is extracted by the second intermediate frequency filter 8, and the extracted second intermediate frequency signal. Is amplified to a predetermined signal level in the intermediate frequency amplifier stage 11, and then limited amplified in the limiter amplifier 12, and then the first input terminal of the multiplication circuit 13 of the quadrature detection circuit 21 is subsequently performed. It is supplied to [13 (1)]. At the same time, the second intermediate frequency signal is 90 degrees or more by the circuit 15 or more by 90 degrees, and is supplied to the second input terminal 13 (2) of the multiplication circuit 13.

The quadrature detection circuit 21 has a second intermediate frequency signal supplied to the first input terminal 13 (1) and 90 ° or more supplied to the second input terminal 13 (2) in the multiplication circuit 13. The second intermediate frequency signal is multiplied, and the FSK detection signal is output to the output terminal of the multiplication circuit 13 by the multiplication. The FSK detection signal output from the multiplication circuit 13 is differentially amplified by the first operation amplifier 16, is then waveform-formed to the comparator 17 and supplied to the data output terminal 20, and the data output terminal 20. Is supplied to the use circuit (not shown). The output signal of the first operation amplifier 16 is converted into an AFC signal (error signal) through an active low pass filter constituted by the low pass filter 19 and the second operation amplifier 18.

The AFC signal obtained from the second operation amplifier 18 is transmitted to the cathode of the varactor diode 14 (3) and the cathode of the level compensation varactor diode 15 (3) through the buffer resistor 14 (4). Each of them is supplied to change the capacitance of the varactor diode 14 (3) and the capacitance of the level compensation varactor diode 15 (3) according to the AFC signal. At this time, when the level compensation varactor diode 15 (3) is supplied with an AFC signal to the LC parallel resonant circuit 14 to tune to an intermediate frequency, the level of the quadrature detector circuit 21 The change in the input signal level is suppressed by changing the capacitance value of the level compensation varactor diode 15 (3). In the case of the FSK signal, the detection output is shifted when a signal of a predetermined level or more is input. Depends on That is, when the intermediate frequency signal (FSK modulated signal) is applied to the LC parallel resonant circuit 14, and the state is changed to high frequency, the capacitance value of the varactor diode 14 (3) and the level compensation burr are changed by the AFC signal. When the capacity value of the varactor diode [15 (3) is reduced and the intermediate frequency signal (FSK modulated signal) is changed to a low frequency, the capacity value of the varactor diode [14 (3)] and the varactor diode for level compensation [ 15 (3)] to increase the input voltage.

2 is a characteristic diagram showing the level change characteristic of the quadrature detection circuit 21 shown in FIG. 1, where the horizontal axis is an AFC signal applied to the varactor diode represented by V, and the vertical axis is a multiplication circuit 13 expressed in dB. ), That is, the output level of the ceramic delimiter [14 (1)], and the curve a is a level compensation varactor diode [15 (3)] and a capacitor [15 (4). This is the case when parallel circuit with)] is connected. Curve b is a case in which the level compensation varactor diode [15 (3)] and the capacitor [15 (4)] are not connected. Curve c is connected to the level compensation varactor diode [15 (3)]. The case where the capacitor | condenser 15 (4) is not connected is all taken as an example for the comparison with curve a.

As shown in the characteristic diagram of FIG. 2, when the parallel circuit of the level compensation varactor diode 15 (3) and the capacitor | condenser 15 (4) is connected to the circuit more than 90 degrees, it shows in the curve a. Similarly, the AFC signal supplied to the varactor diode 14 (3) of the LC parallel resonant circuit 14 and the varactor diode 15 (3) for the level compensation of the circuit 15 or more at 90 degrees is the effective change region thereof. If the variation from 1.0 V to 4.5 V is obtained, the intermediate frequency signal level input to the quadrature detector 21 only exhibits a change in output level within a range of about 2 dB between about 3 dB and about 5 dB.

On the other hand, when the level compensation varactor diode 15 (3) and the capacitor 15 (4) are not connected to the circuit 15 or more by 90 degrees, the AFC supplied to the varactor diode 14 (3). When the signal fluctuates from 1.0 V to 4.5 V, which is the effective change range, it indicates an output level change within a range of about 6 dB between about -1 dB and about 5 dB, and the level compensation varactor is applied to the circuit 15 above 90 °. When the diode 15 (3) is connected but the capacitor 15 (4) is not connected, the AFC signal supplied to the varactor diode 14 (3) varies from 1.0 V to 4.5 V in its effective change range. This represents an output level change in the range of about 6 dB, ranging from about -1 dB to about 1 dB to about -5 dB.

As can be seen from the curve a shown in Fig. 2, when the parallel connection circuit between the level compensation varactor diode [15 (3)] and the capacitor [15 (4)] is connected to the circuit at least 90 degrees, the AFC Even if the signal fluctuates from 1.0 V to 4.5 V, which is the effective change region, the FSK detection signal output level change output from the quadrature detection circuit 21 can be suppressed by about 2 dB, thereby obtaining a good FSK detection signal. .

As described above, according to the FSK detection circuit according to the present invention, by applying an AFC signal to the varactor diode of the LC parallel resonant circuit, the parallel resonant frequency of the LC parallel resonant circuit is changed together with the AFC signal, and the LC parallel to the FSK modulated signal. By widening the intermediate frequency signal bandwidth of the resonant circuit and connecting the level compensation varactor diode to which the AFC signal is applied to the circuit above 90 °, the capacitance partial pressure of the FSK modulated signal of the circuit above 90 ° according to the magnitude of the AFC signal Since the ratio is changed, the FSK detection signal level change corresponding to the magnitude of the AFC signal can be reduced thereby.

Claims (1)

A circuit of 90 degrees or more is connected between a first input terminal and a second input terminal, and an FSK modulation signal is supplied to the first input terminal, and the FSK modulation signal of 90 degrees or more is supplied to the second input terminal through the 90 degrees or more circuit. A FSK detection circuit having a multiplier circuit to be connected and an LC parallel resonant circuit connected to the second input terminal and having a parallel connection between a ceramic delimiter and a varactor diode to which an AFC signal is applied, And the 90 ° or more circuit includes a parallel connection circuit in which a level compensation varactor diode to which the AFC signal is applied and a capacitor are connected in parallel.

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