KR100709769B1 - Fsk signal receiver - Google Patents

Abstract

The present invention applies an AFC signal to the first varactor diode [14 (2)] of the resonant circuit 14 and the second varactor diode [10 (2)] of the frequency determining circuit 10 to impair reception sensitivity. Instead, the present invention provides an FSK signal receiver that further expands the signal bandwidth that can be received.

For this purpose, a frequency converter, an intermediate frequency amplifier, and an FSK detector are provided. The FSK detector includes an FSK signal at the first input terminal 13 (1) and an FSK signal of 90 ° or more at the second input terminal 13 (2). A quadrature detector circuit by a resonant circuit 14 having a multiplier circuit 13 supplied and a first varactor diode 14 (2) connected to a second input terminal 13 (2) to which an AFC signal is applied. A second varactor diode having a PLL circuit 9 configured to generate a local oscillation signal in the frequency converter, and applying an AFC signal to the frequency determination circuit 10 of the PLL circuit 9; 10 (2)].

Description

FSK signal receiver {FSK SIGNAL RECEIVER}

1 is a block diagram showing a main part configuration of an embodiment of an FSK signal receiver according to the present invention;

FIG. 2 is a characteristic diagram showing a receivable signal frequency band ratio with respect to an AFC signal sent by the receiver shown in FIG.

3 is a block diagram showing the configuration of main parts of a receiver disclosed in Japanese Patent Laid-Open No. 2002-27004.

※ Explanation of code for main part of drawing

1: High frequency signal input terminal 2: Band pass filter (BPF)

3: low noise high frequency amplifier stage (LNA) 4: high frequency filter (RF-FIL)

5: 1st mixer stage (MIX 1) 6: 1st intermediate frequency filter (IF-FIL1)

7: 2nd mixer stage (MIX 2) 8: 2nd intermediate frequency filter (IF-FIL2)

9: PLL circuit (PLL) 10: frequency determination circuit

10 (1): crystal oscillator 10 (2): second varactor diode

10 (3): Capacitor 10 (4): Trimmer Capacitor

11: intermediate frequency amplifier stage (IFA) 12: limiter amplifier (LM)

13: multiplication circuit (MPX) 13 (1): first input terminal

13 (2): Second input stage 14: LC parallel resonant circuit

14 (1): Ceramic Delimiter 14 (2): First Varactor Diode

15: Condenser above 90 °

16: first operation amplifier (OA1)

17: comparator (COM)

18: second operation amplifier (OA2)

19: Low pass filter (LF) 20: Data output terminal

21: Quadrature Detection Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a frequency shift keying (FSK) signal receiver controlled by an AFC signal, and more particularly to an FSK signal receiver capable of expanding a receivable signal bandwidth.

In a mobile vehicle such as an automobile, a door lock is provided to lock the door in order to prevent the vehicle from being stolen or the vehicle is intruded and the internal device is damaged. Conventionally, the locking or unlocking of the door lock has been performed by inserting a key for starting the engine into the key hole. However, in terms of convenience, the door lock is locked and unlocked by operating a switch of the portable transmitter without inserting the key into the key hole. A so-called active keyless entry device for performing the above is used. In recent years, a so-called passive keyless entry device has been used, which has a predetermined portable transceiver and does not operate a switch and, when located in a predetermined area, automatically locks or unlocks the door lock.

The passive keyless entry device comprises a vehicle-mounted transceiver mounted on a vehicle and a portable transceiver held by a user or the like. The passive keyless entry device transmits and receives radio signals between the vehicle-mounted transceiver and the portable transceiver during use. If the radio signal transmitted / received is a normal signal, predetermined control of the controlled device on the vehicle side, for example, the door lock is unlocked, allows the vehicle to be used immediately, and on the other hand, If both signals are not normal signals, predetermined control of the controlled device on the vehicle side, for example, unlocking of the door lock is not performed, and therefore the vehicle cannot be used immediately.

At the time of operation of such a passive keyless entry device, a request signal including an ID unique to one's vehicle is wirelessly transmitted from a vehicle-mounted transceiver at a predetermined time. At this time, when the portable transceiver receives the request signal, it compares the ID of the vehicle included in the request signal with the ID of the regular vehicle already registered, and if the IDs match, the portable transceiver responds to the request signal. A radio signal (also called a response signal or an answer signal) including a unique ID and a command signal for controlling a controlled device of the vehicle is wirelessly transmitted to the transceiver. Then, when the on-board transceiver receives this radio signal, the ID of the on-board transceiver included in the radio signal is compared with the ID of the on-board transceiver already registered. The command signal is extracted from the control unit, and predetermined control of the controlled device on the vehicle side, for example, the door lock is unlocked, in accordance with the extracted command signal.

By the way, in the keyless entry device, it is more convenient to have both of the passive operation and the active operation, but in the passive operation, the door is approached to the vehicle because the door is locked and unlocked unintentionally. It is preferable to operate at, so that the low frequency signal is transmitted from the vehicle side so that the communication distance is shortened. In active operation, on the other hand, considering the intended operation, it is preferable that the communication distance is long, and therefore, the transmission signal from the portable transceiver generally transmits a high frequency signal. In the communication using a high frequency signal, an FSK signal obtained by frequency-modulating a high frequency carrier wave by a signal or an ASK signal amplitude-modulated is transmitted.

By the way, when the high frequency radio signal transmitted from the portable transceiver includes an FSK signal, it is necessary to use a receiver capable of receiving and processing the FSK signal, particularly a receiver having an FSK detection circuit, as a receiver of the on-board transceiver. As an example of such a receiver, there is a receiver disclosed in Japanese Patent Laid-Open No. 2002-27004.

3 is a block diagram showing the configuration of main parts of a receiver disclosed in Japanese Patent Laid-Open No. 2002-27004.

As shown in Fig. 3, the receiver includes a reception antenna 41, a band pass filter (BPF) 42, a high frequency amplifier stage (RF-A) 43, a mixer stage 44, and a local oscillator ( LO) 45, intermediate frequency filter (IF-F) 46, limiter amplifier (LM) 47, multiplication circuit (MPX) [48 (1)] and LC parallel resonant circuit [48 (2) ) And a quadrature detector circuit 48 consisting of a capacitor [48 (3)] of 90 degrees or more, a low pass filter (LF) 49, an amplifier stage (AMP) 50, a comparator 51, , The use circuit 52. In this case, the quadrature detection circuit 48 includes a multiplier circuit 48 (1) having a first input terminal and a second input terminal, an LC parallel resonant circuit 48 (2) having an inductor and a capacitor connected in parallel, and 90 And a capacitor 48 (3) or more, wherein a capacitor 48 (3) of 90 degrees or more is connected between the first input terminal and the second input terminal of the multiplication circuit 48 (1) to multiply. The LC parallel resonant circuit 48 (2) is connected between the second input terminal of the circuit 48 (1) and the ground point.

This receiver having the above configuration operates as follows schematically.

When a high frequency radio signal including a FSK modulated signal (hereinafter, a high frequency radio signal including a modulated signal is referred to as a high frequency signal) is received at the reception antenna 41, the received high frequency signal is a signal in the band pass filter 42. Unnecessary frequency components outside the band are removed, and then amplified to a predetermined signal level in the high frequency amplifier stage 43, and then supplied to the first input stage of the mixer stage 44. At this time, the local oscillation signal output from the local oscillator 45 is supplied to the second input terminal of the mixer stage 44, whereby the high frequency signal and the local oscillation signal are frequency-mixed in the mixer stage 44, and the mixer stage 44 is provided. Frequency mixed signal is outputted. As for the output frequency mixed signal of the mixer stage 44, the intermediate frequency filter 46 which is the difference frequency of these two signals is extracted by the intermediate frequency filter 46, and the extracted intermediate frequency signal is the limiter amplifier 47. After the limited amplification at, it is supplied to the first input terminal of the multiplication circuit 48 (1) of the quadrature detection circuit 48 which follows. At the same time, the intermediate frequency signal is 90 degrees or more by the capacitor 48 (3) or more by 90 degrees and is supplied to the second input terminal of the multiplication circuit 48 (1).

The quadrature detection circuit 48 multiplies an intermediate frequency signal supplied to the first input terminal by an intermediate frequency signal of 90 ° or more supplied to the second input terminal in the multiplication circuit 48 (1). As a result, the FSK detection signal is output from the multiplication circuit 48 (1). This FSK detection signal is amplified to remove unnecessary signal components other than the FSK detection signal in the low pass filter 49, and subsequently amplified to the required signal level in the amplifying stage 50. Supplied. The comparator 51 generates coded data from the amplified FSK detection signal, supplies the obtained coded data to the use circuit 52, and performs control of the use circuit 52.

In the quadrature detection circuit 48 used in the receiver as described above, AFC (automatic) derived from the output of the amplifier stage 50 is used as the voltage variable capacitor as the capacitor of the LC parallel resonant circuit 48 (2). Frequency control) signal is applied to the voltage variable capacitor of the LC parallel resonant circuit 48 (2), that is, the capacitance value of the voltage variable capacitor of the LC parallel resonant circuit 48 (2) is AFC. By changing according to a signal, a means for changing the parallel resonant frequency and increasing the signal bandwidth of the FSK signal detectable in the quadrature detector circuit 48, i.e., the receivable bandwidth in the receiver, is known.

Then, the detectable intermediate frequency signal bandwidth in the quadrature detector circuit 48 employing such means is compared with the detectable intermediate frequency signal bandwidth in the quadrature detector circuit 48 prior to employing the above means. If the latter intermediate frequency signal bandwidth is about ± 1 kHz, the former intermediate frequency signal bandwidth is greatly enlarged as ± 7 to 8 kHz.

[Patent Document 1]

Japanese Patent Application Laid-Open No. 2002-27004

In this way, if the quadrature detection circuit 48 adopts a means for applying the AFC signal to the LC parallel resonant circuit 48 (2) and changing the parallel resonant frequency of the LC parallel resonant circuit 48 (2), The intermediate frequency signal bandwidth of the detectable FSK signal in the quadrature detector circuit 48 can be greatly enlarged from ± 1 kHz to ± 7 to 8 kHz. However, in such a receiver, there is a desire to widen the bandwidth of the intermediate frequency signal from ± 7 to 8 kHz to ± 10 kHz in order to further widen the range of the receivable FSK signal. However, applying the AFC signal to the LC parallel resonant circuit 48 (2) and varying the parallel resonant frequency of the LC parallel resonant circuit 48 (2) merely employs the intermediate frequency signal bandwidth of ± 2 to It is difficult to widen 3 kHz further, and a solution of this point is required.

The present invention has been made in view of the above technical background, and an object thereof is to apply an AFC signal to a first varactor diode of a resonant circuit and a second varactor diode of a frequency determination circuit of a PLL circuit without impairing reception sensitivity. An object of the present invention is to provide an FSK signal receiver that further expands a receivable signal bandwidth.

In order to achieve the above object, the FSK signal receiver according to the present invention includes a frequency converter for converting a high frequency signal into an intermediate frequency signal, an intermediate frequency amplifier for amplifying an intermediate frequency signal, and FSK detecting an intermediate frequency signal for FSK. An FSK detector that derives a detection signal and an AFC signal, wherein the FSK detection unit includes a multiplier circuit for supplying an FSK signal to a first input terminal and an FSK signal of 90 ° or more to a second input terminal, and a ceramic filter connected to a second input terminal. A quadrature detector circuit comprising a resonant circuit connected in parallel with a first varactor diode to which an AFC signal is applied, wherein the frequency converter includes a PLL circuit and intermediates a high frequency signal using a local oscillation signal generated from the PLL circuit. Means for converting into a frequency signal and including a second varactor diode to which an AFC signal is applied to a frequency determining circuit of the PLL circuit. Equipped.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

Fig. 1 is a block diagram showing an essential part configuration as an embodiment of an FSK signal receiver according to the present invention.

As shown in FIG. 1, the FSK signal receiver according to this embodiment includes a high frequency signal input terminal 1, a band pass filter (BPF) 2, a low noise high frequency amplifier stage (LNA) 3, and a high frequency filter. (RF-FIL) (4), first mixer stage (MIX 1) (5), first intermediate frequency filter (IF-FIL1) (6), second mixer stage (MIX 2) (7), A second intermediate frequency filter (IF-FIL2) 8, a PLL circuit (PLL) 9, a frequency determining circuit 10, an intermediate frequency amplifier stage IFA 11, and a limiter amplifier LM. 12, multiplication circuit (MPX) 13, resonant circuit 14, 90 ° or more circuit 15, first operation amplifier (OA1) 16, comparator (COM) 17 And a second operation amplifier (OA2) 18, a low pass filter (LF) 19, and a data output terminal 20. 1, the part enclosed by the dotted line is a part comprised by integrated circuit (IC), and the various elements which are outside the dotted line are the elements externally attached to the integrated circuit.

The PLL circuit 9 has an externally mounted frequency determination circuit 10, and the frequency determination circuit 10 includes a crystal oscillator 10 (1), a second varactor diode [10 (2)] and a capacitor. [10 (3)], trimmer capacitor [10 (4)] and buffer resistor [10 (5)]. The circuit portion including the multiplication circuit 13, the resonant circuit 14, and the 90 ° or more circuit 15 constitutes the quadrature detector circuit 21 as a whole. In this case, the resonant circuit 14 includes a ceramic delimiter (ceramic filter) [14 (1)], a first varactor diode 14 (2), and a DC blocking capacitor 14 connected in series thereto. ] Is connected in parallel, and AFC signal derived from the 2nd operation amplifier 18 is supplied to the 1st varactor diode 14 (2) through the buffer resistor 14 (4). The low pass filter 19 is composed of two resistors 19 (1) and 19 (2) and two capacitors 19 (3) and 19 (4), respectively.

In the band pass filter 2, the input terminal is connected to the high frequency signal input terminal 1, and the output terminal is connected to the input terminal of the low noise high frequency amplifier stage 3. The low noise high frequency amplifying stage 3 is connected to the first input terminal of the first mixer stage 5 while being connected to the ground via the high frequency filter 4. The first mixer stage 5 has an output stage connected to the first input stage of the second mixer stage 7 and grounded through the first intermediate frequency filter 6, and the second input stage of the PLL circuit 9. It is connected to the first output terminal. In the second mixer stage 7, the output stage is connected to the input terminal of the intermediate frequency amplifier stage 11 via the second intermediate frequency filter, and the second input terminal is connected to the second output terminal of the PLL circuit 9. The PLL circuit 9 has a reference signal input terminal connected to the frequency determination circuit 10. The frequency determining circuit 10 includes a parallel connection circuit of a second varactor diode [10 (2)], a capacitor [10 (3)], and a trimmer capacitor [10 (4)] to a crystal oscillator 10 (1). In series connection, the AFC signal is supplied to the connection point of the crystal oscillator 10 (1) and the second varactor diode 10 (2) through the buffer resistor 10 (5).

In the intermediate frequency amplifier stage 11, the output terminal is connected to the input terminal of the limiter amplifier 12, and the limiter amplifier 12 is connected directly to the first input terminal [13 (1)] of the multiplication circuit 13. At the same time, it is connected to the second input terminal 13 (2) of the multiplication circuit 13 via a condenser 15 of 90 ° or more. In the multiplication circuit 13, the second input terminal 13 (2) is grounded via the resonant circuit 14, and the output terminal is connected to the input terminal of the first operation amplifier 16. The first operation amplifier 16 is connected to the input terminal of the second operation amplifier 18 through the low pass filter 19 while the output terminal is connected to the input terminal of the comparator 17. In this case, the second operation amplifier 18 and the low pass filter 19 constitute an active low pass filter. The comparator 17 has an output terminal connected to the data output terminal 20. In the second operation amplifier 18, the output terminal is connected to the cathode of the first varactor diode 14 (2) via the buffer resistor 14 (5), and likewise through the buffer resistor 10 (5). It is connected to the caso of two varactor diodes 10 (2).

Here, the operation of the receiver according to this embodiment shown in FIG. 1 will be described.

When a high frequency radio signal (hereinafter referred to as a high frequency radio signal including an FSK signal) received from a receiving antenna (not shown in FIG. 1) is supplied to the high frequency signal input terminal 1, The high frequency signal is removed in the band pass filter 2 so that unnecessary frequency components outside the signal band are removed, and then amplified so as to reach a predetermined signal level in the low noise high frequency amplifier stage 3. The high frequency signal output from the low noise high frequency amplifier stage 3 extracts only a predetermined signal frequency component from the high frequency filter 4 and is supplied to the first input stage of the first mixer stage 5. At this time, the first local oscillation signal outputted from the first output end of the PLL circuit 9 is supplied to the second input end of the first mixer stage 5, whereby the high frequency signal and the first signal are generated in the first mixer stage 5. One local oscillation signal is frequency-mixed, and a first frequency mixed signal is output from the first mixer stage 5.

As for the 1st frequency mixed signal output from the 1st mixer stage 5, the 1st intermediate frequency signal which is the difference frequency of these two signals is extracted by the 1st intermediate frequency filter 6, and the extracted 1st intermediate frequency The signal is supplied to the first input terminal of the second mixer stage 7. At this time, the second local oscillation signal output from the second output terminal of the PLL circuit 9 is supplied to the second input terminal of the second mixer stage 7, whereby the first intermediate frequency in the second mixer stage 7 is supplied. The signal and the second local oscillation signal are frequency mixed, and the second frequency mixed signal is output from the second mixer stage 7. As for the 2nd frequency mixed signal output from the 2nd mixer stage 7, the 2nd intermediate frequency signal which is the difference frequency of those 2 signals is extracted by the 2nd intermediate frequency filter 8, and the extracted 2nd intermediate frequency signal is carried out. The frequency signal is amplified by the intermediate frequency amplifier stage 11 so as to have a predetermined signal level, and then limited amplified by the limiter amplifier 12, and then the multiplier circuit 13 of the quadrature detection circuit 21 is subsequently made. 1 is supplied to the input terminal 13 (1). At the same time, the second intermediate frequency signal is 90 degrees or more by the circuit 15 or more by 90 degrees, and is supplied to the second input terminal 13 (2) of the multiplication circuit 13.

The quadrature detection circuit 21 has a second intermediate frequency signal supplied to the first input terminal 13 (1) and 90 ° or more supplied to the second input terminal 13 (2) in the multiplication circuit 13. The second intermediate frequency signal (the FSK signal of 90 degrees or more) is multiplied, and the FSK detection signal is output to the output terminal of the multiplication circuit 13 by the multiplication. The FSK detection signal output from the multiplication circuit 13 is differentially amplified by the first operation amplifier 16, waveform-formed by the comparator 17, and supplied to the data output terminal 20, and the data output terminal 20. Is supplied to a utilization circuit, not shown. The output signal of the first operation amplifier 16 is converted into an AFC signal (error signal) through an active low pass filter constituted by the low pass filter 19 and the second operation amplifier 18.

The AFC signal obtained from the second comparator 18 receives the second varactor through the cathode of the first varactor diode 14 (3) and the buffer resistor 10 (5) through the buffer resistor 14 (4). Supplied to the cathode of the diode 10 (2), respectively, and changes the capacitance of the first varactor diode 14 (2) and the capacitance of the second varactor diode 10 (2) according to the AFC signal. . In other words, when the FSK signal is applied to the resonant circuit 14 and the FSK signal is in a high frequency state, the capacitance value of the first varactor diode 14 (2) and the second varactor are changed by the AFC signal. When the capacitance value of the diode [10 (2)] is reduced and the FSK signal is shifted to a low frequency, the capacitance value of the first varactor diode [14 (2)] and the second varactor diode [10 (2)] are reduced. ] To increase the capacity value.

2 is a characteristic diagram showing a receivable signal frequency band ratio with respect to the AFC signal sent by the receiver shown in FIG. 1, where the horizontal axis is an AFC signal represented by V, and the vertical axis is a signal frequency band ratio expressed in kHz, and the curve a Is a case where the first varactor diode 14 (2) and the second varactor diode 10 (2) are used in combination. Curve b is a case where only the first varactor diode 14 (2) is used, which is taken as an example for comparison with curve a.

As shown in the characteristic diagram of FIG. 2, a second burr in which the AFC signal is applied to the resonant circuit 14 using the first varactor diode 14 (2), and the AFC signal is applied to the frequency determining circuit 10. When the varactor diode 10 (2) is used, the AFC signal supplied to the first varactor diode 14 (2) and the second varactor diode 10 (2), as shown by the curve a, is effective. When the change range is 0.5 V to 4.5 V, the receiver's receivable signal bandwidth is about ± 10 kHz relative to the center frequency.

In contrast, in the case where only the first varactor diode 14 (2) to which the AFC signal is applied to the resonant circuit 14 is used, it is supplied to the first varactor diode 14 (2), as shown by the curve b. When the AFC signal fluctuates from 0.5 V to 4.5 V, which is the effective change region, the receiver's receivable signal bandwidth is about ± 8 kHz relative to the center frequency, and when the second varactor diode [10 (2)] is used together, Approximately ± 2 kHz will be improved.

As can be seen from the curve a shown in Fig. 2, the first varactor diode 14 (2) to which the AFC signal is applied to the resonant circuit 14 is used, and the AFC signal is simultaneously applied to the frequency determining circuit 10. The use of an applied second varactor diode [10 (2)] allows the receiver to widen the receivable signal bandwidth compared to using only the first varactor diode [14 (2)]. In this case, the capacitance change of the second varactor diode 10 (2) is such that the S-shape detection characteristic of the quadrature detector circuit 21 in the signal band of the intermediate frequency circuit is high frequency with respect to the center frequency of the intermediate frequency signal. Since it slides in the low or low frequency direction, it is possible to widen the receivable signal bandwidth without changing the signal band of the intermediate frequency circuit, and as a result, the receivable signal bandwidth can be widened without compromising reception sensitivity. Will be.

In the above embodiment, the second varactor diode [10 (2)], the capacitor [10 (3)], the trimmer capacitor [10 (10) in series with the crystal oscillator 10 (1) as the frequency determination circuit 10. 4)] is described using an example in which a parallel connection circuit is connected. However, the frequency determining circuit 10 used in the present invention is not limited to the one having such a configuration, but at least a crystal oscillator 10 (1). If the second varactor diodes 10 (2) are connected in series with each other, it is possible to arbitrarily select the connection type, the number of connections, etc. of the capacitors other than those.

As described above, according to the FSK signal receiver according to the present invention, the first varactor diode to which the AFC signal is applied is connected to the resonant circuit in the quadrature detection circuit, and the resonant frequency of the resonant circuit is changed in accordance with the AFC signal. While widening the intermediate frequency signal bandwidth that can be detected for the FSK signal, a second varactor diode to which the AFC signal is applied is connected to the frequency determining circuit of the PLL circuit, and the local oscillation frequency output from the PLL circuit is changed in accordance with the AFC signal. Therefore, it is possible to further expand the receivable signal bandwidth without changing the signal bandwidth of the intermediate frequency circuit, that is, without impairing the signal reception sensitivity of the intermediate frequency circuit.

Claims (2)

An FSK signal receiver comprising a frequency converter for converting a high frequency signal into an intermediate frequency signal, an intermediate frequency amplifier for amplifying the intermediate frequency signal, and an FSK detector for FSK detection of the intermediate frequency signal to derive the FSK detection signal and the AFC signal. In The FSK detector includes a multiplier circuit for supplying an FSK signal to a first input terminal and an FSK signal of 90 ° or more to a second input terminal, and a first varactor diode connected to the second input terminal to which a ceramic filter and the AFC signal are applied. And a quadrature detector circuit comprising a resonant circuit connected in parallel, wherein the frequency converter includes a PLL circuit and converts a high frequency signal into an intermediate frequency signal using a local oscillation signal generated from the PLL circuit. And a second varactor diode to which the AFC signal is applied to a frequency determining circuit. The method of claim 1, The frequency determining circuit includes a series circuit of a crystal oscillator and the second varactor diode.

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