KR100707018B1 - Liquid-crystal display device - Google Patents

Abstract

The present invention discloses a Liquid-Crystal Display Device. According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a plurality of gate lines arranged in a row direction on a liquid crystal panel; A plurality of data lines arranged in a column direction on the liquid crystal panel; A plurality of switching thin film transistors arranged in a matrix at an intersection area of the plurality of gate lines and the plurality of data lines; A plurality of storage capacitors coupled between a drain terminal of the plurality of thin film transistors and a preceding gate line of the plurality of gate lines; And a discharge line for discharging static electricity input through the plurality of gate lines and the plurality of data lines, wherein a plurality of storage capacitors in a first row of the plurality of storage capacitors are coupled to the discharge lines, respectively It is a liquid crystal display device which forms a capacitance.

Description

Liquid crystal display device {LIQUID-CRYSTAL DISPLAY DEVICE}

1 is a circuit diagram illustrating a gate line of a conventional storage on comon method.

2 is a circuit diagram illustrating a conventional storage on gate gate line;

3A to 3C are circuit diagrams illustrating a liquid crystal display device constructed according to a conventional storage on gate method.

4A to 4C are circuit diagrams illustrating a liquid crystal display device including discharge lines according to an exemplary embodiment of the present invention.

5 is a circuit diagram illustrating a gate row electrode according to another exemplary embodiment of the present invention.

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device of a storage on gate type.

In general, a unit pixel of a liquid crystal display device has a structure in which a thin film transistor including a gate electrode, a source electrode, and a drain electrode is coupled with a gate line, a data line, and a pixel electrode, respectively. Liquid crystal capacitance is formed between the pixel electrode and the common electrode, storage capacitance is formed between the pixel electrode and the preceding gate line, and parasitic capacitance due to misalignment is generated between the gate electrode and the drain electrode. In this case, when the transistor is turned on, the voltage applied to the liquid crystal capacitor and the storage capacitor should be maintained even after the transistor is turned off. However, due to the parasitic capacitance Cgs, the voltage applied to the pixel electrode Will cause distortion. This distorted voltage is referred to as a feed through voltage (hereinafter referred to as? V _p ), which is obtained by the following equation.

Where Cgs is the parasitic capacitance between the gate electrode and the source electrode, Clc is the liquid crystal capacitance between the pixel electrode and the common electrode with the liquid crystal in between, Cst is the storage capacitance, and Vgp-p is the peak to peak of the gate. peak) voltage, respectively.

▽ V _p value is caused by the difference between the value of the first end and the end of the gate line when the gate voltage is supplied, and may cause flicker or other screen quality, which is caused by the offset of the common electrode. Set) can be adjusted by correction of the voltage, however, ▽ V _p is not a constant because it can vary depending on the variables of the equation (1) complete compensation is not possible. Therefore, the design is focused on narrowing the scope of ▽ V _p .

As a method for improving the above problem, a method of reducing ▽ V _p value by increasing the value of storage capacitance in a pixel is used.

Commonly used storage capacitance formation methods include a storage on common method in which a common electrode line independent of a gate line is separately arranged to be coupled with a storage capacitor, and a storage capacitor in combination with a preceding gate line of the gate line. There is a storage on gate method.

FIG. 1 is a circuit diagram illustrating a liquid crystal display device employing a conventional storage-on-comb method. As shown in FIG. 1, gate lines Gn to Gn + 1 and data lines Vn to Vn + are arranged on a liquid crystal panel. 1 are independently arranged for the plurality of thin film transistors T1 and T2 formed at the intersection of 1) and the adjacent gate lines Gn among the plurality of gate lines Gn + 1 and the gate lines Gn to Gn + 1. Comprising a common electrode line (Vcom), a plurality of storage capacitors (Cst1, Cst2) is formed between the plurality of thin film transistors (T1, T2) and the common electrode line (Vcom).

Next, FIG. 2 is a circuit diagram illustrating a liquid crystal cell array using a conventional storage on gate method. As shown in FIG. 2, a thin film transistor formed at an intersection of a gate line Gn + 1 and a data line V may be formed. A storage capacitor Cst is formed between T1 and T2 and the thin film transistors T1 and T2 and the preceding gate line Gn. Here, reference numeral Cgs denotes a parasitic capacitance generated between the source electrode s and the drain electrode d of the transistor, and reference numeral Clc denotes a liquid crystal capacitance generated between the drain electrode d and the common electrode Com in the pixel. to be.

However, as described above, when the liquid crystal cell array is configured in the storage-on-communication method, a common electrode line is disposed between the gate lines, which causes a problem that the aperture ratio is reduced, the transmittance is reduced, and the circuit is complicated. . For this reason, a liquid crystal cell array is constructed using the storage on gate method.

Hereinafter, a method of configuring a liquid crystal display device in a conventional storage on gate method will be described with reference to the accompanying drawings.

3A to 3C are circuit diagrams illustrating a liquid crystal display of a conventional storage on gate type.

As shown in FIG. 3A, in the conventional liquid crystal display device, a plurality of gate lines G1 to Gn + 1 are arranged on the liquid crystal panel with a predetermined interval to apply gate driving signals from the gate driver 10, respectively. And a plurality of data lines V1 to Vn + 1 are arranged at regular intervals to intersect the gate lines G1 to Gn + 1, and are configured to receive driving signals from the data driver 20, respectively.

In addition, a liquid crystal cell (not shown) in which a transistor is formed at each intersection of the gate lines G1 to Gn + 1 and the data lines V1 to Vn + 1 is arranged in the liquid crystal panel 30, and is generated during driving. In order to disperse static electricity, a short ring line 40 is formed at the edge of the liquid crystal panel for electrostatic discharge.

The short ring line 40 is coupled to the common electrode line Vcom formed at the last source pad part. In addition, the data lines V1 to Vn + 1, the shorting line 40, and the gate line G1 to absorb the static electricity flowing through the gate pad and the source pad when the circuit is driven to the short ring line 40. An antistatic circuit 50 is provided at each point at which ~ Gn + 1) and the short ring line 40 intersect. The transfer 60 is formed in contact with the common electrode line Vcom on the liquid crystal panel 30 to apply a common voltage Com of each liquid crystal cell.

FIG. 3B is an enlarged view of portion A of FIG. 3A to describe in detail the structures of the gate lines G1 to Gn + 1 and the shorting line 40 of the storage on gate type liquid crystal display.

As shown in FIG. 3B, in the conventional LCD, the gate electrode g is coupled to each gate line G1 to G2 and the source electrode s is coupled to the data lines V1 to V2 in an equivalent circuit. The liquid crystal capacitors Clc1 and Clc2 and the storage capacitors Cst1, which are connected in parallel between the switching thin film transistors T1 to T2, the drains d of the thin film transistors T1 to T2, and the common voltage Com in the pixel. Cst2).

Here, the storage capacitors Cst1 and Cst2 connected to the thin film transistors T1 to T2 have a structure connected to the preceding gate line. Thus, in order to configure the liquid crystal display device as described above, a plurality of first rows A preceding gate line to be coupled with the storage capacitor Cst1 is required, and a gate dummy line 70 to be coupled with the storage capacitor Cst1 of the first row is further configured.

FIG. 3C is a circuit diagram illustrating a wiring process of the shorting line 40 and the gate dummy line 70 opposite the gate pad 10 as part B of FIG. 3A. As shown, the shorting line 40 is coupled to the common electrode line Vcom at the last source pad 21 of the source pad portion 20 opposite to the gate pad 10.

However, in the liquid crystal display configured according to the above method, the gate dummy line 70 must be additionally formed to form the storage capacitance of the first row, and a separate signal line is also formed in the gate pad part 10. This requires space, so it doesn't fit the future trend of shrinking panels.

  Accordingly, the present invention has been made to solve the above problems of the prior art, and when the liquid crystal display device is configured by the conventional storage on gate method, the two lines have a gate dummy line and a discharge line in one line. It is an object of the present invention to provide a liquid crystal display device capable of reducing the size of a liquid crystal panel by simplifying a circuit configuration to simultaneously perform a unique function.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a plurality of gate lines arranged in a row direction on a liquid crystal panel; A plurality of data lines arranged in a column direction on the liquid crystal panel; A plurality of switching thin film transistors arranged in a matrix at an intersection area of the plurality of gate lines and the plurality of data lines; A plurality of storage capacitors formed between a drain terminal of the plurality of thin film transistors and a preceding gate line of the plurality of gate lines; And a discharge line for discharging static electricity input through the plurality of gate lines and the plurality of data lines, wherein the plurality of storage capacitors in the first row of the plurality of storage capacitors are the thin film in the discharge line and the first row. It is formed between the transistor drain terminal is characterized in that each forms a storage capacitance.

Hereinafter, a method of configuring a liquid crystal display device in a storage on gate method according to the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are used for the same signals as in the prior art for consistency of description.

4A to 4B are circuit diagrams for describing a storage on gate liquid crystal display device according to an exemplary embodiment of the present invention. As shown in FIG. 4A, a plurality of gate lines G1 to G2 are arranged on the liquid crystal panel 430 at predetermined intervals in a row direction to receive gate driving signals from the gate pad part 410, respectively. The plurality of data lines V1 to V2 are arranged at regular intervals in the column direction to intersect the gate lines G1 to G2, and are configured to receive driving signals from the source pad unit 420, respectively. The gate pad part 410 and the source pad part 420 are preferably electrically connected to a gate driver (not shown) and a source driver (not shown) that generate a driving signal.

In the liquid crystal panel 430, a plurality of switching thin film transistors T1 to T2 arranged in a matrix form at an intersection area of the plurality of gate lines G1 to G2 and the plurality of data lines V1 to V2 are gated. And an electrode, a source electrode, and a drain electrode, wherein the gate electrode is connected to the gate lines G1 to G2, and the source electrode is connected to the data lines V1 to V2, respectively.

The storage capacitors Cst1 and Cst2 are formed between the drain electrodes of the pixel thin film transistors T1 and T2 and the preceding gate lines of the plurality of gate lines G1 to G2, and the common electrode and the drain of the color filter in the pixel. Liquid crystal capacitors Clc1 and Clc2 are formed between the electrodes.

In addition, a discharge line 440 integrating a conventional gate dummy line and a shorting line is disposed at an edge of the liquid crystal panel 430. The drain electrode and the discharge line 440 of the thin film transistor T1 located in the first row are disposed. The storage capacitor Cst1 is formed therebetween.

In addition, the data lines V1 to Vn + 1, the discharge lines 440, and the gate lines G1 so that static electricity flowing through the gate pads and the source pads may be absorbed into the discharge lines 440 when the circuit is driven. An antistatic circuit 450 is provided at a point where ˜Gn + 1) and the discharge line 440 cross each other.

4B is a circuit diagram illustrating an opposite part of the gate pad 410 of the liquid crystal panel 430 to explain the voltage applied to the discharge line 440. As illustrated, the transfer 460 is in contact with the common electrode line Vcom on the liquid crystal panel 430 to apply a common voltage Com to each liquid crystal cell. In addition, one end portion of the discharge line 440 is connected to the common electrode line Vcom formed at the last source pad 421 of the source pad unit 420 as in the conventional short ring line.

Although not shown, portions other than the circuit diagram described in the present invention, that is, the lower end of the liquid crystal panel, are formed in the same manner as the conventional liquid crystal display device.

5 is a circuit diagram for explaining another embodiment of the present invention with respect to an applied voltage method of a discharge line.

 Since the liquid crystal display according to another exemplary embodiment of the present invention has the same structure as the exemplary embodiment of the present invention in the unit pixel including the gate line and the data line, a detailed description thereof will be omitted.

As shown in FIG. 5, a liquid crystal display according to another exemplary embodiment of the present invention includes a thin film transistor (not shown) and a thin film transistor arranged in a matrix form in a region where a plurality of gate lines and a plurality of data lines cross each other. A storage capacitor is formed between the drain terminal of the first gate line and the first gate line. The storage capacitor of the first row of the storage capacitors is formed between the drain terminal of the thin film transistor of the first row and the discharge line 540 formed around the liquid crystal panel 530. Has a structure.

Referring first to the portion E, one end portion of the discharge line 540 is connected to the common electrode line 542 formed on the last source pad 521 of the source pad portion 520, and the other end of the discharge line 540. One end portion is connected to the gate row electrode line 544 formed on the last source pad 521 of the source pad portion 520. The gate low voltage V _GLOW may be applied to the discharge line 540 through the gate low electrode line 544.
Next, referring to part C, the transfer 550 is configured not to be connected to the gate pad part 510.
Next, referring to part D, an antistatic circuit 560 is connected between the discharge line 540 connected to the gate row electrode line 544 and the discharge line 540 connected to the common electrode line 542. It is configured to control the generation of static electricity due to the voltage difference between the common electrode line 542 and the gate row electrode line 544.

As described above, according to the liquid crystal display device according to the present invention, when the liquid crystal display device is configured in a storage-on-gate method, a discharge line integrating the gate dummy line and the discharge line is connected to the storage capacitors in the first row of the liquid crystal panel. By reducing the V _p value and at the same time playing an antistatic role, screen quality can be improved.

In addition, the discharge line integrated into one can prevent data open since the portion where the data voltage crosses the gate line is reduced from one to two when compared with the conventionally configured lines. It works.

In addition, the circuit can be simplified, and the lines in the liquid crystal panel are reduced, so that the liquid crystal panel can be miniaturized.

On the other hand, the present invention is not limited to the above-described specific preferred embodiment, and any person having ordinary skill in the art to which the invention pertains can make various changes without departing from the gist of the invention claimed in the claims. something to do.

Claims (6)

A plurality of gate lines arranged in a row direction on the liquid crystal panel; A plurality of data lines arranged in a column direction on the liquid crystal panel; A plurality of switching thin film transistors arranged in a matrix at an intersection area of the plurality of gate lines and the plurality of data lines; A plurality of storage capacitors formed between a drain terminal of the plurality of thin film transistors and a preceding gate line of the plurality of gate lines; A discharge line for discharging static electricity input through the plurality of gate lines and the plurality of data lines, And a plurality of storage capacitors in a first row of the plurality of storage capacitors are formed between the discharge line and the drain terminals of the thin film transistors in the first row to each form a storage capacitance.   The method of claim 1,  And the discharge line is formed of a gate metal of the same material as the plurality of gate lines. delete The method of claim 1, A source pad unit for applying a driving signal to the plurality of data lines; The common electrode line is formed on the last source pad of the source pad part, The discharge line is connected to the common electrode line Liquid crystal display device characterized in that. delete The method of claim 1, And a source pad unit for applying a driving signal to the data line. The common electrode line and the gate row electrode line are formed on the last source pad of the source pad part, One end portion of the discharge line is connected to the common electrode line, and the other end portion of the discharge line is connected to the gate row electrode line. The discharge line includes at least one antistatic circuit for controlling the generation of static electricity due to the voltage difference between the common electrode line and the gate row electrode line Liquid crystal display device characterized in that.

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