KR100702007B1 - Semiconductor memory device and signal line arrangement method thereof - Google Patents

Abstract

The present invention discloses a semiconductor memory device and a signal line arrangement method thereof. The device comprises a plurality of first signal lines each consisting of first lines and second lines disposed on different layers on a memory cell array, and the first signal line on the memory cell array. And a plurality of second signal lines disposed on a layer in which the word line enable signal lines are not disposed in a direction orthogonal to each other, wherein the first line of the first signal line is the same as that of the first signal line. Disposed between the second lines and between the second lines of the first signal lines adjacent to each other, wherein the second line is adjacent to the first signal lines between the first lines of the same first signal line; Characterized in that arranged between the first lines of the. Therefore, even if the semiconductor memory device is highly integrated and chip size is increased, the semiconductor memory device can be operated at high speed.

Description

Semiconductor memory device and signal line arrangement method

1 is a diagram showing the configuration of a memory cell array of a conventional semiconductor memory device.

FIG. 2 is a diagram for describing a signal line arrangement method of the semiconductor memory device shown in FIG. 1. FIG.

3 is a view for explaining a signal line arrangement method of a semiconductor memory device according to a first embodiment of the present invention;

4 is a diagram illustrating a signal line arrangement method of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a view for explaining a signal line arrangement method of a semiconductor memory device according to a third embodiment of the present invention; FIG.

FIG. 6 is a diagram for describing a signal line arrangement method of a semiconductor memory device according to a fourth embodiment of the present invention; FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a signal line arrangement method thereof capable of operating a high-capacity and highly integrated semiconductor memory device at high speed.

A typical semiconductor memory device is divided into a memory cell array region and a peripheral circuit region, and signal lines (for example, word line selection signal and column selection signal) for inputting / outputting data are divided into two layers on top of these regions. Is placed.

However, as the semiconductor memory device becomes more integrated and faster, the number of signal lines required is increasing, which leads to an increase in the layout area of the semiconductor memory device, which causes many problems.

1 illustrates a configuration of a memory cell array of a semiconductor memory device according to an exemplary embodiment.

In Fig. 1, 10 denotes a memory cell array, 20 denotes a column decoder, 30 denotes a row decoder, CJ denotes a junction region, SWD denotes a sub wordline driver region, S / A denotes a sense amplifier region, and SMCA. Denotes a sub memory cell array area, respectively.

NWE uses a plurality of word line enable signal lines, CSL uses a plurality of column select signal lines, LIO uses a plurality of local data I / O lines, GIO uses a plurality of global data I / O lines, and PL uses a plurality of power lines. Represent each.

In the memory cell array 10 illustrated in FIG. 1, a block including a junction region CJ, a sub word line driver region SWD, a sense amplifier region S / A, and a sub memory cell array region SMCA is horizontally oriented. And are arranged repeatedly in the longitudinal direction. A control signal generation circuit for controlling the sub word line driver and a control signal generation circuit for controlling the sense amplifier are disposed in the junction region CJ, and sub word line drivers are disposed in the sub word line driver region SWD. In the sense amplifier S / A, sense amplifiers are arranged.

The function, signal line, and power line arrangement of each of the blocks shown in FIG. 1 will be described below.

The memory cell array 10 includes a memory cell MC connected between a sub word line SWL and a bit line BL, and includes a signal and a column selection signal line transferred to the word line enable signal line NWE. Write / read data to / from the selected memory cell MC in response to the signal transmitted to CSL). The column decoder 20 receives an operating voltage through the power line PL, decodes the column address CA, and generates column select signals for selecting a specific column select signal line CSL. The row decoder 30 receives an operating voltage through the power line PL to decode the row address RA to generate word line enable signals for selecting the word line enable signal line NWE.

The word line enable signal line NWE is disposed in the vertical direction on the sub word line driver area SWD and the sub memory cell array area SMCA.

The local input / output line LIO is disposed in the same direction as the word line enable signal line NWE on the junction region CJ and the sense amplifier region S / A sub memory cell array region SMCA.

The column select signal line CSL and the global data input / output line GIO are disposed on the sense amplifier area S / A and the sub memory cell array area SMCA in a direction perpendicular to the word line enable signal line NWE. do.

The first power line PL1 is disposed in the same direction as the word line enable signal line NWE on the junction region CJ and the sense amplifier region S / A, and the second power line PL2 is selected by a column. The remaining area between the signal line CSL and the global input / output line GIO is disposed in a direction orthogonal to the word line enable signal line NWE. That is, the first power line PL1 and the second power line PL2 are arranged in a mesh form.

FIG. 2 is a diagram illustrating a signal line and a power line arrangement method of the semiconductor memory device shown in FIG. 1. The same blocks and lines as those of FIG. The metal lines arranged and the diagonally filled lines represent the metal lines arranged in the second layer, respectively. That is, the first metal layer is formed by the metal lines arranged on the first layer, and the second metal layer is formed by the metal lines arranged on the second layer, so that the signal lines and the power lines are composed of a total of three metal layers. .

Referring to the signal line and power line arrangement method shown in Figure 2 as follows.

The word line enable signal lines NWE are disposed on one layer in the vertical direction. The first power line PL1 is disposed on one layer in the same direction as the word line enable signal line NWE.

The column select signal line CSL and the global data input / output lines GIO are disposed on two layers in a direction orthogonal to the word line enable signal lines NWE, that is, in a horizontal direction. The second power lines PL2 are disposed on the second layer in the same direction as the column select signal lines CSL in the remaining area between the column select signal lines CSL and the global data input / output lines GIO.

As a result, the word line enable signal lines NWE, the local data input / output lines LIO, and the power lines PL are arranged in the same direction on the first floor, and the column select signal lines CSL and the global data input / output lines are arranged in the same direction. The GIO and the power lines PL are disposed in a direction perpendicular to the word line enable signal lines NWE on the second layer.

The number of signal lines arranged in this manner, in particular, the word line enable signal lines NWE and the column select signal lines CSL, may be determined by address coding of the column decoder 20 and the row decoder 30 of the semiconductor memory device. As the semiconductor memory device becomes more integrated and larger in capacity, the number thereof increases.

That is, as semiconductor memory devices become more integrated and larger in capacity, the number of signal lines arranged in a memory cell array having a limited area increases.

As a result, a process margin that can form a plurality of metal layers appears, and the width of the signal line and the spacing between the signal lines are also reduced, resulting in a sharp increase in the loading and coupling effects of the signal lines.

If the loading and coupling effects of the signal lines are increased, the signals transmitted through these signal lines will have incorrect information due to the increased delay time and the increased coupling effects, resulting in deterioration of operating characteristics of the semiconductor memory device. .

In addition, as the number of signal lines to be disposed in the limited area of the memory cell array increases, the area in which the power lines can be disposed is reduced, so that a large number of power lines cannot be disposed. This causes a problem that the power to be supplied to the circuits in the memory cell array cannot be stably supplied.

Therefore, the semiconductor memory device according to the related art has a problem that the line width and the spacing of the signal lines are reduced as the capacity and the density are increased, and thus, the high speed operation cannot be stably supported.

Disclosure of Invention An object of the present invention is to provide a semiconductor memory device capable of stably supporting high-speed operation even when the semiconductor memory device becomes large in size and highly integrated.

Another object of the present invention is to provide a signal line arrangement method of a semiconductor memory device for achieving the above object.

A semiconductor memory device of the present invention for achieving the above object is a plurality of first signal lines each consisting of a first line and a second line disposed in different layers on the memory cell array, and the memory cell array And a plurality of second signal lines disposed on a layer in which the word line enable signal lines are not disposed in a direction orthogonal to the first signal lines of the first signal lines, wherein the first lines of the first signal lines are identical to each other. Disposed between the second lines of a first signal line and between the second lines of the first signal lines adjacent, the second line being adjacent to the first lines of the same first signal line And the first lines of the first signal lines.

According to another aspect of the present invention, there is provided a method of arranging signal lines in a semiconductor memory device, wherein each of a plurality of first signal lines is divided into first lines and second lines, and the first lines and the second lines. Disposing lines in different layers on the memory cell array; and disposing the plurality of second signal lines on the memory cell array in a direction orthogonal to the first signal lines. Disposing a layer, wherein the first line of the first signal line is disposed between the second lines of the same first signal line and between the second lines of the first signal lines adjacent to each other. The second line may be disposed between the first lines of the same first signal line and between the first lines of the adjacent first signal lines.

Hereinafter, a semiconductor memory device and a signal line arrangement method thereof according to the present invention will be described with reference to the accompanying drawings.

3 is a view illustrating a signal line arrangement method of a semiconductor memory device according to a first embodiment of the present invention, in which blocks and lines identical to those of FIG. 1 are denoted by the same reference numerals, and lines without diagonal lines are represented by 1. The metal lines arranged in the layer, the diagonally filled lines represent the metal lines arranged in the second layer, and the dotted lines represent the metal lines arranged in the third layer, respectively. That is, the first metal layer is formed by the metal lines arranged in the first layer, the second metal layer is formed by the metal lines arranged in the second layer, and the third metal layer is formed by the metal lines arranged in the third layer. The signal line and the power lines are formed of a total of three metal layers.

Referring to the signal line arrangement method shown in Figure 3 as follows.

The local data input / output lines LIO and the first power lines PL1 are arranged on the first floor in the same manner as in FIG. 2, and the column select signal lines CSL, the global data input / output lines GIO, and The two power lines PL2 are arranged on the second layer in the same manner as in FIG. 2.

The word line enable signal lines NWE are arranged as follows.

The word line enable signal lines NWE are separated into first word line enable signal lines NWE1 and second word line enable signal lines NWE2 so as to be alternated up, down, left, and right.

That is, each of the first word line enable signal lines NWE1 of the word line enable signal line NWE is between the second word line enable signal lines NWE2 of the same word line enable signal line NWE. And second word line enable signal lines NWE2 of word line enable signal lines NWE adjacent to each other, wherein each of the second word line enable signal lines NWE2 is the same word line enable signal. The first word line enable signal lines NWE1 of the line NWE are separated from each other and the first word line enable signal lines NWE1 of the adjacent word line enable signal lines NWE.

The first word line enable signal lines NWE1 are disposed on the first layer in the vertical direction, and the second word line enable signal lines NWE2 are disposed on the first word line enable signal lines NWE1. Place on the third floor in the vertical direction over the unoccupied area.

One end of the first word line enable signal line NWE1 adjacent to the second word line enable signal line NWE2 and the second word line enable signal adjacent to the first word line enable signal line NWE1. One end of the line NWE2 is overlapped with each other on the sub word line driver region SWD, and then connected through the via VIA. The same signal is transmitted through the first word line enable signal lines NWE1 and the second word line enable signal lines NWE1 that are alternately arranged on the same line.

According to the signal line arrangement method of the semiconductor memory device of FIG. 3, the line spacing of the word line enable signal lines NWE disposed on the same metal layer is a line of the word line enable signal lines NWE according to the related art. It is doubled over the interval. Accordingly, the signal line width of the word line enable signal lines NWE may be increased to reduce the loading and coupling effects of the signal lines and to facilitate the processing of the signal lines.

In addition, all of the word line enable signal lines NWE of FIG. 3 may include a first word line enable signal line NWE1 disposed on a first layer and a second word line enable signal line NWE2 disposed on a second layer. It is formed through the junction box and therefore has the same loading. This provides an effect of preventing the occurrence of skew between the word line enable signal lines (NWE) in advance.

Accordingly, in the method of arranging signal lines of the semiconductor memory device of FIG. 3, since the number of word line enable signal lines NWE to be disposed on the same metal layer is large, it is difficult to arrange the word line enable signal lines NWE. This is a suitable line layout method for memory devices.

4 is a view illustrating a signal line arrangement method of a semiconductor memory device according to a second exemplary embodiment of the present invention. The same blocks and lines as those shown in FIG. 2 are denoted by the same reference numerals. Lines without diagonal lines represent metal lines arranged on the first floor, lines filled with diagonal lines represent metal lines arranged on the second floor, and lines filled with dots represent metal lines arranged on the third floor, respectively. It consists of three metal layers.

Referring to the signal line arrangement method shown in Figure 4 as follows.

The column select signal line CSL, the global data input / output line GIO, and the second power line PL2 are disposed on the second layer in the same manner as in FIG. 2.

The word line enable signal lines NWE, the local input / output line LIO, and the first power lines PL1 are arranged as follows.

The word line enable signal lines NWE, the local input / output line LIO, and the first power lines PL1 are alternately arranged up, down, left, and right so that the first lines NWE1, LIO1, PL3 and the second lines ( NWE2, LIO2, PL4).

That is, each of the first lines NWE1, LIO1, PL3 of the signal lines NWE, LIO, PL1 is adjacent to between the second lines NWE2, LIO2, PL4 of the same signal line NWE, LIO, PL1. Disposed between the second lines NWE2, LIO2, and PL4 of the signal lines NWE, LIO, and PL1, and each of the second lines NWE2, LIO2, and PL4 is the same signal line (NWE, LIO, PL1). The first lines NWE1, LIO1, and PL3 are separated from each other, and the first lines NWE1, LIO1, and PL3 of adjacent signal lines NWE, LIO, and PL1 are separated from each other.

The first lines NWE1, LIO1, PL3 are disposed on the first layer in the vertical direction, and the second lines NWE2, LIO2, PL4 are disposed on an area where the first lines NWE1, LIO1, PL3 are not disposed. Place on the third floor in the vertical direction.

One end of the second line NWE2 adjacent to the first line NWE1 and one end of the first line NWE1 adjacent to the second line NWE2 overlap each other on the sub word line driver region SWD. Connect via VIA. The junction region CJ is connected to one end of the second lines LIO2 and PL4 adjacent to the first lines LIO1 and PL3 and one end of the first lines LIO1 and PL3 adjacent to the second lines LIO2 and PL4. Overlap each other from above and connect via a via (VIA).

In the method of arranging signal lines of the semiconductor memory device of FIG. 4, the word line enable signal lines NWE are not only word line enable signal lines NWE but also a large number of other lines LIO and PL1. ) And other lines (LIO, PL1) is a line arrangement method suitable for a semiconductor memory device is not easy.

The number of lines to be arranged on the same layer as the word line enable signal lines NWE and the word line enable signal line NWE to be disposed in the restricted region according to the operating characteristics of the semiconductor memory device is described above. The present invention proposes a signal line arrangement method suitable for a case where the number of lines to be disposed on the same layer as the CSL and the column select signal lines CSL.

However, depending on the operation characteristics and the design method of the semiconductor memory device, column selection is greater than the number of lines to be arranged on the same layer as the word line enable signal line NWE and the word line enable signal line NWE. In some cases, the number of lines to be disposed on the same layer as the signal lines CSL and the column select signal lines CSL may occur.

Therefore, the following further proposes a signal line arrangement method suitable in the above case.

5 is a view illustrating a signal line arrangement method of a semiconductor memory device according to a third exemplary embodiment of the present invention. The same blocks and lines as those shown in FIG. 2 are denoted by the same reference numerals. Lines without diagonal lines represent metal lines arranged on the first floor, lines filled with diagonal lines represent metal lines arranged on the second floor, and lines filled with dots represent metal lines arranged on the third floor, respectively. It consists of three metal layers.

Referring to the signal line arrangement method shown in Figure 5 as follows.

The word line enable signal lines NWE, the local input / output line LIO, and the first power lines PL1 are disposed on the first layer in the same manner as in FIG. 2, and the global data input / output lines GIO, and The second power lines PL2 are disposed on the second layer in the same manner as in FIG. 2.

The column select signal lines CSL are arranged as follows.

The column select signal lines CSL are separated into first column select signal lines CSL1 and second column select signal lines CSL1 so as to alternate up, down, left, and right.

That is, each of the first column selection signal lines CSL1 of the column selection signal line CSL is adjacent to the second column selection signal lines CSL2 of the same column selection signal line CSL. Disposed between the second column select signal lines CSL2 of the CSL, and each of the second column select signal lines CSL2 is the first column select signal lines CSL1 of the same column select signal line CSL. Are separated to be disposed between the first column selection signal lines CSL1 of the column selection signal lines CSL adjacent thereto.

The first column select signal lines CSL1 are disposed on two layers in the horizontal direction, and the second column select signal lines CSL2 are disposed in the horizontal direction on an area where the first column select signal lines CSL1 are not disposed. Place on the third floor.

One end of the first column select signal line CSL1 adjacent to the second column select signal line CSL2 and one end of the second column select signal line CSL2 adjacent to the first column select signal line CSL1 are sense amplifiers. After overlapping each other on the area S / A, the connection is made through a via VIA.

The signal line arrangement method of the semiconductor memory device of FIG. 5 increases the spacing and line width of the column select signal line CSL in the same manner as in FIG. 3 to reduce the loading and coupling effects of the signal line and Make the process easier.

The column select signal lines CSL are all formed by connecting the first column select signal line CSL1 disposed on the second layer and the second column select signal line CSL2 disposed on the third layer to have the same loading. do. This provides an effect of preventing the skew between the column select signal lines CSL in advance.

Therefore, the signal line arrangement method of the semiconductor memory device of FIG. 5 should be disposed on the same metal layer so that the number of the column select signal lines CSL is large so that it is not easy to arrange the column select signal lines CSL. Placement method.

FIG. 6 is a view illustrating a signal line arrangement method of a semiconductor memory device according to a fourth embodiment of the present invention. The same blocks and lines as those of FIG. 2 are denoted by the same reference numerals. Lines without diagonal lines represent metal lines arranged on the first floor, lines filled with diagonal lines represent metal lines arranged on the second floor, and lines filled with dots represent metal lines arranged on the third floor, respectively. It consists of three metal layers.

Referring to the signal line arrangement method shown in Figure 6 as follows.

The lines NWE, the local input / output lines LIO, and the first power lines PL1 are disposed on the first layer in the same manner as in FIG. 2.

The column select signal line CSL, the global data input / output lines GIO, and the second power line PL2 are arranged as follows.

The first lines CSL1, GIO1, and PL5 and the second lines so that each of the column select signal line CSL, the global data input / output lines GIO, and the second power lines PL2 are alternated up, down, left, and right. CSL2, GIO2, PL6).

That is, each of the first lines CSL1, GIO1, and PL5 of each signal line CSL, GIO, and PL1 may be connected between the second lines CSL2, GIO2, and PL6 of the same signal line CSL, GIO, and PL1. Disposed between the second lines CSL2, GIO2, and PL6 of adjacent signal lines CSL, GIO, and PL1, and each of the second lines CSL2, GIO2, and PL6 is the same signal line CSL, GIO, or PL1. Are separated between the first lines CSL1, GIO1, and PL5 and between the first lines CSL1, GIO1, and PL5 of the adjacent signal lines CSL, GIO, and PL1.

The first lines CSL1, GIO1, and PL5 are disposed on the first floor in the horizontal direction, and the second lines CSL2, GIO2, and PL6 are not disposed on the first lines CSL1, GIO1, and PL5. Place it on the third floor in the horizontal direction.

One end of the second lines CSL2, GIO2 and PL6 adjacent to the first lines CSL1, GIO1 and PL5 and the first lines CSL1, GIO1 and PL5 adjacent to the second lines CSL2, GIO2 and PL6. One ends of the are overlapped with each other on the sense amplifier region (S / A) or junction region (CJ), and then connected through the via (VIA).

In the method of arranging signal lines of the semiconductor memory device of FIG. 6, the column selection is performed in the same metal layer, so that not only the column select signal line CSL but also the global data input / output lines GIO and the second power lines PL2 are selected. A line arrangement method suitable for a semiconductor memory device in which it is not easy to arrange the signal line CSL, the global data input / output lines GIO, and the second power lines PL2.

As described above, the signal line arrangement method of FIGS. 3 to 6 secures the line width and the spacing of the signal lines even when the semiconductor memory device becomes large in size and high density, and allows the entire signal lines to have the same loading so as to operate at high speed. Supports stable operation.

In the above description, each signal line (NWE, CSL) is composed of one first line (NWE1, CSL1) and second line (NWE2, CSL2) in the preferred embodiment, but in the practical application example, each signal line Naturally, the NWE and CSL may be formed of the plurality of first lines NWE1 and CSL1 and the plurality of first lines NWE2 and CSL2 while passing through the entire memory cell array area.

In addition, although the word line enable signal line NWE is disposed on the first layer and the column select signal line CSL is disposed on the second layer in the preferred embodiment, the signal lines are arranged in different layers. Naturally, the signal line can be arranged by applying the above method.

In addition, as an example of a line disposed on the same layer as the word line enable signal line NWE, only the local input / output line LIO and the power line PL1 have been described. However, the same direction as the word line enable signal line NWE is described. Naturally, various signal lines may be arranged by applying the above method. In addition, it is natural that various signal lines having the same direction as that of the column select signal line CSL may be arranged by applying the above method.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

The semiconductor memory device and the method of arranging signal lines thereof according to the present invention allow a signal line to have a sufficient line width and line spacing by adding a metal layer on top and distributing the signal lines to the added metal layer. .

Therefore, even if the semiconductor memory device has a large capacity and high integration, it is possible to secure a sufficient line width and spacing of the signal line, thereby securing a process margin and reducing the loading of the signal line to perform high-speed operation.

In addition, it is possible to stably perform high-speed operation by allowing all of the distributed signal lines to have the same loading.

In addition, as the spacing between signal lines increases, a larger number of power lines are arranged to supply the power of circuits in the memory cell array more stably.

Claims (22)

A semiconductor memory device having a memory cell array, the semiconductor memory device comprising: A plurality of first signal lines each consisting of first and second lines disposed on different layers on the memory cell array; And A plurality of second signal lines disposed in a layer in which the plurality of first signal lines are not disposed in a direction orthogonal to the plurality of first signal lines on the memory cell array; The first lines of the plurality of first signal lines are disposed between the second lines of the same plurality of first signal lines and between the second lines of the plurality of first signal lines adjacent to the And second lines are disposed between the first lines of the same plurality of first signal lines and between the first lines of the plurality of first signal lines adjacent to each other. The semiconductor memory device of claim 1, wherein the first lines and the second lines of each of the plurality of first signal lines transmit the same signal. The method of claim 1, wherein the first lines and the second lines of the plurality of first signal lines are disposed on the different layers, and the plurality of second signal lines are disposed on the lower layers of the different layers. A semiconductor memory device. The method of claim 1, wherein the first lines and the second lines of the plurality of first signal lines are disposed on the different layers, and the plurality of second signal lines are disposed on an intermediate layer of the different layers. A semiconductor memory device. The method of claim 1, wherein the first and second lines of the plurality of first signal lines are disposed on the different layers, and the plurality of second signal lines are disposed on an upper layer of the different layers. A semiconductor memory device. The method of claim 1, wherein the plurality of first signal lines And word line enable signal lines. The method of claim 6, wherein the plurality of second signal lines And column select signal lines orthogonal to the word line enable signal lines. The semiconductor memory device of claim 6, wherein the semiconductor memory device comprises: Sub memory cell array blocks having memory cells connected between a sub word line and a bit line arranged in a direction orthogonal to the sub word line; Sub word line driver blocks disposed vertically between the sub memory cell array blocks; And And sense amplifier blocks disposed left and right between the sub memory cell array blocks; The first lines and the second lines of the word line enable signal lines are disposed on the sub memory cell array blocks and the sub word line driver blocks, and the first lines and the second lines And a sub word line driver block. The method of claim 1, wherein the plurality of first signal lines And the column select signal lines. The method of claim 9, wherein the plurality of second signal lines And word line enable signal lines orthogonal to the column select signal lines. The semiconductor memory device of claim 9, wherein the semiconductor memory device comprises: Sub memory cell array blocks having memory cells connected between a sub word line and a bit line arranged in a direction orthogonal to the sub word line; Sub word line driver blocks disposed vertically between the sub memory cell array blocks; And And sense amplifier blocks disposed left and right between the sub memory cell array blocks; The first lines and the second lines of the column select signal lines are disposed on the sub memory cell array blocks and the sense amplifier blocks, and the first lines and the second lines are the sense amplifier blocks. A semiconductor memory device, characterized in that connected from above. A signal line arrangement method of a semiconductor memory device having a memory cell array, the method comprising: Separating each of the plurality of first signal lines into first and second lines, and disposing the first and second lines in different layers on the memory cell array; And Disposing a plurality of second signal lines on a layer in which the plurality of first signal lines on the memory cell array are not disposed in a direction orthogonal to the plurality of first signal lines; The first lines of the plurality of first signal lines are disposed between the second lines of the same plurality of first signal lines and between the second lines of the plurality of first signal lines adjacent to the The second lines are arranged between the first lines of the same plurality of first signal lines and between the first lines of the plurality of first signal lines adjacent to each other. Way. The method of claim 12, wherein the first lines and the second lines of each of the plurality of first signal lines transmit the same signal. The method of claim 12, wherein the first and second lines of the plurality of first signal lines are disposed on the different layers, and the plurality of second signal lines are disposed on a lower layer of the different layers. A signal line arrangement method of a semiconductor memory device. The method of claim 12, wherein the first and second lines of the plurality of first signal lines are disposed on the different layers, and the plurality of second signal lines are disposed on an intermediate layer of the different layers. A signal line arrangement method of a semiconductor memory device. The method of claim 12, wherein the first and second lines of the plurality of first signal lines are disposed on the different layers, and the plurality of second signal lines are disposed on an upper layer of the different layers. A signal line arrangement method of a semiconductor memory device. The method of claim 12, wherein the plurality of first signal lines Signal line arrangement method of a semiconductor memory device, characterized in that the word line enable signal lines. 18. The method of claim 17, wherein the plurality of second signal lines And column select signal lines orthogonal to the word line enable signal lines. The semiconductor memory device of claim 17, wherein the semiconductor memory device comprises: Sub memory cell array blocks having memory cells connected between a sub word line and a bit line arranged in a direction orthogonal to the sub word line; Sub word line driver blocks disposed vertically between the sub memory cell array blocks; And And sense amplifier blocks disposed left and right between the sub memory cell array blocks; The first lines and the second lines of the word line enable signal lines are disposed on the sub memory cell array blocks and the sub word line driver blocks, and the first lines and the second lines A signal line arrangement method of a semiconductor memory device, characterized in that connected on the sub word line driver blocks. The method of claim 12, wherein the plurality of first signal lines Signal line arrangement method of a semiconductor memory device, characterized in that the column selection signal lines. 21. The method of claim 20, wherein the plurality of second signal lines And word line enable signal lines orthogonal to the column select signal lines. 21. The semiconductor memory device of claim 20, wherein the semiconductor memory device is Sub memory cell array blocks having memory cells connected between a sub word line and a bit line arranged in a direction orthogonal to the sub word line; Sub word line driver blocks disposed vertically between the sub memory cell array blocks; And And sense amplifier blocks disposed left and right between the sub memory cell array blocks; The first lines and the second lines of the column select signal lines are disposed on the sub memory cell array blocks and the sense amplifier blocks, and the first lines and the second lines are the sense amplifier blocks. Signal line arrangement method of a semiconductor memory device, characterized in that connected from above.

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