JP2004119457A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of disturbing a high-speed operation due to a mixture of an interference noise generated at one bit line of adjacent bit lines to each other with the other bit line in a semiconductor device only by a memory cell layout without increasing the area of a memory cell array. <P>SOLUTION: A semiconductor storage device includes a memory cell having a switching transistor connected to a source, and a storage capacitor for storing data with one electrode connected to the source. Bit lines 40, 41 of I/O lines of the data connected to a drain of the switching transistor are formed in a hierarchical structure formed of a metal wiring layer different from adjacent bit lines, and a shielding bit line 49 is provided in a vacant region of an upper layer side from the bit line formed in the hierarchical structure. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a dynamic random access memory circuit (DRAM), for example, having two transistors and one storage capacitor in one memory cell. The present invention relates to a semiconductor memory device which is effective for layout design of a memory cell array section.
[0002]
[Prior art]
A dual word line and dual bit line “low latency DRAM cell” disclosed in US Pat. No. 5,856,940 will be described as a semiconductor memory device with reference to the drawings. The low latency DRAM cell has two transistors and one storage capacitor per memory cell, and each memory cell is connected to two word lines and two bit lines, respectively.
[0003]
FIG. 20 is a circuit diagram showing a configuration of a memory cell of a semiconductor memory device having a conventional "wait-time-saving DRAM cell". The memory cell 20 shown in FIG. 20 includes a first transistor 22, a second transistor 23, and a storage capacitor 24. For example, in the first transistor 22, the gate is connected to the first word line WLa. Connected, the drain is connected to the first bit line BLa, the source is connected to the storage node 21, the gate of the second transistor 23 is connected to the second word line WLb, and the drain is the second bit line The storage capacitor 24 is configured so that one electrode is connected to the storage node 21 and the other electrode is a cell plate.
[0004]
As described above, the memory cell 20 has the first transistor 22 and the second transistor 23 that can be independently controlled with respect to one storage capacitor 24. Therefore, in the memory cell 20, access by the first word line WLa, the first transistor 22, and the first bit line BLa, and access to the second word line WLb, the second transistor 23, and the second bit line BLb , An interleave operation can be performed. Thus, the memory cell 20 can be accessed using the other bit line while precharging or the like is performed on one bit line, so that the read operation and the write operation can be performed at high speed.
[0005]
[Patent Document 1]
U.S. Pat. No. 5,856,940
[0006]
[Problems to be solved by the invention]
However, in the conventional semiconductor memory device having the "low-wait-time DRAM cell", an interleave operation is performed on an adjacent bit line which is a data input / output line, so that the first bit line BLa (n) ( When n = 0, 1, 2,... and the second bit line BLb (n) (n = 0, 1, 2,...) operate mutually, coupling noise due to the change in bit line potential at this time is adjacent. And the high-speed operation is hindered.
[0007]
In view of the above, the present invention solves the above-described problem of hindering high-speed operation with only the memory cell layout without increasing the area in the memory cell array portion, and solves one of the bit lines adjacent to each other. It is an object of the present invention to provide a semiconductor memory device that prevents interference noise generated in a bit line from being mixed into another bit line.
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, a solution taken by the invention according to claim 1 is a memory including a switching transistor connected to a source, and a storage capacitor for data storage having one electrode connected to the source. A bit line, which is a data input / output line connected to the drain of the switching transistor, is formed in a hierarchical structure including a metal wiring layer different from an adjacent bit line; A shield bit line is provided in a vacant region above the formed bit line.
[0009]
With such a configuration, the first bit line, which is an input / output line for data forming the memory cell, and the second bit line adjacent to the first bit line are formed of different metal wiring layers. In addition to the hierarchical bit line structure, the shield bit line is provided in a vacant region above the bit lines formed and arranged by the hierarchical structure, so that the interference noise generated on one bit line is reduced by the other bit line. It can be prevented from being mixed into the wire.
[0010]
According to the second aspect of the present invention, the bit lines adjacent to each other are alternately arranged.
With such a configuration, the load on the bit line due to the different metal wiring layers can be evenly distributed.
[0011]
According to the third aspect of the present invention, the vacant area below the bit line is configured as a plate lining area.
With such a configuration, the resistance of the plate electrode can be reduced, and interference noise from the bit line-cell plate capacitance can be reduced.
[0012]
In the invention according to claim 4, each of the plurality of transistors includes a first switching transistor and a second switching transistor whose sources are connected to each other, and a storage capacitor for data storage whose one electrode is connected to the source. A plurality of first bit lines, each of which is formed by a first-layer metal wiring connected to the drain of the first switching transistor, and serving as a data input / output line; A plurality of second bit lines connected to the drain of the transistor and each formed of a second-layer metal wiring alternately arranged in a hierarchical structure with the first bit lines, the second bit lines being data input / output lines; And so on.
[0013]
Such a configuration is based on the above-mentioned "low latency DRAM cell", but the first bit line and the second bit line have a hierarchical structure so that the same metal wiring layer is formed. Are not adjacent to each other, so that interference between bit lines can be prevented without increasing the pitch between bit lines.
[0014]
According to the fifth aspect of the present invention, the first and second bit lines, which are adjacent data input / output lines, are alternately arranged.
With such a configuration, the load on the bit line due to the different metal wiring layers can be evenly distributed.
[0015]
According to a sixth aspect of the present invention, the shield bit line is provided in a vacant area above the bit line which is a data input / output line having a hierarchical structure.
With such a configuration, noise of interference between bit lines can be suppressed by the shield effect of the shielded bit lines.
[0016]
According to the seventh aspect of the present invention, the vacant area below the bit line is configured as a plate lining area.
With such a configuration, the resistance of the plate electrode can be reduced, and interference noise from the bit line-cell plate capacitance can be reduced.
[0017]
In the invention according to claim 8, the arrangement of the first bit lines and the second bit lines, which are the data input / output lines formed using the hierarchical structure, is alternately arranged for each sense amplifier column. It is.
[0018]
In such a configuration, for example, the arrangement of the first bit lines BLa (n) and the second bit lines BLb (n) is specifically referred to as a, b, b, a, a, b, b, a,. As described above, the same port is arranged adjacently by alternately replacing every pair in the sense amplifier column unit, whereby a part of the wiring between the first word line and the second word line is bent. Therefore, the layout area of the storage capacitor for storing data can be increased, and the memory cell capacity can be increased without increasing the entire area of the memory cell array.
[0019]
According to the ninth aspect of the present invention, the layers of the first bit line and the second bit line, which are the input / output lines of adjacent data, are alternately arranged.
With such a configuration, when performing an interleaving operation on the first bit line and the second bit line adjacent to each other, a high-speed operation generated on one bit line due to a change in bit line potential is impeded. It is possible to take a memory cell layout structure in which coupling noise does not mix into adjacent bit lines.
[0020]
According to a tenth aspect of the present invention, the shield bit line is provided in a vacant area above the bit line which is a data input / output line having a hierarchical structure.
[0021]
With such a configuration, noise of interference between bit lines can be suppressed by the shield effect of the shielded bit lines.
According to the eleventh aspect of the present invention, the vacant area below the bit line is configured as a plate lining area.
[0022]
With such a configuration, the resistance of the plate electrode can be reduced, and interference noise from the bit line-cell plate capacitance can be reduced.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 2 shows a circuit configuration of the memory cell according to the first embodiment. As shown in FIG. 2, the memory cell 30 has a switching transistor 32 and a storage capacitor 33. The switching transistor 32 has a gate connected to the word line WL, a drain connected to the bit line BL, and a source connected to the storage node 31. The storage capacitor 33 has one electrode connected to the storage node 31 and the other electrode serving as a cell plate. Here, the memory cell 30 is referred to as a 1Tr1C cell.
[0024]
FIG. 1 shows a schematic layout configuration of a memory cell array in a semiconductor memory device according to a first embodiment of the present invention. Here, a bit line BL1 (n = 0, 2,...) 40 and BLm (m = 1, 3,...) 41 extending in the row direction and a shield bit line 49 are provided.
[0025]
FIG. 3 is a diagram showing a configuration corresponding to a configuration obtained by removing the shield bit line 49 from the layout configuration of FIG. Hereinafter, a schematic layout configuration of the memory cell array will be described in detail with reference to FIG. The bit lines BL1 (n = 0, 2,...) 40 and BLm (m = 1, 3,...) 41 extending in the row direction are alternately provided and formed of different metal wiring layers. Here, reference numeral 42 denotes a word line WL, which is arranged in a direction intersecting the direction of the bit lines 40 and 41 and is formed by a polysilicon wiring which functions as a gate electrode of a transistor for selectively connecting a memory cell to the bit lines 40 and 41. Have been. 43 is a memory cell capacitor, 44 is a memory cell transistor, and 45 is a contact for electrically connecting the bit line and the memory cell transistor.
[0026]
The layout configuration shown in FIG. 1 is different from the layout configuration of FIG. 3 in that a shield bit line 49 is provided in a vacant region above the bit line 40.
[0027]
With such a configuration, noise due to interference between bit lines can be suppressed by the shield effect of the shield bit line 49. Also, as shown in FIG. 3, the adjacent bit line BL140 and bit line BLm41 are formed of different metal wiring layers, so that interference noise between bit lines can be suppressed without increasing the pitch between bit lines. Thus, a synergistic effect between the interference noise suppressing effect and the interference noise suppressing effect of the shield bit line 49 can be expected.
(Second practical form)
FIG. 4 shows a schematic layout configuration of a memory cell array in a semiconductor memory device according to a second embodiment of the present invention. FIG. 5 is a schematic cross-sectional view taken along line AA in FIG. FIG. As in the first embodiment, the bit lines BLl (l = 0, 2,...) 60 and BLm (m = 1, 3,...) 61 extending in the row direction are different metal wiring layers. , And a shield bit line 62 is arranged in a vacant region above the bit line 60.
[0028]
In FIG. 5, bit line contacts and the like are omitted. The bit line BL160 and the bit line BLm61 have a hierarchical structure, and a shield bit line 62 is arranged in a hierarchical part of a bit line formed by a lower metal wiring. Due to the shielding effect, noise due to interference between bit lines is suppressed.
(Third embodiment)
FIG. 6 shows a schematic layout configuration of a memory cell array in a semiconductor memory device according to a third embodiment of the present invention. The bit lines BL1 (l = 0, 2,...) 50 and BLm (m = 1, 3,...) 51 extending in the row direction are arranged such that different metal wiring layers 52, 53 are alternately arranged. It is configured. Although not shown, the same shield bit line as that shown in FIGS. 1 and 4 to 5 is also provided in the memory cell array of FIG.
[0029]
This makes it possible to equalize the load on the bit lines 50 and 51 depending on the difference in hierarchy. In addition, the synergistic effect of being able to suppress the noise of interference between the bit lines 50 and 51 and being able to suppress the interference noise with the shielded bit lines ensures that the interference noise between the bit lines is reduced. Can be suppressed.
[0030]
Although the wiring layers are exchanged for each memory cell in the drawing, the same applies when the interconnection layers are exchanged for two or more memory cells.
(Fourth embodiment)
FIG. 7 shows a schematic configuration of a 1Tr1C memory cell in a semiconductor memory device according to a fourth embodiment of the present invention, in which bit lines BL1 (l = 0, 1, 2,. ..) 80 and BLm (m = 0, 1, 2,...) 81 are provided alternately and are composed of different metal wiring layers. A word line 85 is arranged in a direction intersecting the bit lines 80 and 81, and is formed by a polysilicon wiring functioning as a gate electrode of a transistor for selectively connecting a memory cell to the bit line. 82 is a memory cell capacitor, 83 is a memory cell transistor, and 84 is a backing region of a cell plate.
[0031]
Here, a backing region 84 of a plate is formed by a metal wiring of a lower layer in an empty region of a lower layer of a bit line 81 which is a data input / output line provided in a hierarchical structure using a metal wiring. Thereby, the resistance of the plate electrode can be reduced, and the interference noise between the bit line and the cell plate can be reduced.
(Fifth practical form)
FIG. 8 shows a schematic configuration of a memory cell array in a semiconductor memory device according to a fifth embodiment of the present invention. A first sense amplifier system circuit 9A is provided at one end of the first bit line BLa (n = 0, 1, 2,...), And the second bit line BLb (n = 0, 1, 2,. ..) Are provided with second sense amplifier circuits 9B at ends opposite to the first sense amplifier circuits 9A.
[0032]
Also, a first word line WLa (j = 0, 1, 2,...) And a second word line WLb each intersecting the first bit line BLa (n) and the second bit line BLb (n) (J = 0, 1, 2,...) Are provided so as to extend alternately in the column direction. 90 is a 2Tr1C cell.
[0033]
FIG. 9 shows a circuit configuration of a 2Tr1C cell 90 according to the present embodiment. As shown in FIG. 9, a memory cell 90 is provided in a region surrounded by a first word line WLa and a second word line WLb and a first bit line BLa and a second bit line BLb, respectively. Has been. Further, the 2Tr1C cell 90 has a first switch transistor 102, a second switch transistor 103, and a storage capacitor 104. The first switch transistor 102 has a gate connected to the first word line WLa, a drain connected to the first bit line BLa, and a source connected to the storage node 101. The second switch transistor 103 has a gate connected to the second word line WLb, a drain connected to the second bit line BLb, and a source connected to the storage node 101. The storage capacitor 104 is configured such that one electrode is connected to the storage node 101 and the other electrode is a cell plate.
[0034]
FIG. 10 is a schematic layout structure diagram of a memory cell array in a 2Tr1C cell. Here, 110 is a bit line BLa (n) formed of a first-layer metal wiring, 111 is a bit line BLb (n) formed of a second-layer metal wiring, and 112 intersects the bit lines 110 and 111. The word lines WLa and 113 formed by polysilicon wiring arranged in the same direction and serving as a gate electrode of a transistor for selectively connecting a memory cell to a bit line are word lines WLb formed in the same manner as the word line 112. . 114 is a memory cell capacitor, 115 is a memory cell transistor, and 116 is a contact for electrically connecting the bit lines 110 and 111 and the memory cell transistor.
[0035]
FIG. 11 is a timing chart of changes in the bit line potentials BLa and BLb of the port a and the port b in the semiconductor memory device having the 2Tr1C cell. For example, when attention is paid to port a, interference noise is superimposed upon sensing of port b during precharge operation of port a, which affects amplification operation and hinders high-speed operation. However, by adopting the memory cell layout structure as described above, in the semiconductor memory device having the 2Tr1C cell according to the present embodiment, for example, during the read operation, the first bit line and the second bit line Has a hierarchical structure, the metal wiring layers are not adjacent to each other, so that interference between the bit lines BLa (n) and BLb (n) can be prevented without increasing the pitch between bit lines.
(Sixth embodiment)
FIG. 12 shows a schematic layout configuration of a memory cell array of the aforementioned 2Tr1C memory cells in the semiconductor memory device according to the sixth embodiment of the present invention. The bit lines BLa (n = 0, 1, 2,...) 130 and BLb (n = 0, 1, 2,...) 131 extending in the row direction are configured so that different metal wiring layers are alternately replaced. I have. With such a configuration, the load on the bit lines can be equalized due to the difference in hierarchy, and noise due to interference between bit lines can be suppressed. Also, in the figure, the wiring layers are replaced for each memory cell, but the same is true even if the wiring layers are replaced for two or more memory cells.
(Seventh embodiment)
FIG. 13 shows a schematic layout configuration of the aforementioned 2Tr1C memory cell array in the semiconductor memory device according to the seventh embodiment of the present invention. Each of the bit lines BLa (n) 140 and BLa (n + 1) 141 extending in the row direction is formed of an upper metal wiring layer, and is a hierarchical portion which is an upper free space of a bit line formed of a lower metal wiring. Is provided with a shield bit line 142.
[0036]
With such a configuration, noise of interference between the bit lines 140 and 141 is suppressed by the shield effect of the shield bit line 142. This embodiment can provide a greater effect by combining with the fifth and sixth embodiments.
(Eighth embodiment)
FIG. 14 shows a schematic layout configuration of the aforementioned 2Tr1C memory cell array in the semiconductor memory device according to the eighth embodiment of the present invention. In the semiconductor device of this embodiment, bit lines BLa (n = 0, 1, 2,...) 150 and BLb (n = 0, 1, 2,...) 151 extending in the row direction are provided alternately. And different metal wiring layers. Reference numeral 152 denotes a word line WLa, which is arranged in a direction crossing the bit lines 150 and 151, and is formed of a polysilicon wiring which functions as a gate electrode of a transistor for selectively connecting a memory cell to the bit lines 150 and 151. 153 is a word line WLb formed similarly to the word line WLa152. 154 is a memory cell capacitor, 155 is a memory cell transistor, and 156 is a lining area of a cell plate.
[0037]
That is, in the semiconductor memory device according to the eighth embodiment, the lining 156 of the plate is provided with the metal wiring in the free space below the bit line 151 which is the data input / output line provided in a hierarchical structure using the metal wiring. It is what went. Thus, the resistance of the plate electrode can be reduced, and the interference noise between the bit line and the cell plate can be reduced.
(Ninth embodiment)
FIG. 15 shows a schematic layout configuration of the aforementioned 2Tr1C memory cell array in the semiconductor memory device according to the ninth embodiment of the present invention. A first sense amplifier system circuit 16A is provided at one end of the first bit line BLa (n), and the second bit line BLb (n) is provided on the opposite side of the first sense amplifier system circuit 16A. At the ends, second sense amplifier circuits 16B are provided. Here, the arrangement of the first bit lines BLa (n) and the second bit lines BLb (n) is alternate for each pair. WLa (j) (j = 0, 1, 2,...) Is a first word line, WLb (j) (j = 0, 1, 2,...) Is a second word line, and 90 is a 2Tr1C cell. .
[0038]
FIG. 16 shows a layout diagram of a memory cell in the present embodiment. By adopting a configuration in which the first bit line BLa (n) 171 and the second bit line BLb (n) 172 are adjacent to each other at the same port, a space formed by bending the word lines WLa 173 and WLb 174 can be secured. The layout of the memory cell capacitor 175 can be processed. As a result, the size of the memory cell capacitor can be increased without increasing the layout area of the memory cell array, and the memory cell capacity can be increased.
(Tenth embodiment)
FIG. 17 shows a schematic layout configuration of a memory cell array in a 2Tr1C memory cell in the ninth embodiment based on the semiconductor memory device of the tenth embodiment of the present invention. The bit lines BLa (n = 0, 1, 2,...) 180 and BLb (n = 0, 1, 2,...) 181 each extending in the row direction are configured such that different metal wiring layers are alternately replaced. Have been. This makes it possible to equalize the load on the bit lines 180 and 181 due to the difference in hierarchy, and to suppress interference noise between the bit lines 180 and 181. Also, in the figure, the wiring layers are replaced for each memory cell, but the same is true even if the wiring layers are replaced for two or more memory cells.
(Eleventh practical form)
FIG. 18 shows a 2Tr1C memory cell according to the ninth embodiment based on the semiconductor memory device according to the eleventh embodiment of the present invention, in which the first bit lines BLa (n) 190 and BLa (n + 1) 191 Shield bit lines 192 formed of the same layer of metal wiring are arranged between them. This makes it possible to suppress interference noise between the bit lines 190 and 191 without increasing the pitch between the bit lines 190 and 191 and increasing the layout area of the memory cell array unit. The eleventh embodiment provides a greater effect when combined with the tenth embodiment.
(Twelfth embodiment)
FIG. 20 shows a schematic configuration of a 2Tr1C memory cell according to the ninth embodiment based on the semiconductor memory device according to the twelfth embodiment of the present invention. Here, reference numeral 200 denotes a backing area of the cell plate. That is, here, in the semiconductor memory device of the ninth embodiment, the plate is backed 200 with the lower metal wiring in the free space below the bit line provided by the upper metal wiring. Thereby, the resistance of the plate electrode can be reduced, and the interference noise between the bit line and the cell plate can be reduced. Note that 171 and 172 are bit lines, and 173 and 174 are word lines.
[0039]
In the above, the present invention has been described with reference to the layout diagrams based on the embodiments. However, the present invention is not limited to only the above-described embodiments, and can be changed without departing from the gist thereof. For example, the case where the semiconductor memory device according to the above embodiment is applied to a DRAM has been described. However, the present invention is not limited to the DRAM, and can be widely applied to other semiconductor memories. The present invention can be applied to a semiconductor memory which is required to reduce interference noise between bit lines.
[0040]
【The invention's effect】
As described above, according to the present invention, the memory cells having the hierarchical bit line structure are provided, and the shield bit lines are arranged, so that the adjacent bit lines can be arranged without increasing the layout area between the adjacent bit lines. An excellent semiconductor memory device that can reduce intervening interference noise only by the layout structure of the memory cell can be realized.
[Brief description of the drawings]
FIG. 1 is a schematic layout diagram showing a memory cell array in a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a circuit diagram of a memory cell in the semiconductor device of FIG. 1;
FIG. 3 is a schematic layout diagram showing a memory cell array in the semiconductor device according to the first embodiment of the present invention, excluding a shield bit line;
FIG. 4 is a schematic layout diagram showing a memory cell array in a semiconductor device according to a second embodiment of the present invention;
FIG. 5 is a sectional view taken along line AA in FIG. 4;
FIG. 6 is a schematic layout diagram showing a memory cell array in a semiconductor device according to a third embodiment of the present invention;
FIG. 7 is a schematic plan view showing a memory cell array in a semiconductor device according to a fourth embodiment of the present invention.
FIG. 8 is a schematic plan view showing a memory cell array in a semiconductor device according to a fifth embodiment of the present invention.
9 is a circuit diagram of a memory cell in the semiconductor device of FIG.
FIG. 10 is a schematic layout diagram of the memory cell array of FIG. 8;
11 is a timing chart schematically showing a state of a change in bit line potential in the semiconductor device of FIG. 8;
FIG. 12 is a schematic layout diagram showing a memory cell array in a semiconductor device according to a sixth embodiment of the present invention.
FIG. 13 is a schematic layout diagram showing a memory cell array in a semiconductor device according to a seventh embodiment of the present invention;
FIG. 14 is a schematic plan view showing a memory cell array in a semiconductor device according to an eighth embodiment of the present invention.
FIG. 15 is a schematic plan view showing a memory cell array in a semiconductor device according to a ninth embodiment of the present invention.
FIG. 16 is a schematic plan view showing a memory cell array in a semiconductor device according to a ninth embodiment of the present invention.
FIG. 17 is a schematic layout diagram showing a memory cell array in a semiconductor device according to a tenth embodiment of the present invention.
FIG. 18 is a schematic layout diagram showing a memory cell array in a semiconductor device according to an eleventh embodiment of the present invention.
FIG. 19 is a schematic plan view showing a memory cell array in a semiconductor device according to a twelfth embodiment of the present invention.
FIG. 20 is a circuit diagram of a memory cell in a conventional semiconductor memory device having a DRAM cell with a reduced waiting time;
[Explanation of symbols]
40, 60 bit line
41, 61 bit line
49, 62 Shield bit line

Claims (11)

A switching transistor connected to a source, and a memory cell including a storage capacitor for storing data connected to one of the electrodes connected to the source. A certain bit line is formed in a hierarchical structure composed of a metal wiring layer different from an adjacent bit line, and a shield bit line is provided in a vacant region above the bit line formed in the hierarchical structure. A semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein adjacent bit lines are arranged alternately. 3. The semiconductor memory device according to claim 1, wherein an empty area below the bit line is formed as a plate lining area. A plurality of memory cells each including a first switching transistor and a second switching transistor having sources connected to each other, and a storage capacitor for data storage having one electrode connected to the source;
A plurality of first bit lines, each of which is formed of a first layer metal wiring connected to the drain of the first switching transistor and is a data input / output line;
A plurality of data input / output lines each connected to a drain of the second switching transistor and formed of a second layer metal wiring alternately arranged in a hierarchical structure with the first bit line; A second bit line;
A semiconductor memory device comprising: 5. The semiconductor memory device according to claim 4, wherein the layers of the first bit line and the second bit line, which are adjacent data input / output lines, are alternately arranged. 6. The semiconductor memory device according to claim 4, wherein a shield bit line is provided in a vacant area above a bit line which is a data input / output line having a hierarchical structure. 7. The semiconductor memory device according to claim 4, wherein an empty area below the bit line is formed as a plate lining area. 5. The arrangement of a first bit line and a second bit line, which are data input / output lines formed using a hierarchical structure, are alternately arranged in units of sense amplifier columns. 13. The semiconductor memory device according to claim 1. 9. The semiconductor memory device according to claim 8, wherein the hierarchy of the first bit line and the second bit line, which are the input / output lines of adjacent data, are alternately arranged. 10. The semiconductor memory device according to claim 8, wherein a shield bit line is provided in a vacant area above a bit line which is a data input / output line having a hierarchical structure. 11. The semiconductor memory device according to claim 8, wherein an empty area below the bit line is configured as a plate lining area.

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