JP5068432B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to dynamic random access memory (DRAM) semiconductor devices, and more particularly to the placement of power and signal lines with stacked metal layers.

  The DRAM device includes a memory array, circuitry for accessing the memory array, and peripheral circuitry that controls DRAM operation and communicates with external devices. A general memory array is formed as a repeating pattern of sub memory cell arrays scattered between access circuits used for access. The rest of the access circuit typically includes a row decoder and a column decoder located at the edge of the memory array.

  FIG. 1 is a diagram showing a configuration of a general memory 100 including a memory array 10, a column decoder 20, and a row decoder 30. The memory array 10 is arranged in the same manner as a checker board, and the sub memory cell array (SMCA) is separated in the vertical direction by the sub word line driver (SWD), and is horizontally arranged by the memory cell sense amplifier (SA). To be separated. Each sub memory cell array includes a plurality of memory cells (MC). Each memory cell includes an access transistor enabled by a sub word line (SWL) and a capacitor for storing data. SAs are separated vertically by coupling regions (CJs) including SA control signal generation circuits.

  The column decoder 20 is a circuit that provides a signal on column selection lines (CSLs), and selects one or more columns of the array to be written or read according to the applied column address (CA).

  The row decoder 30 selects one of a plurality of main word line (NWE) and word line selection (PX) signals in response to the supplied row address, thereby selecting a memory cell in the corresponding row in the array. Activate.

  1 will be further described with reference to FIG. 2, which shows a portion of the array 10 of FIG. 1 in greater detail. Two memory cells (MC1, MC2) are shown in SMCA1 and SMCA2, respectively. Each memory cell includes a capacitor (C) connected between the cell plate voltage (Vp) and the source of the access transistor (N). In general, Vp has a value of ½ of the power supply voltage. The gate of each access transistor (N) is controlled by the corresponding sub word line (SWL). SWL1 controls the access transistor of MC1, and SWL2 controls the access transistor of MC2.

  The drain of each access transistor (N) is connected to a corresponding bit line (BL), for example, BL1 for MC1 and BL2 for MC2. Each bit line is connected to another memory cell (not shown) in each SMCA, and an access transistor (not shown) of the other memory cell is connected to another SWL.

  The sense amplifier region (SA1) exists between SMCA1 and SMCA2. BL1 and BL1B in SMCA1 are connected to a precharge circuit (PRE1) in SA1 and are connected to a pair of sense bit lines (SBL, SBLB) via a bit line isolation gate (ISO1). BL2 and BL2B of SMCA2 are connected to a precharge circuit (PRE2) in SA1 and connected to a pair of sense bit lines (SBL, SBLB) via a bit line isolation gate (ISO2). The bit line sense amplifier (BLSA) and the data input / output gate (IOG) are connected to the sense bit lines (SBL, SBLB).

  For example, the bit line sense amplifier amplifies a voltage difference between BL1 and BL1B of the memory cell MC1 in the following procedure. Memory cell MC1 displays one of two logic states (multiple memory cells also exist, in which case a more complex sense amplifier circuit is used). A bit line isolation gate (ISO1) connects BL1 to SBL and connects BL1B to SBLB.

  The precharge circuit (PRE1) has BL1 and BL1B as an intermediate voltage between the voltage of the discharge capacitor (C) (for example, indicating logic 0) and the voltage of the charging capacitor (C) (in this example, indicating logic 1) To charge. SWL1 is activated to connect the capacitor of memory cell MC1 to BL1. When the cell capacitor is discharged, the voltage of BL1 decreases compared to BL1B due to charge sharing. When the cell capacitor is charged, the voltage of BL1 increases compared to BL1B due to charge sharing. After the charge sharing is completed, the bit line isolation gate (ISO1) is enabled, and a slight voltage difference between the bit lines (BL1 / BL1B) is transmitted to the sense bit lines (SBL1 / SBL1B). In this case, the sense amplifier (BLSA) that senses and amplifies a slight voltage difference between the bit lines (BL1 / BL1B) is activated during a predetermined period.

  When the input / output gate (IOG) is activated, SBL and SBLB are connected to a pair of local input / output lines (LIO, LIOB). These lines (LIO, LIOB) are also connected to other IO gates in other SA regions (not shown) above and below SA1. Here, the input / output gate (IOG) is activated in response to a column selection line (CSL; not shown). The local global input / output gate (LGIOG) selectively connects the LIO and LIOB to a pair of global input / output lines (GIO, GIOB) when the LIO and LIOB are activated. Thus, the sensed memory cell state is provided to the peripheral input / output circuit.

  It can be seen from FIGS. 1 and 2 that many conductors (conductors) are routed (wired or arranged) through the memory array 10. NWE lines are routed vertically across the array through the sub-memory cell array, and PX, LIO and LIOB lines are routed vertically across the array via the coupling and sense amplifier regions. The CSL, GIO and GIOB lines are routed horizontally across the array through the sub-memory cell array. The power conductors that must be further routed through the array to power the circuits in the SA, CJ, and SWD regions are not shown.

  FIG. 3 is a diagram illustrating a memory array 10 region having a lower circuit whose details are omitted and metal lines arranged in a stacked manner. For the first metal layer, the LIO, PX and NWE lines are separated from the first power line (P1) that supplies power at different voltage levels required by the array circuit. Some power lines in the first power line (P1) may include a ground potential voltage line (VSS) and a power line (VCC), and other power lines in the first power line (P1). May include a reference voltage line (Vref), a negative power line (VBB), or a boosting voltage line (VPP). For the second metal layer, the CSL and GIO lines are separated from the second power line (P2) that supplies power at different voltage levels. Some power lines in the second power line (P2) may include a ground potential voltage line (VSS) and a power line (VCC), and other power lines in the second power line (P2). May include a reference voltage line (Vref), a negative power line (VBB), or a boosting voltage line (VPP). At the position where the P2 line intersects the P1 line of the same voltage level, the two lines are connected to each other to form a grid. The P2 line is connected to a power supply located outside the memory array area of the DRAM device.

  FIG. 4 is a simplified block diagram of the row decoder 30 of FIG. The row decoder 30 includes a row address decoder region 30-1 and a row address predecoder region 30-2. In the row address decoder area 30-1, each of the illustrated first decoder areas (RD1) generates a word line selection signal (PX), and each of the illustrated second decoder areas (RD2) is a row address. (RA) and a main word line signal (NWE) are generated in response to a predecoding row address (DRA) generated by the row address predecoder 30-2.

  FIG. 5 is a diagram showing a part of the row decoder 30 having a lower circuit whose details are omitted, and metal lines arranged in a stacked manner. When the first metal layer is stacked on the first decoder region (RD1), the first power line (PVINT1, PVSS1) is positioned on the side of the signal line (S1; for example, PX line). When the first metal layer is stacked on the second decoder region (RD2), the additional first power line (PVINT1, PVSS1) is positioned on the side of the signal line (S1; for example, NWE line). .

  The second metal layer includes a signal line (S2; for example, RA and DRA lines) and a second power line (PVINT2, PVSS2). PVINT2 is connected to PVINT1 at a portion intersecting with PVINT1, and PVSS2 is connected to PVSS1 at a portion intersecting with PVSS1. PVINT2 and PVSS2 are connected to a power supply located outside the memory array area of the DRAM device. In this state, the power line cannot be designed to be thicker because it increases the chip area.

  An object of the present invention is to provide, for example, a semiconductor memory device capable of stably supplying power without increasing the chip area, and a method of arranging the signal and the power line.

  In the current situation where the cell size of a DRAM device is becoming smaller or the number of cells in a memory array is increasing, the area is essentially the same as the area where a conventional small number of signal lines are routed. It is necessary to pass more signal lines over the memory array and the row decoder. Therefore, the power line width decreases in proportion to this. However, a reduction in power line width is preferable because reduced power line width increases resistance to current flow, voltage drop, and power consumption, and current fluctuations prevent stable power supply. Absent. The various signals and the power lines are close to each other as the size of the DRAM device is further reduced, and undesirable crosstalk is generated between adjacent lines.

  The embodiments described herein use a triple metal layer DRAM with significantly improved signal and power line routing compared to the double metal layer design. Various schemes have been proposed in addition to routing signals with a memory array using three metal layers, but this design solves this problem with particular emphasis on the power supply problem, so it is designed as the smallest cell. It is intended to provide a new metal layer arrangement in one group.

  In order to achieve the above object, a first embodiment of a semiconductor memory device according to the present invention includes repeated row / column pattern cell blocks each including a sub memory cell array, and a sense amplifier and a sub word line driver associated with the sub memory cell array. A memory cell array including first, second, and third patterned metal layers each including a plurality of lines disposed on the memory cell array, and a hole in one insulating layer in the insulating layer is a line. An insulating layer deposited around the patterned metal layer to substantially insulate the line, except for the portion provided to establish electrical contact, the first patterned The metal layer line has a plurality of substantially flat planes respectively coupled to a plurality of sense amplifiers in the cell blocks arranged in the row direction. A row of local input / output (I / O) lines, a plurality of first power lines arranged substantially parallel to the local I / O lines and supplying memory cell array power, and the local I / O lines A plurality of main word lines connected to a plurality of sub word line driving units in cell blocks arranged substantially in parallel and arranged in the row direction, and the second patterned metal layer line Includes a plurality of substantially parallel column select lines each connected to input / output gates in the cell block, wherein the third patterned metal layer line includes a plurality of third power lines. The memory cell array power is supplied, and a line in at least one of the second and third patterned metal layers is selected by the column selection. A plurality of global I / O lines arranged substantially parallel to the IN, each global I / O line being connected to the plurality of cell blocks to selectively select the plurality of local I / O lines. It is characterized by multiplexing.

  The third power line may be substantially parallel to the column selection line, and the second patterned metal layer line further includes a plurality of second power lines to supply the memory cell array power. The second power line may be substantially parallel to the column selection line, and each of the third power lines may be associated with a corresponding one of the second power lines. The third power lines may overlap and be connected to the power line, and each of the third power lines may have a width substantially larger than a width of the lower second power line, and the global I / O line All may be present in the third patterned metal layer.

  The third power line may be disposed substantially perpendicular to the column selection line, and the second patterned metal layer line may further include a plurality of second power lines. And the second power line may be disposed substantially parallel to the column selection line, and at least one of the third power lines may be connected to the third power line. It may be connected to at least one of the second power lines at an intersection between the lower second power line and at least one of the third power lines is Substantially overlaps with and can be connected to a corresponding one of the first power lines, At least one line may have a substantially greater width than the width of the lower portion of the first power line.

  And further including a column decoder located around the memory cell array and connected to at least a part of the column selection lines, wherein at least a part of the global I / O lines are connected to the column. A third patterned metal layer may be routed across the decoder, and at least some of the global I / O lines are third patterned across the memory array. Or at least some lines in the global I / O lines are routed with a second patterned metal layer that traverses the memory array. Can be done.

  All of the global I / O lines may be disposed in the second patterned metal layer, and the second patterned metal layer line further includes a plurality of second power lines. Cell array power may be supplied, the plurality of second power lines may be disposed substantially parallel to the column selection line, and the plurality of third power lines may be substantially parallel to the column selection line. The at least one third power line substantially overlaps a corresponding one of the first power lines and is connected to the first power line. The connection between the at least one third power line substantially overlapping with a corresponding one of the first power lines may be connected to the at least one third power line. One of the corresponding said first power line Rain can be present in the vias directly connected.

  In order to achieve the above object, a second embodiment of the semiconductor memory device of the present invention includes a sub memory cell array, a cell block having a repeated row / column pattern, a sense amplifier and a sub word line drive associated with the sub memory cell array. A memory cell array including a portion, first, second, and third patterned metal layers that are disposed on the memory cell array and each include a plurality of lines, and a hole in one insulating layer of the insulating layers An insulating layer deposited around the patterned metal layer to substantially insulate the line, except for a portion that is provided to establish electrical contact with the line. The patterned metal layer lines are coupled to a plurality of sense amplifiers in the cell blocks arranged in the row direction. Substantially parallel local input / output (I / O) lines and the plurality of sub-wordline drivers in a cell block arranged substantially parallel to the local I / O lines and arranged in a row direction A plurality of main word lines connected to each other, wherein the second patterned metal layer lines are connected to a plurality of substantially parallel columns respectively connected to input / output gates arranged in the cell block. A plurality of second power lines arranged substantially parallel to the column selection lines and supplying memory cell array power; and arranged substantially parallel to the column selection lines; A plurality of global I / O lines connected to selectively multiplex a plurality of local I / O lines; Grayed metal layer line, and supplying said memory cell array power include a plurality of third power line.

  The third power line may be disposed substantially parallel to the column selection line, and each third power line overlaps with a corresponding one of the second power lines, and , Each third power line may have a width substantially larger than a width of the second power line below.

  The first patterned metal layer line may further include a plurality of first power lines to supply the memory cell array power, or the third power line may be substantially connected to the column selection line. Can be arranged vertically. At least one line in the third power line may overlap with and be connected to a corresponding line in the first power line.

  In order to achieve the above object, a third embodiment of the semiconductor memory device of the present invention is a cell block having repeated row / column patterns each including a sub memory cell array, and a sense amplifying unit and a sub word line driving unit related to the sub memory cell array. A memory cell array including first, second, and third patterned metal layers that are disposed on the memory cell array and each include a plurality of lines, and a hole in one insulating layer of the insulating layer is a line. An insulating layer deposited around the patterned metal layer to substantially insulate the line, except for the portion provided to establish electrical contact with the first patterned layer. The metal layer line is connected to a plurality of sense amplifiers in the cell block arranged in the row direction. A local input / output (I / O) line parallel to the first I / O line, a plurality of first power lines disposed substantially parallel to the local I / O line to supply memory cell array power, and the local I / O A plurality of main word lines connected to a plurality of sub word line driving units in cell blocks arranged in a row direction and arranged substantially in parallel with the lines, and the second patterned metal The layer lines are arranged in parallel to the plurality of substantially parallel column selection lines respectively connected to the input / output gates arranged in the cell block, and substantially parallel to the column selection lines. A plurality of second power lines to be supplied and a plurality of the plurality of second power lines arranged substantially parallel to the column selection line and connected to the plurality of cell blocks A plurality of global I / O lines that selectively multiplex local I / O lines, and wherein the third patterned metal layer line includes a plurality of third power lines to increase the memory cell array power. Each of the third power lines is overlapped with a corresponding one of the second power lines and has a width larger than that of the lower second power line.

  In order to achieve the above object, a fourth embodiment of the semiconductor memory device of the present invention is a cell block having repeated row / column patterns each including a sub memory cell array, and a sense amplifier and a sub word line driver associated with the sub memory cell array. A memory cell array including: first, second and third patterned metal layers disposed on the memory cell array, each including a plurality of lines; and a hole in one insulating layer in the insulating layer is a line. An insulating layer deposited around the patterned metal layer to substantially insulate the line, except for the portion provided to establish electrical contact, and the first patterned metal The layer line is formed by a plurality of substantially flat planes respectively coupled to a plurality of sense amplifiers in the cell blocks arranged in the row direction. A row of local input / output (I / O) lines, a plurality of first power lines disposed substantially parallel to the local I / O lines to supply memory cell array power, and the local I / O lines The second patterned metal layer line includes a plurality of main word lines respectively connected to a plurality of sub word line driving units in the cell blocks arranged in the row direction. The memory cell array power is supplied including a plurality of second power lines, and the third patterned metal layer lines are respectively coupled to a plurality of sense amplifiers in the cell blocks arranged in the column direction. Substantially parallel column select lines and a plurality of substantially parallel columns connected to input / output gates arranged in the cell block, respectively. Select lines, a plurality of second power lines arranged substantially parallel to the column select lines to supply the memory cell array power, and a plurality of cells arranged substantially parallel to the column select lines. And a plurality of global I / O lines that are connected to the block and selectively multiplex the plurality of local I / O lines.

  In order to achieve the above object, according to a fifth embodiment of the semiconductor memory device of the present invention, a row decoder for generating a plurality of main word lines, and a first decoder and a second decoder each including a plurality of lines disposed on the row decoder. And a third patterned metal layer and deposited around the patterned metal layer, except for the portion provided with holes in the insulating layer to establish electrical contact with the line. An insulating layer that substantially insulates, wherein the first patterned metal layer line is substantially parallel to the first signal line and a plurality of first signal lines connected to a predetermined control circuit, respectively. A plurality of first power lines disposed and providing power, wherein the second patterned metal layer line is arranged in a plurality of real lines arranged substantially perpendicular to the first signal line. The third patterned metal layer line includes a plurality of third power lines to supply power, and the third power line includes the second signal line. Are arranged substantially parallel to each other and so as to substantially overlap at least a part of the second signal lines.

  A memory cell array adjacent to the row decoder, wherein at least some of the power lines in the first power line can supply power to the memory cell array; And at least a part of the third power line may supply power to the memory cell array, and the second metal layer line may further include a plurality of second power lines to supply power. The second power line may be disposed substantially parallel to the second signal line, and each of the second power lines may have a substantially narrower width than the third power line. . At least one power line in the third power line may substantially overlap with at least one power line in the second power line, and at least one power line in the first power line. May be disposed across the central half of each row decoder cell, and at least one power line in the first power line may traverse each central half of the row decoder cell. Can be arranged.

  In order to achieve the above object, according to a sixth embodiment of the semiconductor memory device of the present invention, a row decoder including a row decoder cell and first, second, and third elements disposed on the row decoder and including a plurality of lines, respectively. Except for the patterned metal layer and portions where holes in the insulating layer are provided to establish electrical contact with the line, and are deposited around the patterned metal layer to substantially define the line. The first patterned metal layer line includes an insulating layer to be insulated, and the first patterned metal layer line is disposed substantially parallel to the first signal line and a plurality of first signal lines respectively connected to corresponding decoder cells. A plurality of first power lines for supplying power, wherein the second patterned metal layer line is arranged in a plurality of real lines arranged substantially perpendicular to the first signal line. A third patterned metal layer comprising: a second signal line qualitatively parallel; and a plurality of second power lines disposed substantially parallel to the second signal line for supplying power. The line includes a plurality of third power lines to supply power, wherein the third power line is substantially parallel to the second signal line and within the second signal line and the second power line. It is characterized by being arranged so as to substantially overlap at least a part of the lines.

  Over each of the decoder cells, one power line in the first power line supplies an internal operating voltage, and the other power line in the first power line supplies a ground voltage. The first power line supplying the internal operating voltage and the first power line supplying the ground voltage are arranged adjacent to each other over each of the decoder cells, and are at least one of the first signal lines. One signal line is placed on the decoder cell and outside the first power line supplying the internal operating voltage, and at least one other signal line in the first signal line is the first power line. Each of the decoder cells can be disposed on the decoder cell and outside the first power line supplying the ground voltage. And at least two signal lines among the first signal lines are disposed adjacent to each other, the first power line supplies an internal operating voltage, and is disposed outside the signal lines on one side. One power line provides ground voltage and can be placed outside these signal lines on the other side.

  In order to achieve the above object, a seventh embodiment of the semiconductor memory device of the present invention includes a memory cell array, a column decoder arranged around the memory cell array, and a plurality of lines arranged across the column decoder. Except for the first, second and third patterned metal layers each including a portion where holes in one insulating layer of the insulating layer are provided to establish electrical contact with the line, An insulating layer deposited around the patterned metal layer to substantially insulate the line, wherein the third patterned metal layer line includes a plurality of global I connected to the memory cell array. / O line is included.

  The global I / O line is routed to a second patterned metal layer line on the memory cell array connected to each of the third patterned metal layer global I / O lines on the column decoder. The global I / O lines of the third patterned metal layer can be routed onto the memory cell array as lines of the third patterned metal layer.

  According to a first aspect of the present invention, there is provided a method for arranging a semiconductor memory device in which a primary power line is formed of a third metal layer, and the first metal layer and the second metal layer are formed. Connecting the primary power line to a narrower secondary power line with at least one metal layer, and forming local I / O lines and word lines with the first metal layer. It is characterized by including.

  The method may further include forming a column selection line with the second metal layer, and may further include forming a global I / O line with the second metal layer. The method may further include forming a global I / O line.

  According to a second aspect of the present invention, there is provided a semiconductor memory device arrangement method comprising: forming a primary power line from a third metal layer; and Connecting the primary power line to a narrower secondary power line with at least one metal layer and forming a signal line with the first and second metal layers. And

  The following embodiments use three metal layers for the memory array, row decoder and / or column decoder. In general, these embodiments can increase the width of the power line to improve power distribution and safety. Various advantages of these embodiments will be apparent from the following description with reference to the drawings.

  FIG. 6 is a diagram illustrating a first embodiment of signals and power lines routed (wired or placed) on a memory array using three metal layers. The first metal layer includes NWE, PX, LIO signal lines, and P1 power lines as in the prior art. The second metal layer includes CSL and GIO signal lines, but does not include power lines. The third metal layer includes a P3 power line that passes in a direction perpendicular to the P1 power line on which the first metal layer is formed. The P3 power line can be formed wider than the conventional P2 power line on which the second metal layer is formed. The reason is that the CSL and GIO lines are not disposed in the third metal layer region that is configured to overlap the memory array. For simplicity, this feature was not shown in FIG. 6, but the P3 line portion could be placed directly over the CSL and GIO lines. The part where the P3 power line intersects with the P1 power line transferring the same voltage (in this specification, the intersection means that two or more lines passing through different layers intersect each other in a plan view) There is a connection for connecting the P3 power line and the P1 power line. This connection may be connected to the first metal using via contacts (direct connection between the third metal and the first metal) or an intermediate P2 pad (not shown). Thus, the P3 line can be routed to provide reduced resistance and improved power distribution. The spacing between the CSL and GIO lines can be improved by the removal of the P2 line, reducing crosstalk and increasing the signal propagation speed.

  FIG. 7 is a diagram illustrating a second embodiment of signals and power lines routed over a memory array using three metal layers. In this embodiment, P1 is not present on the first metal layer, and the P2 line parallel to CSL and GIO on the second metal layer distributes power to the memory array circuit. The P3 line is arranged in the third metal layer so as to be orthogonal to the P2 line at a portion intersecting with the P2 line having the same voltage level (crossing at right angles) and connected to the P2 line. The P2 line is relatively narrow, while the P3 line is relatively wide so that current can be efficiently transmitted where it is needed.

  FIG. 8 illustrates a third embodiment of signal and power lines routed over a memory array using three metal layers. In this embodiment, the narrow P1 power line intersects the narrow P2 power line. The P1 and P2 lines at the same voltage level are connected at the intersection of them. The wider P3 line is routed parallel to the P2 line and generally overlaps the P2 line at the same voltage level. Where the P3 and P2 lines overlap along their length along the direction, the connection between these two lines can be formed with a long channel or with a plurality of abbreviated vias. The P3 / P2 structure contributes to a reduction in resistance per unit length while occupying the least space on the metal layer shared by CSL and GIO.

  FIG. 9 is a diagram illustrating a fourth embodiment of signal and power lines routed over a memory array using three metal layers. In this embodiment, the first metal layer includes a narrow P1 power line that is routed parallel to the NWE line. The second metal layer includes a narrow P2 power line that is perpendicular to the P1 power line and routed parallel to the CSL and GIO lines. The two power lines are connected to each other at the portion where the P2 power line intersects the P1 power line at the same voltage level. The third metal layer includes a relatively wide P3 power line parallel to the P1 power line, and the P3 power line is preferably routed to overlap the lower P1 line at the same voltage level. The two power lines are connected to each other at the portion where the P3 power line intersects the P2 line having the same voltage level.

  FIG. 10 is a diagram illustrating a fifth embodiment of signals and power lines routed over a memory array using three metal layers. This embodiment is similar to the third embodiment (FIG. 8), but the GIO lines are routed on the third metal layer instead of the second metal layer. This embodiment functions as a single conductor with all of the overlapping P2 and P3 lines having a reduced resistance, reducing the width of P3 and creating space for placing signal lines on the third metal layer. be able to. Therefore, the line width (pitch) between the CSLs becomes larger, and the coupling noise can be reduced.

  As an application example of the above-described embodiment, various embodiments for routing signals and power lines arranged in the row decoder will be described below.

  FIG. 11 is a diagram illustrating a first embodiment of the row decoder. Relatively narrow power lines (PVINT1, PVSS1) are disposed on the first metal layer to supply power to the lower row decoder circuit. For example, the PVINT1 and PVSS1 power lines may be provided on both sides of the row decoder region (RD1) while leaving an internal section on the row decoder region (RD1) to place the signal line (S1) in the first metal layer. outboard area) from the top to the bottom. Another row decoder signal line (S2) is disposed in the second metal layer while proceeding perpendicular to the PVINT1, PVSS1, and S1 lines. As the third metal layer, relatively wide power lines (PVINT3, PVSS3) run parallel to the S2 line, and each of the PVINT3 and PVSS3 overlaps one or more signal lines (S2). The connection between the two power lines is made in a portion where PVINT3 overlaps PVINT1 but does not overlap S2. Similarly, PVSS3 overlaps PVSS1, but connection between two power lines is made at a portion not overlapping S2. This connection may include a via partially filled with metal from the second metal layer, but there is no continuous second metal layer power line in this embodiment. This connection can be made directly between the third metal layer and the first metal layer. This arrangement uses extra space on the second metal layer to increase the number of lines (S2) and also has a third metal having a larger cross section than the power lines of the second metal layer of the prior art. Distribute power through the layer power lines.

  FIG. 12 is similar to FIG. 11, but a second embodiment of a row decoder using additional power lines (PVINT2, PVSS2) on a second metal layer running parallel to and outside the signal line (S2). FIG. Where PVINT2 overlaps PVINT1, a connection is made between the two power lines, and a similar connection is made between PVSS2 and PVSS1. PVINT3 overlaps PVINT2 (and may overlap one or more signal lines (S3)), and the connection between PVINT3 and PVINT2 is made at the portion where the two lines overlap. This connection is also an extended channel or a series of vias spaced apart from each other along the length of PVINT3 and PVINT2. Similar arrangements and connections exist between PVSS3 and PVSS2.

  FIG. 13 is a diagram showing a third embodiment of a row decoder similar to FIG. PVINT1 and PVSS1 are arranged in the center on the row decoder area (RD1), and the signal line (S1) is arranged outside PVINT1 and PVSS1. Here, PVINT2 and PVSS2 are not present on the second metal layer.

  FIG. 14 shows a fourth row decoder embodiment similar to FIG. PVINT1 and PVSS1 are arranged on the row decoder area (RD1), and the signal line (S1) is arranged outside PVINT1 and PVSS1. Here, PVINT2 and PVSS2 exist in the second metal layer having the signal line (S2).

  As an application example of the above-described embodiment, various embodiments for routing signals and power lines arranged in a column decoder will be described below.

  FIG. 15 is a diagram illustrating an embodiment of a first column decoder useful for the embodiment of FIG. 10 having, for example, GIO lines located in a third metal layer. The column decoder 20 ′ includes a signal line (S1) and a power line (PVINT1, PVSS1) arranged in the first metal layer, and a signal line (S2) and a power line arranged in the second metal layer on the first metal layer. (PVINT2, PVSS2) is used. However, in the third metal layer, the GIO line of the third metal layer arranged in the memory array (and the optional second metal layer power line (not shown) for supplying power to the memory array) is connected to the column decoder. Via the peripheral I / O circuit (not shown).

  FIG. 16 shows a second column decoder embodiment similar to FIG. The GIO line is routed through the column decoder by the third metal layer. However, after passing through the column decoder, each GIO line is connected via a via to the GIO line of the second metal layer on the memory array, for example, as shown in FIGS.

  One skilled in the art will recognize that various routing variations are possible within the general scope of the embodiments described above. These embodiments generally do not describe the established line widths and spacings because the devices and processes and the required functions are involved. Details of such minimal variations and implementation methods are within the scope of the claims included within the embodiments of the present invention.

FIG. 2 illustrates a conventional memory array and row / column decoder arrangement for a DRAM memory device. FIG. 2 is an enlarged view of a part of the memory array of FIG. FIG. 2 is an enlarged view of a part of the memory array of FIG. 1, focusing on signal and power line routing layouts for two metal layers stacked with the memory array. FIG. 2 is an enlarged view of a part of the row decoder of FIG. 1 to show details of additional circuits and signal lines. FIG. 2 is an enlarged view of a part of the row decoder in FIG. 1 to focus on signal and power line routing layouts for two metal layers in which row decoders are stacked. 1 is a diagram illustrating a first embodiment for a signal and power line composed of triple metal layers routed by a memory array; FIG. FIG. 6 shows a second embodiment for a signal and power line composed of triple metal layers routed by a memory array. FIG. 6 shows a third embodiment for signals and power lines composed of triple metal layers routed by a memory array. FIG. 10 is a diagram illustrating a fourth embodiment for a signal and power line composed of triple metal layers routed by a memory array. FIG. 10 shows a fifth embodiment for signals and power lines composed of triple metal layers routed by a memory array. It is a figure which shows 1st Embodiment with respect to the signal and power line which are comprised by the triple metal layer routed by the row decoder. It is a figure which shows 2nd Embodiment with respect to the signal and power line which are comprised by the triple metal layer routed by the row decoder. It is a figure which shows 3rd Embodiment with respect to the signal and power line which are comprised by the triple metal layer routed by the row decoder. FIG. 10 is a diagram showing a fourth embodiment for a signal and power line composed of triple metal layers routed by a row decoder. It is a figure which shows 1st Embodiment with respect to the signal and power line which are comprised by the triple metal layer routed by the column decoder. It is a figure which shows 2nd Embodiment with respect to the signal and power line which are comprised by the triple metal layer routed by the column decoder.

Explanation of symbols

10: Memory array 20, 20 ': Column decoder 30: Row decoder 100: Memory array

Claims (38)

Repeated row / column pattern cell blocks each including a sub memory cell array, and a memory cell array including a sense amplifier and a sub word line driver associated with the sub memory cell array;
First, second and third patterned metal layers disposed on the memory cell array, each including a plurality of lines;
An insulating layer that is deposited around the patterned metal layer to insulate the line, except for the portion of the insulating layer in which a hole in one insulating layer is provided to establish electrical contact with the line; Including,
The first patterned metal layer line is
A plurality of parallel local input / output (I / O) lines arranged in the row direction and respectively coupled to a plurality of sense amplifiers in the cell block;
A plurality of first power lines arranged in parallel to the local I / O lines and supplying memory cell array power;
A plurality of main word lines connected in parallel to the local I / O lines and connected to a plurality of sub word line driving units in the cell blocks arranged in the row direction,
The second patterned metal layer line includes a plurality of parallel column select lines each connected to an input / output gate in the cell block;
The third patterned metal layer line includes a plurality of third power lines and supplies memory cell array power;
The lines in at least one metal layer in the second and third patterned metal layers further include a plurality of global I / O lines arranged in parallel with the column selection lines, and each global I / O A line is connected to the plurality of cell blocks to selectively multiplex the plurality of local I / O lines;
The third power line has a portion that overlaps at least one of the plurality of first power lines, and is connected to the overlapping first power line at the overlapping portion. apparatus.   The semiconductor dynamic random access memory device of claim 1, wherein the third power line is parallel to the column selection line.   The second patterned metal layer line further includes a plurality of second power lines for supplying the memory cell array power, and the second power line is parallel to the column selection line. The semiconductor dynamic random access memory device according to claim 2.   4. The semiconductor dynamic random access according to claim 3, wherein each of the third power lines overlaps with and is connected to a corresponding one of the second power lines. Memory device.   5. The semiconductor dynamic random access memory device according to claim 4, wherein each of the third power lines has a width larger than a width of the lower second power line.   The semiconductor dynamic random access memory device of claim 4, wherein all of the global I / O lines are present in the third patterned metal layer.   The semiconductor dynamic random access memory device of claim 1, wherein the third power line is disposed perpendicular to the column selection line.   The second patterned metal layer line further includes a plurality of second power lines to supply the memory cell array power, and the second power line is disposed in parallel with the column selection line. 8. The semiconductor dynamic random access memory device according to claim 7, wherein:   At least one of the third power lines is connected to at least one of the second power lines at an intersection between the third power line and a lower second power line. 9. The semiconductor dynamic random access memory device according to claim 8, wherein:   8. The semiconductor device according to claim 7, wherein at least one line in the third power line overlaps with and is connected to a corresponding one line in the first power line. Dynamic random access memory device.   11. The semiconductor dynamic random access memory device according to claim 10, wherein at least one of the third power lines has a width larger than a width of the lower first power line.   A column decoder disposed around the memory cell array and connected to at least some of the column selection lines, wherein at least some of the global I / O lines are connected to the column decoder; The semiconductor dynamic random access memory device according to claim 1, wherein the semiconductor dynamic random access memory device is routed with the third patterned metal layer while traversing the substrate.   13. The semiconductor dynamic random of claim 12, wherein at least some of the global I / O lines are routed with the third patterned metal layer across the memory array. Access memory device.   13. The semiconductor of claim 12, wherein at least some of the global I / O lines are routed with the second patterned metal layer that traverses the memory array. Dynamic random access memory device.   The semiconductor dynamic random access memory device according to claim 1, wherein all of the global I / O lines are disposed in the second patterned metal layer.   The second patterned metal layer line further includes a plurality of second power lines to supply the memory cell array power, and the plurality of second power lines are disposed in parallel with the column selection line. The semiconductor dynamic random access memory device according to claim 15.   The semiconductor dynamic random access memory device of claim 16, wherein the plurality of third power lines are disposed perpendicular to the column selection line.   18. The semiconductor dynamic random access memory according to claim 17, wherein the at least one third power line overlaps with a corresponding one of the first power lines and is connected to the first power line. apparatus.   The connection between the corresponding one of the first power lines and the at least one third power line overlapping therewith directly connects the at least one third power line with the corresponding one of the first power lines. 19. The semiconductor dynamic random access memory device according to claim 18, wherein the semiconductor dynamic random access memory device is present in a via connected to the semiconductor dynamic random access memory. Each including a sub-memory cell array, a cell block having a repeated row / column pattern, and a memory cell array including a sense amplifier and a sub-word line driving unit related to the sub-memory cell array;
First, second and third patterned metal layers disposed on the memory cell array, each including a plurality of lines;
Insulation that is deposited around the patterned metal layer to insulate the line, except for the portion of the insulating layer where holes in one insulating layer are provided to establish electrical contact with the line. A layer, and
The first patterned metal layer line is:
A plurality of parallel local input / output (I / O) lines each coupled to a plurality of sense amplifiers in the cell blocks arranged in the row direction;
A plurality of main word lines connected in parallel to the local I / O lines and connected to the plurality of sub word line driving units in the cell blocks arranged in the row direction,
The second patterned metal layer line is
A plurality of parallel column select lines respectively connected to input / output gates arranged in the cell block;
A plurality of second power lines disposed in parallel to the column selection lines and supplying memory cell array power;
A plurality of global I / O lines arranged in parallel to the column selection lines and connected to the plurality of cell blocks to selectively multiplex a plurality of local I / O lines;
The third patterned metal layer line includes a plurality of third power lines, and supplies the memory cell array power.
The third power line has a portion overlapping at least one of the plurality of second power lines, and is connected to the overlapping second power line at the overlapping portion. apparatus.   21. The semiconductor dynamic random access memory device according to claim 20, wherein the third power line is disposed in parallel with the column selection line.   The semiconductor dynamic random access memory device of claim 21, wherein each third power line overlaps with and is connected to a corresponding one of the second power lines.   23. The semiconductor dynamic random access memory device of claim 22, wherein each of the third power lines has a width that is greater than a width of the lower second power line.   21. The semiconductor dynamic random access memory device of claim 20, wherein the first patterned metal layer line further includes a plurality of first power lines and supplies the memory cell array power.   21. The semiconductor dynamic random access memory device according to claim 20, wherein the third power line is disposed perpendicular to the column selection line.   26. The semiconductor device of claim 25, wherein at least one line of the third power line overlaps with and is connected to a corresponding one of the first power lines. Dynamic random access memory device. Repeated row / column pattern cell blocks each including a sub memory cell array, and a memory cell array including a sense amplifier and a sub word line driver associated with the sub memory cell array;
First, second and third patterned metal layers disposed on the memory cell array, each including a plurality of lines;
An insulating layer that is deposited around the patterned metal layer to insulate the line, except for the portion of the insulating layer where holes in one insulating layer are provided to establish electrical contact with the line. And including
The first patterned metal layer line is:
A plurality of parallel local input / output (I / O) lines respectively coupled to a plurality of sense amplifiers in the cell blocks arranged in the row direction;
A plurality of first power lines disposed in parallel to the local I / O lines to supply memory cell array power;
A plurality of main word lines connected in parallel to the local I / O lines and respectively connected to a plurality of sub word line driving units in a cell block arranged in the row direction,
The second patterned metal layer line is
A plurality of parallel column select lines respectively connected to input / output gates arranged in the cell block;
A plurality of second power lines arranged in parallel to the column selection lines to supply the memory cell array power;
A plurality of global I / O lines arranged in parallel to the column selection lines and connected to the plurality of cell blocks to selectively multiplex the plurality of local I / O lines;
The third patterned metal layer line includes a plurality of third power lines and supplies the memory cell array power, and each of the third power lines corresponds to one corresponding line in the second power line. A semiconductor dynamic random access memory device characterized by having a width larger than that of the lower second power line connected to the corresponding one line at the overlapping portion. A row decoder for generating a plurality of main word lines;
First, second and third patterned metal layers disposed on the row decoder and each including a plurality of lines;
An insulating layer that is deposited around the patterned metal layer to insulate the line, except for the portion where holes in the insulating layer are provided to establish electrical contact with the line;
The first patterned metal layer line is:
A plurality of first signal lines each connected to a predetermined control circuit;
A plurality of first power lines arranged in parallel to the first signal lines for supplying power;
The second patterned metal layer line is
A plurality of parallel second signal lines arranged perpendicular to the first signal lines;
The third patterned metal layer line is:
A plurality of third power lines are provided to supply power, and the third power line is arranged in parallel to the second signal line and overlapping at least a part of the second signal lines. A semiconductor dynamic random access memory device comprising portions overlapping each line of the plurality of first power lines, wherein each portion is connected to each line.   30. The semiconductor dynamic random number according to claim 28, further comprising a memory cell array adjacent to the row decoder, wherein at least some of the power lines in the first power line supply power to the memory cell array. Access memory device.   30. The semiconductor dynamic memory according to claim 28, further comprising a memory cell array adjacent to the row decoder, wherein at least some of the power lines in the third power line supply power to the memory cell array. Random access memory device.   The second metal layer line further includes a plurality of second power lines to supply power, and the second power lines are disposed in parallel to the second signal lines, and each of the second power lines is 30. The semiconductor dynamic random access memory device according to claim 28, wherein the semiconductor dynamic random access memory device has a narrower width than the third power line.   32. The semiconductor dynamic random access memory device of claim 31, wherein at least one power line in the third power line overlaps with at least one power line in the second power line.   32. The semiconductor dynamic random access memory device of claim 31, wherein at least one of the first power lines is disposed across the center half of each row decoder cell.   30. The semiconductor dynamic random access memory device of claim 28, wherein at least one power line of the first power lines is disposed across a central half of each row decoder cell. A row decoder including row decoder cells;
First, second and third patterned metal layers disposed on the row decoder and each including a plurality of lines;
Except for the portion provided in the insulating layer where holes are provided to establish electrical contact with the line, including an insulating layer deposited around the patterned metal layer to insulate the line;
The first patterned metal layer line is:
A plurality of first signal lines respectively connected to corresponding decoder cells;
A plurality of first power lines arranged in parallel to the first signal lines and supplying power;
The second patterned metal layer line is
A plurality of parallel second signal lines arranged perpendicular to the first signal lines;
A plurality of second power lines arranged in parallel to the second signal lines and supplying power;
The third patterned metal layer line is:
A plurality of third power lines for supplying power, wherein the third power line is parallel to the second signal line and at least a part of the second signal line and the second power line; A semiconductor dynamic random access memory device, wherein the semiconductor dynamic random access memory device is arranged so as to overlap and is connected to the partial line of the second power line at a portion overlapping the at least partial line of the second power line.   One power line of the first power lines supplies an internal operating voltage to each of the decoder cells, and another power line of the first power lines supplies a ground voltage. 36. The semiconductor dynamic random access memory device according to claim 35.   In each of the decoder cells, a first power line that supplies the internal operating voltage and a first power line that supplies the ground voltage are arranged adjacent to each other, and at least one signal in the first signal line. A line is placed on the decoder cell and outside the first power line supplying the internal operating voltage, and at least one other signal line in the first signal line is connected to the decoder cell. 37. The semiconductor dynamic random access memory device according to claim 36, wherein the semiconductor dynamic random access memory device is disposed outside the first power line that supplies the ground voltage.   In each of the decoder cells, at least two signal lines of the first signal line are disposed adjacent to each other, the first power line supplies an internal operating voltage, and one of these signal lines 37. The semiconductor dynamic random access memory device according to claim 36, wherein the first power line supplies a ground voltage and is arranged outside the other of the signal lines.

Images