TW200614258A - Semiconductor memory device and method of arranging signal and power lines thereof - Google Patents

Semiconductor memory device and method of arranging signal and power lines thereof

Info

Publication number
TW200614258A
TW200614258A TW094118121A TW94118121A TW200614258A TW 200614258 A TW200614258 A TW 200614258A TW 094118121 A TW094118121 A TW 094118121A TW 94118121 A TW94118121 A TW 94118121A TW 200614258 A TW200614258 A TW 200614258A
Authority
TW
Taiwan
Prior art keywords
memory device
semiconductor memory
power lines
sdram
conductors
Prior art date
Application number
TW094118121A
Other languages
Chinese (zh)
Other versions
TWI286325B (en
Inventor
Jae-Young Lee
Hyuk-Joon Kwon
Chi-Wook Kim
Sung-Hoon Kim
Youn-Sik Park
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040074730A external-priority patent/KR100689814B1/en
Priority claimed from US11/134,855 external-priority patent/US7161823B2/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200614258A publication Critical patent/TW200614258A/en
Application granted granted Critical
Publication of TWI286325B publication Critical patent/TWI286325B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Method and apparatus for use, e.g., with Synchronous Dynamic Random Access Memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.
TW094118121A 2004-06-03 2005-06-02 Semiconductor memory device and method of arranging signal and power lines thereof TWI286325B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR20040040542 2004-06-03
KR1020040074730A KR100689814B1 (en) 2004-06-03 2004-09-17 Semiconductor memory device and method of arranging signal and power lines thereof
US11/134,855 US7161823B2 (en) 2004-06-03 2005-05-19 Semiconductor memory device and method of arranging signal and power lines thereof

Publications (2)

Publication Number Publication Date
TW200614258A true TW200614258A (en) 2006-05-01
TWI286325B TWI286325B (en) 2007-09-01

Family

ID=35499786

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094118121A TWI286325B (en) 2004-06-03 2005-06-02 Semiconductor memory device and method of arranging signal and power lines thereof

Country Status (3)

Country Link
JP (1) JP5068432B2 (en)
DE (1) DE102005026637A1 (en)
TW (1) TWI286325B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102601866B1 (en) * 2019-01-16 2023-11-15 에스케이하이닉스 주식회사 Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3374967B2 (en) * 1998-10-26 2003-02-10 日本電気株式会社 Semiconductor integrated circuit
JP2001067863A (en) * 1999-08-31 2001-03-16 Mitsubishi Electric Corp Semiconductor storage

Also Published As

Publication number Publication date
DE102005026637A1 (en) 2006-01-12
TWI286325B (en) 2007-09-01
JP2005347754A (en) 2005-12-15
JP5068432B2 (en) 2012-11-07

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