KR100701674B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR100701674B1 KR100701674B1 KR1020010081676A KR20010081676A KR100701674B1 KR 100701674 B1 KR100701674 B1 KR 100701674B1 KR 1020010081676 A KR1020010081676 A KR 1020010081676A KR 20010081676 A KR20010081676 A KR 20010081676A KR 100701674 B1 KR100701674 B1 KR 100701674B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 다수의 비아홀이 패터닝된 기판을 준비하는 단계; 상기 다수의 비아홀을 매립하는 두께로 상기 기판상에 BARC (bottom anti-reflective coating)를 형성하는 단계; 및 상기 BARC를 화학적 기계적 연마 공정으로 일부 제거하여 평탄화하는 단계를 포함하는 것이며, BARC 충전(filling) 이후에 트렌치 포토(trench photo) 공정시 레지스트 두께의 균일성(resist thickness uniformity)으로 인해 트렌치 포토 공정의 임계치수 균일성이 향상되는 탁월한 효과가 있으며, 별도의 장비 필요 없이 단순한 BARC 공정만으로도 미세한 다마신 트렌치 패턴이 가능하며, 단순화된 안정적 공정 제어로 인하여 소자 개발이 용이하며 생산 수율도 향상되는 효과가 있는 것이다.The present invention relates to a method for manufacturing a semiconductor device, comprising: preparing a substrate on which a plurality of via holes are patterned; Forming a bottom anti-reflective coating (BARC) on the substrate with a thickness filling the plurality of via holes; And partially removing the BARC by a chemical mechanical polishing process to planarize the trench, and a trench photo process due to resist thickness uniformity during the trench photo process after BARC filling. It has an excellent effect of improving the uniformity of critical dimension, and it is possible to make fine damascene trench pattern by simple BARC process without the need of additional equipment, and it is easy to develop devices and improve the production yield by simplified stable process control. It is.
Description
도 1 및 도 2는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도.1 and 2 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10: 기판 10: Substrate
20: 비아홀20: Via Hole
30,30a: BARC (bottom anti-reflective coating)30,30a: BARC (bottom anti-reflective coating)
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는 트렌치 포토 임계치수 균일성을 개선시키는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for improving trench photo critical dimension uniformity.
최근 반도체 소자의 제조기술이 발전하면서 0.13 ㎛ 이하의 반도체 소자 제조 과정에서는 점점 초미세한 패턴을 형성하여야 한다. 또한, 0.13 ㎛ 이하급의 반도체 소자 제조 공정에서는 다마신(damascene) 공정을 도입하기 시작하였다. 이에 따라, 리소그래피(lithography) 공정에서는 기존 라인 패턴(line pattern)을 대신하여 스페이스 트렌치 패턴(space trench pattern)을 형성시켜야 한다. With the recent development of the manufacturing technology of semiconductor devices, an increasingly fine pattern must be formed in the process of manufacturing a semiconductor device of 0.13 μm or less. In addition, a damascene process has begun to be introduced in the process of manufacturing a semiconductor device of 0.13 µm or less. Accordingly, in the lithography process, a space trench pattern should be formed in place of the existing line pattern.
한편, 포토리소그래피(photolithography) 공정 기술에 있어서는 KrF 광원을 이용하는 공정인 경우, 최근에는 0.13㎛ 라인 패턴(line pattern) 형성이 가능한 상태에 이르렀다. On the other hand, in the photolithography process technology, in the case of using a KrF light source, it has recently reached the state where 0.13 micrometer line pattern formation is possible.
그러나, 종래 기술에 따른 반도체 소자의 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, there is a problem in the method of manufacturing a semiconductor device according to the prior art as follows.
종래 KrF 광원을 이용하는 포토리소그래피(photolithography) 공정에 있어서는 광원의 한계상 0.13㎛ 이하의 패턴 형성은 어려운 실정이고, 이후 0.10㎛ 공정에서는 ArF 공정이 고려되고 있다. 특히, 다마신(damascene) 공정에서는 투과도가 높은 산화막(oxide) 계열의 막위에 트렌치 리소그래피(trench lithography) 공정을 수행하여야 하기 때문에 BARC (bottom anti-reflective coating)를 사용하더라도 BARC 두께의 불균일성 및 홀 패턴 밀도(hole pattern density)에 대한 BARC 충전(filling) 불균일성이 존재하여 트렌치 임계치수 균일성(trench critical dimension uniformity) 문제가 중요하게 대두되어 미세한 사이즈(size)의 패터닝(patterning)이 어려운 상태이다.In the photolithography process using a KrF light source, it is difficult to form a pattern of 0.13 μm or less due to the limitation of the light source, and the ArF process is considered in the 0.10 μm process. In particular, in the damascene process, a trench lithography process must be performed on an oxide-based film having high permeability, so that even if BARC (bottom anti-reflective coating) is used, nonuniformity and hole pattern of BARC thickness Because of BARC filling nonuniformity with respect to the hole pattern density, trench critical dimension uniformity problem is a significant problem, it is difficult to pattern the fine size (size).
이에 대한 해결방안으로 최근 시도되는 방법이 BARC 충전(filling)에 의한 임계치수 균일성(CD uniformity) 향상 방법인데, 이러한 방안 역시 근원적으로는 BARC 자체의 재료적인 특성이 갖는 코팅(coating) 특성 등으로 인해 모든 패턴에서 완전한 BARC 충전(filling)을 이루지 못하여 임계치수 균일성 문제를 해결하지 못한다는 문제점이 있다. As a solution to this problem, a recent attempt is to improve CD uniformity by BARC filling, which is basically due to the coating properties of BARC itself. Due to this, there is a problem in that it does not solve the problem of critical uniformity because it does not achieve full BARC filling in all patterns.
이에, 본 발명은 상기 종래 기술의 제반 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 비아홀이 패터닝된 기판에 트렌치 공정을 진행할 경우 BARC CMP 공정을 이용하여 BARC 충전(filling)을 함으로써 트렌치 포토 임계치수 균일성을 개선시키는 반도체 소자의 제조방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, the object of the present invention is to carry out the trench process to the via hole patterned substrate by using BARC CMP process BARC filling (trench photo) It is to provide a method for manufacturing a semiconductor device that improves the critical uniformity.
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은, 다수의 비아홀이 패터닝된 기판을 준비하는 단계; 상기 다수의 비아홀을 매립하는 두께로 상기 기판상에 BARC (bottom anti-reflective coating)를 형성하는 단계; 및 상기 BARC를 화학적 기계적 연마 공정으로 일부 제거하여 평탄화하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: preparing a substrate on which a plurality of via holes are patterned; Forming a bottom anti-reflective coating (BARC) on the substrate with a thickness filling the plurality of via holes; And flattening the BARC by partially removing the BARC by a chemical mechanical polishing process.
이하, 본 발명에 따른 반도체 소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 및 도 2는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도이다.1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 제조방법은, 도 1에 도시된 바와 같이, 선택적인 식각(etching) 공정으로 다수의 비아홀(20: via hole) 패터닝(patterning)을 마친 기판(10:substrate)을 준비한다. In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 1, a
그런다음, 후속하는 트렌치(trench) 공정시 BARC 충전(bottom anti-reflection coating filling)을 가능하게 하는 BARC (bottom anti-reflective coating), 예를 들면, 분자량(molecular weight)이 1,000 ~ 100,000 정도로 낮은 BARC(30)를 충분한 두께로 코팅(coating)한다.Then, a bottom anti-reflective coating (BARC) that enables bottom anti-reflection coating filling in subsequent trenching processes, e.g. BARC with molecular weights as low as 1,000 to 100,000 (30) is coated to a sufficient thickness.
한편, 상기 코팅된 상태의 BARC(30)는 여전히 일부 토폴로지(topology)가 남아있게 된다. 그렇지만, 상기 BARC(30)는 충분한 두께로 코팅(coating) 되어 있기 때문에 상기 다수의 비아홀(20) 내부는 상기 BARC(30)로 완전히 충전(filling) 할 수 있게 된다.On the other hand, the coated BARC 30 still has some topology left. However, since the BARC 30 is coated to a sufficient thickness, the plurality of
이어서, 도 2에 도시된 바와 같이, 상기 비아홀(30)을 충분히 매립하며 표면의 굴곡을 제거하여 평탄화시킬 목적으로 상기 기판(10)상에 코팅된 BARC(30)를 레지스트 화학적 기계적 연마(resist chemical mechanical polishing) 공정을 진행한다.Subsequently, as illustrated in FIG. 2, the BARC 30 coated on the
한편, 상기 BARC(30)에 대한 화학적 기계적 연마 정도는 상기 비아홀(20)을 충분하고도 완전하게 충전(filling)된 상태이면서 후속하는 식각(etching) 공정이 가능할 정도의 두께로 연마한다.On the other hand, the chemical mechanical polishing degree for the BARC 30 is polished to a thickness sufficient to allow the subsequent etching process while the
이후, 도면에는 도시하지 않았지만, 트렌치 포토 공정을 진행하고 이후에 예정된 후속 공정을 진행하여 반도체 소자를 완성한다.Subsequently, although not shown in the drawings, a trench photo process is performed and a subsequent predetermined process is performed to complete the semiconductor device.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 제조방법에 있어서는 다음과 같은 효과가 있다. 본 발명에 있어서는, BARC 충전(filling) 이후에 트렌치 포토(trench photo) 공정시 레지스트 두께의 균일성(resist thickness uniformity)으로 인해 트렌치 포토 공정의 임계치수 균일성의 탁월한 효과가 있게 된다.As described above, the method of manufacturing a semiconductor device according to the present invention has the following effects. In the present invention, due to the resist thickness uniformity in the trench photo process after BARC filling, there is an excellent effect of the critical dimension uniformity of the trench photo process.
또한, 별도의 장비 필요 없이 단순한 BARC 공정만으로도 미세한 다마신 트렌치 패턴이 가능하며, 단순화된 안정적 공정 제어로 인하여 소자 개발이 용이하며 생산 수율도 향상되는 효과가 있다.In addition, a fine damascene trench pattern is possible using a simple BARC process without the need for additional equipment, and the device development is easy and the production yield is improved due to the simplified and stable process control.
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| US5362669A (en) * | 1993-06-24 | 1994-11-08 | Northern Telecom Limited | Method of making integrated circuits |
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| US5362669A (en) * | 1993-06-24 | 1994-11-08 | Northern Telecom Limited | Method of making integrated circuits |
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