KR100698241B1 - Method of driving Liquid Crystal Display - Google Patents

Abstract

The present invention relates to a data driving method for reducing the amount of memory used in a liquid crystal display device, and more particularly, to a data driving method of a liquid crystal display device capable of reducing rearranged memory capacity of a liquid crystal display device using a Mux driving method. will be.

M}에 대응하는 저장용량을 가지는 메모리를 마련하는 단계와 현재 라인 데이터를 저장하는 단계와, 상기 현재라인 데이터중 일부 데이터가 데이터라인에 공급되도록 멀티플렉서를 제어하는 단계와, 상기 데이터라인에 공급된 현재 라인데이터에 의해 비어있는 잔류영역에 다음 라인 데이터의 일부를 저장하는 단계와, 상기 라인 메모리에 잔류한 현재라인 데이터 모두가 상기 데이터라인들에 공급되도록 멀티플렉서를 제어함과 동시에 상기 라인메모리에 저장된 상기 다음라인데이터 일부 이외의 다음라인 데이터 모두를 상기 라인메모리에 저장하는 단계를 포함한다. A data driving method of a liquid crystal display device according to the present invention is a liquid crystal display device having a multiplexer for supplying data to N data lines by dividing the data from a memory into a predetermined number of quarters N, wherein + M) / N {where N and M are integers greater than or equal to "0" and N

Providing a memory having a storage capacity corresponding to M}, storing current line data, controlling a multiplexer such that some data of the current line data is supplied to a data line, and Storing a portion of the next line data in the remaining area empty by the current line data, and controlling the multiplexer so that all of the current line data remaining in the line memory is supplied to the data lines and simultaneously stored in the line memory. And storing all the next line data other than the portion of the next line data in the line memory.

According to the present invention, the area corresponding to the memory chip can be reduced by reducing the amount of memory to be used, thereby reducing the unit cost and power consumption.

Description

Driving Method of Liquid Crystal Display {Method of driving Liquid Crystal Display}             

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically shows a MUX drive timing generator.

FIG. 2 is a signal characteristic diagram of a MUX driving timing generator shown in FIG. 1; FIG.

3 is a block diagram of a memory storage state at an early stage according to the conventional scheme;

4 is a block diagram of an intermediate memory storage state according to the conventional scheme.

5 is a block diagram of a memory storage state of the last stage according to the conventional scheme.

6 is a block diagram of an initial memory storage state in accordance with the present invention.

7 is a block diagram of an intermediate memory storage state in accordance with the present invention.

Figure 8 is a block diagram of a memory storage state of the final stage in accordance with the present invention.

9 to 12 are exemplary views illustrating a storage state of a memory by the MUX driving method according to the present invention.

               <Brief description of symbols for the main parts of the drawings>

1,11,21,31: (N-1) line data 2,12,22,32: N line data

The present invention relates to a data processing method for reducing the amount of memory used in a timing controller, and more particularly, to a data driving method of a liquid crystal display device capable of reducing rearranged memory capacity of a liquid crystal display device using a Mux circuit.

Conventional liquid crystal display devices display video signal such as a television signal using a pixel matrix in which pixels are arranged at intersections between gate lines and data lines. Here, each pixel is composed of a liquid crystal cell for adjusting the light transmittance according to the data signal and a thin film transistor for switching the data signal to be supplied to the liquid crystal cell from the data line. The pixel matrix is located between two glass substrates. The liquid crystal display includes a driving integrated circuit for driving the gate lines and the data lines.

Referring to FIG. 1, a circuit diagram of a MUX driving method is shown. In the MUX driving method, N data lines are connected to the output of each driving circuit through a MUX switch, and a signal is applied to each data line while the MUX switch is operated in turn. In FIG. 1, five MUX switches are used.

2 shows a signal diagram of the circuit diagram shown in FIG. 1. When the first MUX switch operates, a signal is applied to the data line, and the next switch is operated, such that the MUX switch operates in order, and a signal is applied to the data line.

3 to 5, a memory storage state of the conventional method is shown. 3 shows a state where the data 1 of the previous line is stored in the memory. Notice that two lines of memory are used. When the first MUX switch of the next line is turned on, the data corresponding to the first switch in the first line memory is sent to the driving circuit, and the corresponding data (2) is stored in the second memory. As a result, as shown in FIG. 4, the memory state is changed. If this operation is repeated to operate all the switches of the next line, the block diagram as shown in FIG. The data of the previous line is moved to the driving circuit, and the data 12 of the next line is stored in the second line memory. This can be seen that the signal is not sequentially applied from the front of the line. Since the order of applying the data is different from the order of the signals supplied from the system, the data signals must be rearranged and supplied to the driving circuit according to the MUX method. The data rearrangement is performed by a timing generator, which requires data of one entire line, and also requires additional line memory to store the data since the data of the next line is continuously input while the data is rearranged. There is a problem.

Accordingly, an object of the present invention is to provide a data processing method of a liquid crystal display device in which two line memories perform MUX data rearrangement.

M}단, N 에 대응하는 저장용량을 가지는 메모리를 마련하는 단계와 현재 라인 데이터를 저장하는 단계와, 상기 현재라인 데이터중 일부 데이터가 데이터라인에 공급되도록 멀티플렉서를 제어하는 단계와, 상기 데이터라인에 공급된 현재 라인데이터에 의해 비어있는 잔류영역에 다음 라인 데이터의 일부를 저장하는 단계와, 상기 라인 메모리에 잔류한 현재라인 데이터 모두가 상기 데이터라인들에 공급되도록 멀티플렉서를 제어함과 동시에 상기 라인메모리에 저장된 상기 다음라인데이터 일부 이외의 다음라인 데이터 모두를 상기 라인메모리에 저장하는 단계를 포함한다. 특히, 상기 메모리는 (멀티플렉서의 분기수 +2)에 대응하는 저장용량을 가지는 단계을 포함한다.In order to achieve the above object, the present invention provides a liquid crystal display device having a multiplexer for dividing data from a memory by a predetermined number of quarters N and supplying the data to N data lines, wherein (N + M) / N {where N and M are integers greater than or equal to "0" and N

M} providing a memory having a storage capacity corresponding to N, storing the current line data, controlling a multiplexer so that some of the current line data is supplied to the data line, and the data line Storing a part of the next line data in an empty remaining area by the current line data supplied to the control panel; and controlling the multiplexer so that all of the current line data remaining in the line memory is supplied to the data lines. And storing all the next line data other than the portion of the next line data stored in the memory in the line memory. In particular, the memory includes the step of having a storage capacity corresponding to (the number of branches of the multiplexer +2).

Other objects and features of the present invention other than the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.
6 shows an initial memory storage state according to the present invention.
7 shows an intermediate memory storage state according to the present invention.
8 shows a memory storage state of the final stage according to the present invention.
6 to 8, the memory 100 further includes twice the number of MUX branches in a capacity of one line, and a storage area of the memory 100 obtained through Equation 1 below. Divide by.
Memory area = MUX branch number + 2
Referring to FIG. 6, it can be seen that the previous data 21 is stored in the memory 100 and an extra storage area corresponding to +2 exists. When the first switch of the next line is turned on, the first data 31 of the previous line is sent to the driving circuit, and the new data 22 is stored in the spare storage area. This can be represented as shown in FIG. Accordingly, if the operation is repeated, the data corresponding to the next switch is stored in the spare storage area, and the data 32 corresponding to the next line is stored without the memory of the next line as shown in FIG. 8. .

delete

9 to 12, a preferred embodiment of the present invention will be described. These are the memory storage states when 5MUX is used at 800 * RGB * 600 (SVGA) resolution. Six cells can be stored in one cell, which is supplied to the driver IC one by one.

80은 데이터가 들어오는 순서를 나타내게 된다. 하나의 칸에는 6개의 데이터가 저장되므로, 1 라인의 데이터가 전부 저장시 총 2400개의 데이터가 메모리에 저장되게 된다.Referring to FIG. 9, a state where all data of one line is stored. Each MUX switch is called A, B, C, D, E. 1

80 indicates the order in which data comes in. Since six data are stored in one cell, when all data of one line is stored, a total of 2400 data are stored in the memory.

16E)에 1/5라인 만큼은 여분의 메모리에 저장된다. 이 때 이전 라인의 저장된 데이터 중 첫번째 MUX에 해당되는 데이터(A)는 구동회로에 공급되기 때문에, 이에 해당하는 메모리장소에는 새로운 데이터를 저장할 수 있게 된다.Referring to FIG. 10, it is a memory storage state diagram when data of the next line is input. When data of the next line is input (1A

As many as 1/5 lines are stored in the extra memory. At this time, since the data A corresponding to the first MUX of the stored data of the previous line is supplied to the driving circuit, new data can be stored in the corresponding memory location.

Referring to FIG. 11, a memory storage state when the second MUX switch is operated is illustrated. Since the data B corresponding to the second MUX is supplied to the driving circuit, when data of the next line is input (17A to 32E), as in FIG. 10, 1/5 lines are stored in an extra memory location. That is, since the data B corresponding to the second MUX is supplied to the driving circuit, the data 17A to 32E corresponding to the next line are stored in the memory location where the data B corresponding to the second MUX existed. .

Referring to FIG. 12, after all of the data of the previous line is supplied to the driving circuit, the data of the next entire line is stored in the memory. The data corresponding to each MUX is supplied to the driving circuit, and the data corresponding to the MUX of the next line are stored in the corresponding data place.

When the data of the next line is stored in the manner described above with reference to FIG. 12, the state is changed back to the state as shown in FIG. Accordingly, only two states of FIGS. 9 and 12 alternately occur, thereby simplifying the memory addressing circuit implementing the same. However, if it is not driven in this way, various types of results are produced, and although the amount of memory can be reduced, the implementation circuit becomes very complicated and adverse effects occur. Accordingly, by using the driving method using the memory of the (N + 2) / N line, it is possible to reduce the amount of memory and to implement a simple addressing circuit. For example, 5 MUX uses 7 / 5-line memory, saving 30% memory.

As described above, in the data processing method of the liquid crystal display device according to the present invention, while a signal is applied to each data line while operating the MUX switch, data is stored in an extra memory location. Accordingly, in the method of designating the address of the memory of the timing generator of the MUX driving method, it is possible to reduce the chip area and the power consumption by reducing the amount of memory used.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

A liquid crystal display comprising a multiplexer for dividing data from a memory into a predetermined number of quarters N and supplying the data to N data lines. Providing a memory having a storage capacity calculated by Equation 1 with respect to the branch number N of the multiplexer; Storage capacity = (N + M) / N --- Equation 1 However, in the above formula, N and M are integers of "0" or more, and N

M Storing current line data in the memory; Controlling the multiplexer to supply some data of the current line data to a data line; Storing a part of the next line data in a remaining area empty by the current line data supplied to the data line; Controlling the multiplexer to supply all of the current line data remaining in the memory to the data lines and simultaneously storing all the next line data other than the portion of the next line data stored in the memory in the memory. A data driving method of a liquid crystal display device. The method of claim 1, Adding a capacity corresponding to the following Equation 2 to the memory for one line of the memory; The data driving method of the liquid crystal display device further comprising. Additional capacity = M / N --- Equation 2 The method of claim 1, And the memory has a storage capacity obtained by the following equation (3). Storage capacity = number of branches of the multiplexer + 2 --- Equation 3 The method according to claim 1 or 3, Periodically storing data in the memory and periodically outputting data from the memory The data driving method of the liquid crystal display device further comprising.

Images