KR100697271B1 - Voltage sense amplifier for generating variable reference level - Google Patents

Abstract

The present invention relates to a voltage sense amplifier having a variable reference level generation function. The voltage sense amplifier is capable of sufficiently securing on-cell margins and off-cell margins required for data recognition regardless of changes in operating voltages of semiconductor memory devices. The reference voltage is varied according to the change of the operating voltage. As a result, read errors due to lack of voltage margin are prevented.

Sense Amplifier, Reference Level, Reference Voltage

Description

VOLTAGE SENSE AMPLIFIER FOR GENERATING VARIABLE REFERENCE LEVEL}

1 is a diagram illustrating a change in a reference voltage according to an operating voltage of a semiconductor memory device and a change in a core cell voltage when a memory cell is turned on or off;

2 is a block diagram schematically showing a configuration of a voltage sense amplifier according to a preferred embodiment of the present invention;

3 is a circuit diagram of a core cell level detector and a comparer according to a preferred embodiment of the present invention shown in FIG.

4 is a circuit diagram of a reference level controller according to a preferred embodiment of the present invention shown in FIGS. 2 and 3;

5 is a detailed circuit diagram of a voltage detector according to a preferred embodiment of the present invention shown in FIG.

6 shows a comparison voltage with respect to an operating voltage, and an operating voltage distribution result between each resistor;

7 shows the output of a voltage detector according to an operating voltage;

8 is a circuit diagram of a reference level generator according to a preferred embodiment of the present invention shown in FIGS. 2 and 3;

9 shows a simplified configuration of a voltage sense amplifier for a memory cell using a split gate type transistor, which is one of flash cell types;

FIG. 10 is a circuit diagram of a reference level generator for the voltage sense amplifier shown in FIG. 9; FIG.

11 is a flowchart showing a data recognition method and a reference level changing method of the voltage sense amplifier according to the present invention; And

12 is a view showing a result of the reference level conversion of the voltage sense amplifier according to the present invention.

<Description of Symbols for Main Parts of Drawings>

400, 500: voltage sense amplifier 410: reference cell level converter

420: reference level control unit 421: comparison voltage generation unit

423: control voltage generator 427: voltage divider

440: reference level generator 470: core cell level detector

490: comparison unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier of a semiconductor memory device, and more particularly to a voltage sense amplifier capable of varying a reference level to be used for data recognition.

As the size of the memory increases, the data signal weakens when reading data stored in the memory core cell, which can read wrong data and delay time until the voltage swing in the bit line stabilizes. Can be long. Therefore, most memories use sense amplifiers that amplify the data signal to provide stable read operations, reduce bit line latency, and provide low power. Sense amplifiers are largely divided into voltage sense amplifiers and current sense amplifiers.

In general, a voltage sense amplifier generally compares and compares a certain level of reference cell voltage (Vr) with a sensed core cell voltage (Core cell voltage; Vc) when performing a read on a core cell. According to the result, it is determined whether the corresponding core cell is on or off. For example, when the core cell voltage Vc is lower than the reference cell voltage Vr, the core cell voltage Vc is determined as the off cell D0. When the core cell voltage Vc is higher than the reference cell voltage Vr, the core cell voltage Vc is turned on as the on cell D1. To judge. At this time, changes of the core cell voltage Vc and the reference cell voltage Vr according to the operating voltage Vcc are as follows.

FIG. 1 is a diagram illustrating a change of a reference voltage Vr according to an operating voltage Vcc of a semiconductor memory device and a change of core cell voltages Von and Voff when a memory cell is turned on or off.

Referring to FIG. 1, when the state of the core cell is in the off state D0, the voltage Voff of the core cell has a lower value than the reference voltage Vr. However, in the high voltage of the core cell, the reference voltage Vr ) Will gradually decrease (see the hatched section on arrow 1). The off-core core cell voltage Voff may not perform a read operation properly in the sense amplifier due to lack of margin when compared to the reference voltage Vr at the high voltage HVcc. On the contrary, when the state of the core cell is in the on state D1, the voltage Von of the core cell has a higher value than the reference voltage Vr, but at a low voltage LVcc due to the voltage characteristics of the core cell, it is different from the reference voltage. Is reduced (refer to the hatched portion of arrow 2), and there is a problem in that the sense amplifier cannot be properly turned on (D1).

The technical problem to be achieved by the present invention is to ensure the on-cell margin and off-cell margin sufficient to perform the correct data recognition by varying the reference cell voltage in accordance with the change in the operating voltage, thereby reducing the read error due to the lack of voltage margin It is to provide a voltage sense amplifier that can be prevented in advance.

According to a feature of the present invention for achieving the object of the present invention as described above, the voltage sense amplifier can secure enough on-cell margin and off-cell margin required for data recognition regardless of the change in the operating voltage of the semiconductor memory device. A reference cell level converter configured to vary a reference cell voltage according to the change of the operating voltage; A core cell level detector sensing a voltage generated from a core cell of the semiconductor memory device; And a comparing unit which compares magnitudes of the reference cell voltage and the core cell voltage to recognize data stored in the core cell.

According to a feature of the present invention for achieving the object of the present invention as described above, the sensing method of the voltage sense amplifier (a) on-cell margin and off-cell required for data recognition regardless of the change in the operating voltage of the semiconductor memory device Varying a reference cell voltage according to a change in the operating voltage to sufficiently secure a margin; (b) sensing a voltage generated from a core cell of the semiconductor memory device; And (c) recognizing data stored in the core cell by comparing the magnitudes of the reference cell voltage and the core cell voltage.

According to an aspect of the present invention for achieving the object of the present invention as described above, by comparing the magnitude of the reference cell voltage and the core cell voltage of the semiconductor memory device to recognize the data stored in the core cell of the semiconductor memory device The reference level generation method of the voltage sense amplifier includes: (a) controlling a plurality of reference levels in response to a predetermined comparison voltage generated from an operating voltage of the semiconductor memory device and a voltage division result of dividing the operating voltage by a predetermined resistance ratio; Generating a voltage; And (b) adjusting a value of an output resistance in response to the plurality of reference level control voltages, and dividing the operating voltage by the output resistance value to generate the reference cell voltage.

According to an aspect of the present invention for achieving the object of the present invention as described above, by comparing the magnitude of the reference cell voltage and the core cell voltage of the semiconductor memory device to recognize the data stored in the core cell of the semiconductor memory device A method of generating a reference level of a voltage sense amplifier includes: (a) generating a comparison voltage having a constant voltage level from an operating voltage of the semiconductor memory device; (b) distributing the operating voltage at a predetermined resistance ratio through a plurality of resistors, and generating a plurality of reference level control voltages in response to the operation voltage distribution result and the comparison voltage; (c) selectively coupling a plurality of output resistors in response to the plurality of reference level control voltages; And (d) generating the reference cell current by dividing the operating voltage by the total resistance of the output resistors.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The novel voltage sense amplifier of the present invention varies the reference cell voltage based on a voltage distribution result obtained by dividing the operating voltage of the semiconductor memory device at a predetermined ratio and a predetermined comparison voltage generated inside the semiconductor memory device. As a result, in the low operating voltage section, the on-cell margin is sufficiently secured when the reference cell voltage is down, and in the high operating voltage section, the reference cell voltage is leveled up to sufficiently increase the off cell margin. Secured.

2 is a block diagram schematically illustrating a configuration of a voltage sense amplifier 400 according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the voltage sense amplifier 400 according to the present invention includes a reference cell level conversion unit 410, a core cell revel detecting unit 470, and a comparison unit comparison unit; 490). The reference cell level converter 410 divides the voltage distribution result Vr12, Vr23,..., By dividing the operating voltage Vcc of the semiconductor memory device by a predetermined ratio, and the predetermined comparison voltage Vcomp generated inside the semiconductor memory device. Based on this, the variable reference cell voltage Vr is output to the comparator 490. The core cell level detector 470 detects the core cell voltage Vc from the core cell of the semiconductor memory device and outputs the core cell voltage Vc to the comparator 490. The comparator 490 compares the magnitude of the reference cell voltage Vr input from the reference cell level converter 410 with the core cell voltage Vc input from the core cell level detector 470 to the core cell. Recognize the stored data.

In order to perform such an operation, the reference cell level converter 410 includes a reference level controller 420 and a reference level generator 440. The reference level controller 420 compares the voltage distribution results Vr12, Vr23,... With the predetermined comparison voltage Vcomp with respect to the operating voltage Vcc, and according to the comparison result, a plurality of reference level control voltages V _do1. -V _doN ) Reference level generation section 440 in response to the plurality of reference level, the control voltage (V -V _{do1 doN)} generated from the reference level, the control section 420 switches a plurality of the output resistor (R11, R12, ..., R14 ) . The plurality of output resistors R11, R12, ..., R14 are connected in parallel with each other. When increasing the number of the output resistor connected by the switching operation according to the reference level, the control voltage (V _do1 -V _doN), the total output resistance is reduced. When the number of output resistors connected by the switching operation decreases, the total output resistance value increases.

After the total output resistance value is determined, the reference level generator 440 distributes the operating voltage Vcc to the determined total output resistance value to generate the reference cell voltage Vr. For example, when the operating voltage Vcc decreases below the comparison voltage Vcomp, the total output resistance value is increased and the reference cell voltage Vr is lowered. As a result, the gap between the reference cell voltage Vr and the on cell voltage Von becomes large. In addition, when the operating voltage Vcc increases above the comparison voltage Vcomp, the total output resistance value decreases, and the reference cell voltage Vr becomes high. As a result, the gap between the reference cell voltage Vr and the off cell voltage Voff becomes large. Thus, sufficient on-cell margin and off-cell margin are secured enough to perform correct data recognition, thereby preventing read errors due to lack of voltage margin.

3 is a circuit diagram of the core cell level detector 470 and the comparator 490 according to an exemplary embodiment of the present invention shown in FIG. 2.

Referring to FIG. 3, the comparator 490 receives the core cell voltage Vc as one input terminal from the core cell level detector 470, and receives the reference cell voltage Vr from the reference cell level converter 410. It consists of a comparator that accepts as an input terminal. The comparator 490 compares the magnitudes of the core cell voltage Vc and the reference cell voltage Vr, and if the magnitude of the core cell voltage Vc is greater than the reference cell voltage Vr, a result of sensing the value of "1" If the magnitude of the core cell voltage Vc is smaller than the reference cell voltage Vr, the sensing result SAOUT of the value "0" is output.

The core cell level detector 470 includes a first PMOS transistor MP1 and a first NMOS transistor MN1 having a current path connected in series between the operating voltage Vcc and ground.

The first NMOS transistor MN1 receives a word line voltage Vwl of the memory device through a control terminal and outputs a core cell voltage Vc corresponding to the word line voltage Vwl. The current path of the first PMOS transistor MP1 is connected in series between the current path of the first NMOS transistor MN1 and the operating voltage Vcc. The first PMOS transistor MP1 receives the core cell voltage Vc through a control terminal.

FIG. 4 is a circuit diagram of the reference level controller 420 according to the preferred embodiment of the present invention shown in FIGS. 2 and 3.

Referring to FIG. 4, the reference level controller 420 according to the present invention includes a comparison voltage generator 421 and a control voltage generator 423. The comparison voltage generator 421 generates a comparison voltage Vcomp having a predetermined level from the operating voltage Vcc, and the control voltage generator 423 generates a plurality of reference level control voltages for varying the level of the reference cell voltage. do.

The comparison voltage generator 421 includes first and second resistors Rx1 and Rx2 connected in series to the operating voltage Vcc, and first and second current paths connected in series between the second resistor Rx2 and ground. The second NMOS transistors MN11 and MN12 and the first PMOS transistor MP11 are connected in series between the contacts of the first and second resistors Rx1 and Rx2 and ground. The control terminal of the first PMOS transistor MP11 is connected to the contact point of the second resistor Rx2 and the first NMOS transistor MN11, and the control terminal of the first NMOS transistor MN11 is connected to the first and second resistor Rx1. , Rx2). The control terminal of the second NMOS transistor MN12 is connected to an operating voltage Vcc.

When the operating voltage Vcc drops by a predetermined level by the first resistor Rx1 to generate a predetermined comparison voltage Vcomp, the first NMOS transistor MN11 is generated from the first resistor Rx1. The NMOS transistor MN12 is turned on in response to the comparison voltage Vcomp, and the second NMOS transistor MN12 is turned on in response to the operating voltage Vcc. As the first NMOS transistor MN11 and the second NMOS transistor MN12 are turned on, respectively, voltage levels applied to the control terminal of the comparison voltage Vcomp and the first PMOS transistor MP11 are the first and second NMOS transistors. The voltage is gradually lowered by the discharge operation of the MN11 and MN12, and when the voltage becomes lower than or equal to the predetermined level, the first PMOS transistor MP11, which is initially off, is turned on to start charging the comparison voltage Vcomp. As a result, the comparison voltage Vcomp can always generate a constant voltage without being influenced by an external environment due to the complementary charging and discharging operations of the transistors. The predetermined comparison voltage Vcomp generated internally by this process is used as a voltage (that is, a reference voltage for adjusting the level of the reference cell current) which is a reference of the operation of the voltage sense amplifier.

The control voltage generator 423 includes a plurality of voltage detectors 4251-4254 and a voltage divider 427. The voltage divider 427 divides the operating voltage Vcc at a predetermined rate through the plurality of resistors R1-R5 connected in series between the operating voltage Vcc and the ground, thereby providing voltage distribution results Vr12−. Vr45). Each of the voltage detectors 4251-4254 compares the corresponding operating voltage distribution result Vr12-Vr45 with the comparison voltage Vcomp generated from the comparison voltage generator 421, and thus the reference level control voltage V _do1. -V _do4 ), respectively. The plurality of reference level, the control voltage generated from a plurality of voltage detectors (4251-4254), (V -V _{do1 do4)} are all output to the reference level generator 440. In FIG. 4, the case in which four voltage detectors are provided is described as an example. However, this is merely an example. The number of voltage detectors, the number of resistors constituting the voltage divider, and the resistance ratio of the voltage divider may vary. It is possible.

FIG. 5 is a detailed circuit diagram of the voltage detector 425x according to the preferred embodiment of the present invention shown in FIG. 6 illustrates a comparison voltage Vcomp with respect to an operating voltage Vcc, and an operation voltage distribution result Vr12 to Vr45 between the resistors, and FIG. 7 illustrates a voltage detector according to the operating voltage Vcc. illustrates the output (V -V _{do1 do4)} of 4251-4254).

Referring to FIG. 5, a voltage detector 425x according to the present invention is generated from a first input terminal that receives an operating voltage distribution result Vrxy generated from a voltage divider 427 and a comparison voltage generator 421. And a second input terminal for receiving the comparison voltage Vcomp, and an output terminal for outputting the reference level control voltage Vdox to the reference level generator 440.

Each voltage detector 425x includes first and second PMOS transistors MP21 and MP22 having one end of a current path connected to the operating voltage and a control terminal connected in common to form a current mirror, and a current path. The first and second NMOS transistors MN21 and MN22 connected at one end of the first and second PMOS transistors MP21 and MP22 to the other ends of the current paths, respectively, and the first and second NMOS transistors MN21 in the current path. A third NMOS transistor MN23 connected in common with the other end of the current path of MN22, and a fourth NMOS transistor MN24 with a current path connected in series between the other end of the current path of the third NMOS transistor MN23 and ground. It includes. Here, the control terminal of the second NMOS transistor MN22 is used as the first input terminal that receives the operating voltage distribution result Vrxy, and the control terminal of the first NMOS transistor MN21 receives the comparison voltage Vcomp. It is used as a second input terminal, and the contact point of the current path of the first PMOS transistor MP21 and the first NMOS transistor MN21 is used as an output terminal for outputting the reference level control voltage Vdox.

The operation of each voltage detector 425x will be described with reference to FIGS. 5 to 7 as follows.

First, the second NMOS transistor MN22 of each voltage detector 425x receives the operating voltage distribution result Vrxy applied from the voltage divider 427 through the control terminal (ie, the first input terminal). The second NMOS transistor MN22 is turned on when the input operating voltage distribution result Vrxy is greater than or equal to a predetermined voltage to generate a current corresponding to the voltage.

The current generated in the second NMOS transistor MN22 is transferred to the first PMOS transistor MP21 through a current mirror configured between the first and second PMOS transistors MP21 and MP22 to charge the output terminal. The MN21 flows a current of a predetermined level corresponding to the comparison voltage Vcomp to the third and fourth NMOS transistors MN23 and MN24 in response to the comparison voltage Vcomp input through the second input terminal. Discharge the output terminal. The level of the reference level control voltage Vdox is determined according to the result of the charging and discharging of the output terminal (that is, the result of comparing the operating voltage distribution result Vrxy with the comparison voltage Vcomp).

In FIG. 6, a portion indicated by an arrow indicates a point in time at which each voltage detector 425x starts to generate a high level reference level control voltage Vdox, and a portion indicated by an arrow in FIG. 7 is indicated by an arrow in FIG. 6. Denotes the reference level control voltage Vdox generated at each voltage detector 425x, respectively. Reference level the control voltage (V -V _{do1 do4)} generated from each of the voltage detectors (4251-4254), as can be seen in Figure 6 and 7, first, while maintaining a low level operating voltage (Vcc), the arrow (I.e., when the operating voltage distribution result Vrxy becomes higher than the comparison voltage Vcomp), the level of the reference level control voltage Vdox increases rapidly, and the high level reference level control voltage ( the V -V _{do1 do4)} is generated.

At this time, the operating voltage Vcc is applied to the control terminals of the third and fourth NMOS transistors MN23 and MN24 to maintain the turn-on state. Accordingly, the third and fourth NMOS transistors MN23 and MN24 perform a current sink operation for flowing currents applied to the third and fourth NMOS transistors MN23 and MN24 to ground.

As described above, the value of the reference level control voltage Vdox generated in each voltage detector 4251-2254 is determined by the amount of current charged and discharged at the output terminal, and the amount of current charged and discharged is It is determined by the operating voltage division result Vrxy and the comparison voltage Vcomp. For example, when the operating voltage distribution result Vrxy for the operating voltage Vcc is lower than the comparison voltage Vcomp, the amount of charge discharged is larger than the amount of charge charged to the output terminal, so that the low level reference level control is performed. When the voltage Vdox is generated and the operating voltage distribution result Vrxy for the operating voltage Vcc is higher than the comparison voltage Vcomp, the amount of charge charged in the output terminal is greater than the amount of charge discharged. The high level reference level control voltage Vdox is generated. As a result, as the operating voltage Vcc level increases, the number of voltage detectors generating a high level reference level control voltage Vdox increases, and as the operating voltage Vcc level decreases, a low level reference level control voltage The number of voltage detectors generating (Vdox) increases.

FIG. 8 is a circuit diagram of the reference level generator 440 according to the preferred embodiment of the present invention shown in FIGS. 2 and 3. Referring to FIG. 8, the reference level generator 440 according to the present invention includes a switching unit 445, a reference voltage generator 446, and a reference level output unit 447.

The reference voltage generator 446 includes a first resistor Rx1, a first NMOS transistor MN31, and a second resistor Rx2 connected in series between the operating voltage Vcc and the ground. The first NMOS transistor MN31 is turned on by the word line voltage Vwl of the memory device, and outputs a voltage distribution result of the operating voltage Vcc by the first resistor Rx1 as the reference voltage Vr.

Although the magnitude of the reference voltage Vr is basically determined by the value of the first resistor Rx1, the reference level generator 440 according to the present invention may be driven by the switching unit 445 in addition to the value of the first resistor Rx1. The magnitude of the reference voltage Vr is adjusted by reflecting the adjusted resistance values R11, R12, R13, and R14.

The switching unit 445 is connected in parallel between the first resistor Rx1 of the reference voltage generator 446 and the first and second nodes N1 and N2 positioned at the end of the first NMOS transistor MN31. Two switching circuits 4451-4454. Each switching circuit 4451-4454 is composed of one resistor (R11-R14) and one NMOS transistor (MN32-MN35) connected in series. Each NMOS transistor MN32-MN35 included in the switching circuits 4451-4454 operates as a kind of switch. For example, if the reference level, the control voltage (V -V _{do1 do4)} corresponding to the reference level from the control unit 420 inputs, the response to the input reference level, the control voltage (V -V _{do1 do4)} on / off the resistance The R11-R14 are selectively connected to the first resistor Rx1 of the reference voltage generator 446. Accordingly, the reference voltage Vr generated from the reference voltage generator 446 may be a resistor R11-R14 of the switching unit 445 selectively connected to the first resistor Rx1 included in the reference voltage generator 446. It can be determined by the parallel resistance ratio of As a result, the voltage sense amplifier 400 in accordance with the invention by varying the level of the reference cell voltage (Vr) in accordance with a reference level control signal (V -V _{do1 do4)} outputted from each of the voltage detector (4251-4254) You can print it out.

At this time, if the level of the operating voltage (Vcc) is lowered to increase the number of the reference level the control signal (V -V _{do1 do4)} having a low level, the first resistor having the reference voltage generating section 446 ( The number of resistors connected to Rx1) is reduced. As a result, as the level of the operating voltage Vcc is lowered, it is possible to sufficiently secure an on cell margin at which the reference cell voltage Vr is down. Then, when a higher level of operating voltage (Vcc) is that the number of the reference level the control signal has a high level (V -V _{do1 do4)} increases, the first resistor (Rx1) provided in the reference voltage generating section 446 The number of resistors connected with is increased. As a result, as the level of the operating voltage Vcc increases, the reference cell voltage Vr is leveled up to sufficiently secure an off cell margin.

FIG. 9 is a schematic diagram illustrating a voltage sense amplifier 500 for a memory cell using a split gate type transistor, which is one of flash cell types, and FIG. 10 is a diagram illustrating a voltage sense amplifier 500 shown in FIG. A circuit diagram of the reference level generator 540 is shown.

9 and 10, the types of the transistors ST1 and ST31-ST35 included in the switching unit 545 of the core cell level detector 570 and the reference level generator 540 are flash memory cell type transistors. Except that, the same configuration as the circuit shown in Figs. 3 and 8, and the operations performed are also the same. Therefore, in order to simplify the description, the redundant description of the circuit will be omitted below.

The core cell of the semiconductor memory device may be configured as a general MOS transistor as shown in FIGS. 3 to 8, or may be configured as a flash memory cell type transistor as shown in FIGS. 9 and 10. In this case, the transistors constituting the core cell level detectors 470 and 470, the reference level generators 446 and 446 and the switching units 445 and 445 included in the reference level generators 440 and 440 are cores. It is composed of the same type of transistor as the cell.

For example, when the core cell of the semiconductor memory device includes a flash memory cell type transistor, the transistor ST1, the reference voltage generator 546, and the switching unit detect the core cell voltage in the core cell level detector 570. The transistors ST31-ST35 constituting the unit 545 are each composed of a transistor of a flash memory cell type. At this time, although not shown in the drawing, the reference level control unit 520 has the same circuit configuration as the reference level control unit 420 shown in FIG.

As described above, when the transistors constituting the core cell level detector 470, the reference level generator 546, and the switching unit 545 are composed of the same kind of transistors as the core cell, the characteristics of the core cell are maintained. It is possible to effectively vary the level of the reference current.

11 is a flowchart illustrating a data recognition method and a reference level change method of the voltage sense amplifiers 400 and 500 according to the present invention, and FIG. 12 illustrates a result of the reference level conversion of the voltage sense amplifiers 400 and 500 according to the present invention. Figure showing.

Referring to FIG. 11, in order to recognize data stored in a core cell, the voltage sense amplifiers 400 and 500 according to an exemplary embodiment of the present invention first use the reference cell level converters 410 and 510 to operate the voltage of the semiconductor memory device. Vcc is distributed at a predetermined resistance ratio and the reference cell voltage Vr is varied based on the voltage distribution result Vr12-Vr45 and a predetermined comparison voltage Vcomp generated in the semiconductor memory device (step 4100). ). Then, the voltage Vc generated from the core cell of the semiconductor memory device is sensed through the core cell level detectors 470 and 570 (step 4700), and the core cell voltage Vc through the comparators 490 and 590. The data stored in the core cell is recognized by comparing the magnitudes of the reference cell voltages Vr (step 4900).

In detail, the reference cell level converters 410 and 510 of the voltage sense amplifiers 400 and 500 generate a comparison voltage Vcomp of a predetermined level in order to vary the reference level (step 4200), and apply a plurality of resistors. In operation 4250, a plurality of reference level control voltages Vdox are generated by comparing the voltage distribution result Vrxy obtained by dividing the operating voltage Vcc with a predetermined resistance ratio and the comparison voltage Vcomp of a predetermined level. Then, in response to the plurality of reference level control voltages Vdox generated from the reference level controllers 420 and 540, the plurality of resistors R11 to R14 are switched (step 4400), and the plurality of switched plurality of resistors is switched. The parallel resistance ratios of the resistors R11-R14 and the resistor Rx1 included in the reference voltage generator 446 are obtained, and the reference cell voltage Vr is obtained by distributing the operating voltage Vcc using the obtained resistance ratio. (4444 steps).

As described above, the voltage sense amplifiers 400 and 500 according to the present invention generate voltage distribution results Vr12-Vr45 obtained by dividing the operating voltage Vcc of the semiconductor memory device at a predetermined ratio and generated inside the semiconductor memory device. in response to on the basis of a predetermined comparison voltage (Vcomp) controls the output of the voltage detector (4251-2254), and the voltage detector, the plurality of reference level control signal (V -V _{do1 do4)} generated from (4251-2254) The level of the reference cell voltage Vr is varied by controlling the on / off of the plurality of switching transistors to adjust the resistance ratio to be used to distribute the operating voltage Vcc.

As a result, as shown in FIG. 12, the reference cell voltage Vr is sufficiently lowered as the level of the operating voltage Vcc decreases, thereby sufficiently securing the cell margin. In addition, the reference cell voltage Vr becomes higher as the level of the operating voltage Vcc increases, thereby sufficiently securing off-cell margins.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

As described above, according to the voltage sense amplifier and the method according to the present invention, at a low voltage, a sufficiently high cell margin on which the reference voltage itself is down is ensured, and at a high voltage, the reference voltage is maintained. It is leveled up to sufficiently secure off cell margin. As a result, a read error of the memory device due to the lack of voltage margin is prevented.

Claims (19)

A reference cell level converter configured to vary a reference cell voltage according to the change of the operating voltage to sufficiently secure an on cell margin and an off cell margin for data recognition regardless of a change in an operating voltage of a semiconductor memory device; A core cell level detector detecting a voltage generated from a core cell of the semiconductor memory device; Comparing unit for comparing the magnitude of the reference cell voltage and the core cell voltage to recognize the data stored in the core cell, The reference cell level converter; A reference level controller configured to generate a plurality of reference level control voltages based on a voltage distribution result of dividing the operating voltage at a predetermined ratio and a predetermined comparison voltage generated inside the semiconductor memory device; And a reference level generator configured to selectively connect a plurality of resistors in response to the plurality of reference level control voltages, and to distribute the operating voltage to the total resistance values of the selectively connected resistors to generate the reference cell voltage. The reference level control unit; A comparison voltage generator for generating the comparison voltage having a predetermined level from the operating voltage; A voltage divider configured to distribute the operating voltage at a predetermined rate through a plurality of resistors connected in series between the operating voltage and ground; And A voltage detector configured to detect when an operation voltage distribution result generated from each of the resistors becomes higher than the comparison voltage and generate a plurality of reference level control voltages, The voltage detector; A plurality of comparison circuits for comparing the operation voltage distribution result with the comparison voltage, The voltage detector may increase the number of activated reference level control voltages when the detection result of the operation voltage distribution is higher than the comparison voltage. And when the operation voltage division result is lower than the comparison voltage, the number of activated reference level control voltages is reduced. delete The method of claim 1, The reference cell level converting unit increases the gap with the cell voltage down by lowering the level of the reference cell voltage when the operating voltage decreases below the comparison voltage. And when the operating voltage increases above the comparison voltage, increases the level of the reference cell voltage to increase the gap with the off cell voltage. delete delete delete The method of claim 1, wherein the reference level generating unit A reference voltage generator including a first output resistor; And A switching unit selectively connecting a plurality of second output resistors to the first output resistors in response to the plurality of reference level control voltages generated from the reference level controllers; And the reference voltage generator generates the reference cell voltage by dividing the operating voltage by the total resistance values of the first and second output resistors. The method of claim 7, wherein And the switching unit includes a plurality of switching transistors which are switched according to the plurality of reference level control voltages to selectively connect the plurality of second output resistors to the first output resistor. The method of claim 8, Wherein each switching transistor is a transistor of the same kind having the same operating characteristics as the core cell of the memory device. The method of claim 9, And the switching transistors are any one of an N-type MOS transistor and a P-type MOS transistor. The method of claim 9, And said switching transistors are flash memory cell type transistors. delete delete delete delete delete delete delete delete

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