JP2003317492A - Memory for two-stage sensing amplifier with additional load element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory capable of reading data fast and accurately by increasing an operation margin and improving a reading speed and to provide a method for operating the memory. <P>SOLUTION: This memory includes at least one or more memory cells having a data end for providing a data current; a sensing element connected to the data end and having comparison ends for generating a data signal on the basis of a voltage difference with a reference current; a first load element connected to a first comparison end of the sensing element and having a first end for generating voltage; and a second load element connected to the first comparison end of the sensing element to be enabled or disabled. When the second load element is enabled, the second load element generates voltage on the basis of current inputted to a second end, and when the second load element is disabled, the second load element stops the input of the current. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory, and particularly when reading data, the sensitivity is increased by temporarily accelerating the memory by using an additional load element and further invalidating the load element. The present invention relates to a memory for ensuring a margin and a method thereof.

[0002]

2. Description of the Related Art With the development of the information society, a large amount of data,
Information, technology, knowledge, etc. are now organized and stored in the form of digital data. Therefore, the memory for storing digital data has become an important point for research and development in the information industry. In particular, the flash memory can store digital data in a non-volatile manner, and can achieve high-speed access in an electronic application manner. That is, it is one of the most important non-volatile memory devices because it can store data without requiring mechanical operation unlike a general hard disk.

FIG. 1 is a circuit diagram of a conventional memory 10.
As shown, the memory 10 is biased with a DC power supply Vdd. A plurality of memory cells (in FIG. 1, only two memory cells 11A and 11B are disclosed and represented).
And two load separation elements 12A and 12B, a sensing element SA1, two p-type metal oxide semiconductor transistors Ta1 and Ta3 as load elements, and a p-type metal oxide film transistor Ta7 as a reference element. . The memory cells 11A and 11B are metal oxide semiconductor transistors Ma each having a floating gate.
1, data is saved by Ma2, transistor TA
1 and TA2 respectively control access to the memory cell. The transistors Ma1, Ma2, TA1, T
The gates of A2 have control voltages Vma1 and Vma, respectively.
The conduction and interruption of each transistor are controlled by 2, Vd1 and Vd2. In addition to the gate, the transistor TA1 of the memory cell 11A has one end electrically connected to the transistor Ma1 and the other end serving as a data end of the memory cell 11A, and electrically connected to the node Na5 together with the load separation element 12A. Similarly, one end connected to the node Na5 of the transistor TA2 of the memory cell 11B is
It becomes the data end of the memory cell 11B.

The load isolation elements 12A and 12B are provided with inverters Iva1 and Iva2 and p-type metal oxide semiconductor transistors Ta5 and Ta6, respectively. P-type metal oxide semiconductor transistor Ta1 serving as a load element,
Ta3 is connected in a negative feedback form, and the source of the transistor TA1 serves as the first end and is connected to the node N.
It is connected to the load separation element 12A at a1. The drain is connected to the ground terminal G. The source of the transistor TA3 is connected to the load separation element 12B at the node Na3 as the third end, and the drain is also connected to the ground end G. The sensing element SA1 is a differential sensing amplifier,
It has a first comparison end N1a and a second comparison end N2a, and is connected to the nodes Na1 and Na3, respectively. Sensing element S
A1 compares the voltages of the first comparison terminal N1a and the second comparison terminal N2a and generates the data signal Vrp1 in accordance with this. The metal oxide semiconductor transistor Ta7 having a floating gate serves as a reference element, and its gate is controlled by receiving the control voltage Vca. In addition, both electrodes have one end connected to the power supply Vdd and the other end serving as a reference end.
In, it is connected to the load separation element 12B.

A flash memory stores data for each bit in a transistor having a floating gate in a memory cell. When writing bit-wise data to a memory cell, different amounts of charge are injected into the floating gate, and the bit represents a digital value "0" or "1". The threshold voltage of the transistor changes when different amounts of charge are injected into the floating gate. That is, even under the same gate bias conditions, if the amount of charge in the floating gate is different, the degree of conductivity of the transistor is also different, so that different data currents are generated. Due to this difference, the data stored in the floating gate of each memory cell can be read.

As shown in FIG. 1, when the memory 10 reads the bit data stored in the memory cell 11A,
The gate of the transistor MA1 is biased by an appropriate control voltage Vma1, and the gate is made conductive to generate the data current If1. At the same time, the high level control voltage Vd1
Thus, the transistor TA1 is made conductive, and the data current If1 flows to the node Na5 via the transistor TA1. As a matter of course, in this case, the transistor TA2 in the memory cell 11B is controlled by the control voltage Vd2.
The memory cell 11B is cut off by the
No current is output to the node Na5. Therefore, the reading of data from the memory cell 11A is not interfered with. The load isolation element 12A transmits the data current If1 to the node Na1 and injects the data current If1 into the transistor TA1 serving as a load element. Transistor TA
1 is biased by the data current, the node Na1
At, the corresponding voltage is generated.

At the same time that the transistor MA1 becomes conductive,
The transistor TA7 whose control voltage Vca is also a reference element
And a reference current Ir1 is generated in the transistor TA7. The reference current Ir1 is applied to the load separation element 12B.
Is injected into the transistor TA3 via. The transistor TA3 serving as a load element receives the bias of the reference current and similarly generates a reference voltage corresponding to the node Na3.

The sensing element SA1 has a first comparison end N1.
a and the second comparison terminal N2a, the voltages of the nodes Na1 and Na3 are compared, and the corresponding data signal Vrp
1 is generated and the data in the memory cell 11A is read.

FIG. 2 shows the above-mentioned data reading process.
Will be described in detail below with reference to. FIG. 2 shows that when the memory 10 reads data, the first comparison terminal N1a in the process is read.
3 is a table showing changes in voltage between the second comparison terminal N2a and the second comparison terminal N2a over time. The horizontal axis of FIG. 2 represents time, and the vertical axis represents voltage. Curves V (N1a) H and V (N1a) L represent changes in the voltage of the first comparison terminal N1a with time,
(N2a) represents the change with time of the voltage of the second comparison terminal N2a. Before reaching the time point ta0, the memory 10 has not started reading data. Therefore, the first comparison end N1
The voltage of a and the second comparison terminal N2a becomes a high voltage by charging. When the time point ta0 is reached, the transistors Ma1 and Ta are
7 starts to generate current, and lowers the voltage at the first comparison terminal N1a and the second comparison terminal N2a, respectively. As described above, since the amount of charges stored in the floating gate of the transistor Ma1 in the memory cell 11A is different, the data currents If1 generated under the control of the equivalent control voltage Vma1 are different from each other. When the threshold voltage of the data current If1 is large (that is, the transistor Ma1) is low,
The voltage of the first comparison terminal N1a becomes as represented by the curve V (N1a) H, and finally decreases until reaching a relatively high steady voltage state VaH. On the contrary, when the data current If1 is low (that is, the threshold voltage is high when the transistor Ma1 is high), the voltage of the first comparison terminal N1a becomes as shown by the dotted curve V (N1a) L, and finally becomes a relatively low steady state. It goes down to the voltage state VaR. Similarly, the voltage of the second comparison terminal N2a falls to the steady voltage state VaR. In the time from time point ta0 to ta2, the inverters Iva1 and Iva2 in the load separation elements 12A and 12B are connected to the transistor TA.
5 and TA6 are appropriately biased, and nodes Na1 and Na3 are
It reduces the loading effect of and reduces the time to reach a stable state. When the voltages at both comparison terminals reach a stable state at time ta2, the sensing element SA1 determines the data stored in the memory cell 11A based on the voltage difference between both comparison terminals. That is, if the voltage at the first comparison end is higher than the voltage at the second comparison end, it means that the charge stored in the transistor MA1 corresponds to a relatively high data current, and conversely, the charge stored in the transistor MA1. Indicates that the charge corresponds to a relatively low data current. Therefore, in the sensing element SA1, the numerical value stored in the memory cell 11A is "0" (for example, corresponding to a relatively low data current) or "1" (corresponding to a relatively high data current). Can be determined, and the data signal Vrp1 is generated based on such determination.

A flash memory is usually provided with a large number of memory cells and is connected to a node Na1 via a conductive path having a certain distance, and a large capacitance is equivalently formed at the node Na1. If the voltage of the node Na1 (that is, the first comparison terminal N1a) is to be lowered to the steady state by the data current of one memory cell,
It takes a considerable time for the process discharge in the transient state to proceed, for example, the time Ta from the time ta0 to the time ta2 disclosed in FIG. 2a.

One of the drawbacks of the conventional memory 10 is that it is easily affected by a transient state in the process of reading data. As shown in FIG. 2, if an error occurs in the operation of the sensing element SA1 and the voltages are compared at time point ta1, the sensing element S1 is irrelevant regardless of whether the data current provided by the memory cell 11A is high or low.
Since the voltage of the first comparison terminal N1a is higher than the voltage of the second comparison terminal N2a, A1 makes a mistake in determining the data stored in the memory cell 11A.

FIG. 3 is a circuit diagram of a conventional memory 20 according to another aspect. For convenience of explanation, elements and nodes disclosed in FIG. 3 having the same operation, effect, and connection method as those disclosed in FIG. 1 are represented by the same reference numerals. The memory 20 differs from the memory 10 in that an equivalent element 24 is separately provided. The equalization element 24 is connected between the first comparison end N1a and the second comparison end N2a of the sensing element SA1, and is connected to the p-type metal oxide semiconductor transistor Tta.
And an n-type metal oxide semiconductor transistor Ttb and an inverter Ivb3. Both transistors Tta
A transmission gate is formed in each of Ttb and Ttb, and the inverter Ivb3 is adjusted to the control voltage Veq0 to control ON / OFF of the transmission gate.
When the transmission gate is turned on and becomes conductive, the node Na1 and the node Na3 are short-circuited. When the transmission gate is turned off and becomes non-conductive, the node Na1 and the node Na3 are not short-circuited via the equalization element.

Referring to FIG. 3, FIG. 4A will be described below. FIG. 4A is an explanatory diagram showing changes over time in the voltages of the first comparison end N1a and the second comparison end N2a during the time when the memory 20 reads the data. The horizontal axis in the figure represents time, and the vertical axis represents voltage. Curve V (N1a)
L and V (N1a) H represent changes in the voltage of the first comparison terminal N1a under different data currents, and curve V (N2a)
b) represents a voltage change of the second comparison terminal N2a. Further, as in the example of FIG. 2, it is assumed that the memory cell 11A in the memory 20 supplies the data current If1. Memory 20
Is different from the memory 10, when the memory cell 11A is controlled to generate the data current If1 and the transistor TA7 is controlled to generate the reference current Ir1 at the time point ta0, the control voltage Veq0 causes the equalization element 24 to simultaneously operate. The transmission gate of 1 is turned on to make the node conductive, and the node Na1 and the node Na2 are short-circuited together.
Therefore, the voltages at the first comparison end N1a and the second comparison end N2a become equal, and the voltages are changed within the same change width. As in the state from time ta0 to time tb1 in FIG. 2, the curves V (N1a) H << and V (N1b) L >>
And the curve V (N2b) overlap at time Tb1. When reaching the time point tb1, the control voltage Veq0 changes and the transmission gate in the equalization element 24 is turned off and becomes non-conductive. In this case nodes Na1 and Na3
, Without being short-circuited together via the equalizing element 24, the voltage changes individually and finally reaches a steady state.

At time tb2, the sensing element SA1
Can determine what the data stored in the memory cell 11A is based on the voltage difference between the first comparison terminal N1a and the second comparison terminal N2a. That is, the memory 20 controls the equivalent element 24 to match the voltages of the first comparison end N1a and the second comparison end N2a during the transitional state of the voltage change, and the memory 10 determines the data in the transitional state. It is possible to prevent the occurrence of errors.

The sensing element SA1 has a steady state voltage Va.
H, VaL, and the reference voltage VaR in the steady state (see FIGS. 2 and 4).
In order to determine the data stored in the memory cell according to A), the larger the difference between the voltages VaH, VaL and the voltage VaR, the more the sensing element SA1 becomes
The data in the memory cell can be more clearly determined and read, and the margin for reading data is increased. The memory cells have more or less some differences due to manufacturing non-uniformity in the semiconductor manufacturing process. In addition, noise interference occurs during the reading process, and each memory cell is repeatedly programmed (programmed).
m) Since the erasing is performed, the electrical characteristics may change, so that even if the same data is stored in each memory cell, a slight difference occurs in the supplied data current. Furthermore, the steady-state voltages VaH and VaL also differ accordingly. When laying out the memory, if the difference between the ideal steady-state voltages VaH, VaL and VaR is increased,
You can get a bigger margin. Therefore, when actually operating the memory, the voltage V
Even if aH and VaL drift, the memory can read the data correctly.

The steady-state voltages VaH and VaL are the transistors TA1 (FIG. 1, FIG.
3)). Therefore, when laying out the memory, the characteristics of the transistor TA1 can be changed to increase the difference between the voltages VaH and VaL. Generally, in a situation where the data current is fixed, the transistor TA1 has a relatively small aspect ratio (as
If the pect ratio, that is, W / L ratio) is provided, the difference between the purified voltages VaH and VaL also becomes large.

FIG. 4B is an explanatory diagram showing the relationship between the voltage across the transistor Ta1 (horizontal axis) and the current between the source and drain (vertical axis). Transistor T
If a1 is a transistor having a small aspect ratio, the relationship between the current and the voltage is as shown by the curve IV1. If the transistor Ta1 has a large aspect ratio, the relationship between the current and the voltage is as shown by the curve IV2. As described above, if the data stored in the memory cell is different, the supplied data current If1 is also different. The current If1 (H) and the current If1 (L) disclosed in FIG. 4B represent two kinds of different currents supplied by the memory cell. When the currents If1 (H) and If1 (L) are injected into the transistor Ta1, steady-state voltages VaH and VaL are generated, respectively. If the aspect ratio of the transistor TA1 is relatively small, as indicated by the curve IV1, the voltage difference D between the two corresponding steady-state voltages is
V1 also becomes large, and a relatively large number of operation margins can be obtained. However, if the aspect ratio of the transistor TA1 is relatively large under the condition of injecting the same current, the voltage difference DV2 between the steady-state voltages corresponding to the curve IV2 becomes small.

However, as is well known to those skilled in the art, if the aspect ratio of the transistor TA1 is reduced, the current driving capability of the transistor Ta1 is also reduced accordingly. Therefore, the time of the transient state in the reading process also becomes long.
That is, when the memory cell starts supplying the data current, the first
It takes a relatively long time until the voltage at the comparison end becomes low and the voltage at the first comparison end reaches a steady state and data is read (from an equivalent point, the charge accumulated at the node Na1 is discharged). Need more time). Therefore, the memory cannot read data at a high speed, and the efficiency of data access becomes low. Conventional memory 1
In the case of 0 or 20, the layout of the load element (that is, the transistor Ta1) has a problem that it is not possible to combine both the above-mentioned operational margin and the high-speed reading.

[0019]

SUMMARY OF THE INVENTION The present invention has an additional load element for increasing the operational margin and speed of reading, and providing a memory capable of high-speed and accurate reading of data. It is an object to provide a memory and an operation method related to the memory.

[0020]

Therefore, as a result of intensive research conducted by the present inventor in view of the drawbacks of the prior art,
A first comparison end having at least one memory cell having a data end, storing data, and providing a data current at the data end based on the stored data; A sensing element electrically connected to the data end of the memory cell and generating a corresponding data signal based on the voltage difference between the voltage at the first comparison end and the reference current;
A first end having a first end, the first end electrically connected to a first comparison end of the sensing element, and generating a voltage at the first end based on a voltage input to the first end. Load element and second
An end, the second end being electrically connected to the first comparison end of the sensing element to enable or disable, and when enabled, the second end based on the current input to the second end. A second load element for generating a voltage corresponding to the second end and for generating a different voltage corresponding to a different input current, and disabling the input of the current to the second end when disabled. In addition, the present invention has been completed based on such findings in view of the problem that can be solved by the structure of the memory having the features described below.

That is, in the memory, when the memory cell provides a data current, the second load element is enabled first, and the data current is transferred to the first load element via the first comparison terminal. When the second load element is input and the enabled time of the second load element exceeds a predetermined value, the second load element becomes invalid, the data current is input to the first load element, and the second load element is input. The input to the device is stopped, the sensing device generates the data signal based on the voltage difference between the voltage of the first comparison terminal and the reference voltage, and the memory reads the data stored in the memory cell. Second
The load element is disabled and the sensing element
When the data signal is generated based on the voltage difference between the voltage at the comparison terminal and the reference voltage, the voltage at the second terminal is configured to be substantially different from the reference voltage. A memory that solves the problems of the invention is obtained.

The present invention will be described in detail below.

A memory according to claim 1 has a data edge, stores data, and at least one memory cell providing a data current at the data edge based on the stored data, and The first comparison end is electrically connected to the data end of the memory cell, and the corresponding data signal is generated based on the voltage difference between the voltage of the first comparison end and the reference current. A sensing element and a first end,
A first load element having a first end electrically connected to a first comparison end of the sensing element and generating a voltage at the first end based on a voltage input to the first end; and a second end And the second end is electrically connected to the first comparison end of the sensing element to enable or disable, and when enabled, the second end based on the current input to the second end. Two
A second load element for generating a voltage corresponding to the terminal and a different voltage corresponding to a different input current, and stopping the input of the current to the second terminal when it becomes invalid, If the memory cell provides a data current, the second load element is first enabled and the data current is input to the first load element and the second load element via the first comparison terminal, When the enabled time of the second load element exceeds a predetermined value, the second load element becomes invalid, the data current is input to the first load element, and the input to the second load element is stopped, and the sensing is performed. The device generates the data signal based on the voltage difference between the voltage at the first comparison terminal and the reference voltage, the memory reads the data stored in the memory cell, and the second load device becomes ineffective. Sen Ring element, when generating the data signal based on the voltage difference between the voltage and the reference voltage of the first comparison end, the voltage of the second end is configured differently to the reference voltage substantially.

According to another aspect of the memory of the present invention, the sensing element of the first aspect further includes a second comparison end.
The memory separately includes a reference element and a third load element, the reference element has a reference end electrically connected to the second comparison end, and provides a reference current to the reference end. The 3 load element includes a third end electrically connected to the second comparison end, and generates a voltage based on a current input to the third end,
When the second load is disabled, the reference current is the second current.
Is input to the third end of the third load element via the comparison end,
The third load element is configured to generate a reference voltage at the third end.

According to a third aspect of the present invention, the memory according to the second aspect further includes an equalization element connected between the first comparison end and the second comparison end, and the second load element is When enabled, the equalization element shorts the first comparison end and the second comparison end and causes the voltage at the first comparison end to be substantially equal to the voltage at the second comparison end. When the second load element becomes invalid, the equalizing element causes the first comparison end to move to the second
It is configured so as not to short-circuit with the comparison end.

According to a fourth aspect of the present invention, there is provided a memory according to the second aspect, wherein the memory according to the second aspect is electrically connected to the second comparison end.
A fourth load element having an end is separately included, the fourth load element generating a voltage at the fourth end based on a current input to the fourth end, and the second load element being enabled, The reference current passes through the second comparison end to the third load element,
It is configured to be input to the fourth load element.

According to a fifth aspect of the present invention, the memory according to the second aspect is electrically connected between the reference end and the second comparison end, and the reference current flows from the reference end to the second comparison end. It further comprises a load separation element for transmission.

According to a sixth aspect of the present invention, in the memory according to the first aspect, the data current electrically connected between the data end and the first comparison end is supplied from the data end to the first comparison end. It further comprises a load separation element for transmitting to the.

According to a seventh aspect of the present invention, in a memory cell according to the first aspect, the memory cell is a metal oxide semiconductor transistor having a floating gate, a metal oxide semiconductor transistor (SONOS) having an ONO gate, or a mask read-only type. Including memory.

According to an eighth aspect of the present invention, in the memory according to the first aspect, when the voltage at the first end of the first load element becomes equal to the voltage at the second end of the second load element, the first load element has the second voltage. The current input to the first terminal is smaller than the current input to the second input terminal of the second load element.

According to a ninth aspect of the present invention, when the data stored in the memory cell of the first aspect is the first data, the memory cell provides the first data current and is stored in the memory cell. If the data is the second data,
A voltage of a voltage generated by the memory cell providing a second data current, the first data current being input to the first load element, and a voltage generated after the second data power is input. The difference is defined as a first voltage difference, and a voltage difference between a voltage generated after the first data current is input to the second load element and a voltage generated after the second data current is input is expressed as a first voltage difference. The voltage difference is two, and the first voltage difference is larger than the second voltage difference.

The memory according to claim 10 is the memory according to claim 1.
The second load element has a load transistor having a source and a switching transistor electrically connected between the source and the second end, the switching transistor being conductive when the second load element is enabled. The second transistor through the switching transistor.
The current at the end is input to the source, the switching element is turned off when the second load element is disabled, and the current at the second end is not substantially input to the source through the switching transistor. To configure.

A method of operating a memory according to claim 11 is a method of operating a memory for reading or storing data, the memory having a data end, storing the data, and storing the data. At least one memory cell providing a data current at the data end based on the data, and a first end, the first end electrically connected to the data end, and the first end electrically connected to the first end. According to the input voltage, the first
A first load element for generating a voltage at one end, and a second end,
A second load element electrically coupled to the first end to enable or disable the second end, the second load element being enabled when the second load element is enabled. Generates a voltage corresponding to the second end based on the current input to the second end, and generates a different voltage corresponding to a different input current, and when invalid, inputs the current to the second end. And the memory cell provides a data current to the data end and enables the second load element to pass the data current to the first load element and the first load element. 2 load element, and when the enabled time of the second load element exceeds a predetermined value, the second load element becomes invalid and the data current is input to the first load element to 2 The input to the load element is stopped and the first The voltage of the first end of the over-de element,
Determining the data stored in the memory cell based on the reference voltage, disabling the second load element, and sensing the voltage difference between the voltage at the first end and the reference voltage. When the data stored in the memory cell is determined based on, the voltage at the second end is substantially different from the reference voltage.

According to a twelfth aspect of the present invention, there is provided a method of operating a memory, wherein the memory according to the eleventh aspect includes a reference end, and a reference element for providing a reference current to the reference end, and a third end. Further comprises a third load element connected to the reference end and generating a voltage at the third end based on a current input to the third end, and when the second load element is disabled, A reference current is input to the third end, and the third load element is configured to generate a reference voltage at the third end.

According to a thirteenth aspect of the present invention, in a method of operating a memory, when the second load element of the twelfth aspect is enabled, the first end is short-circuited with the third end, and the voltage at the first end is reduced. The method further includes a step of making the voltage substantially equal to the voltage of the third end, and preventing the first end and the third end from being short-circuited when the second load element becomes ineffective.

According to a fourteenth aspect of the present invention, there is provided a method of operating a memory, wherein the memory according to the twelfth aspect is electrically connected between the reference end and the third end, and the reference current flows from the reference end to the third end. And a load separation element for transmitting to the.

According to a fifteenth aspect of the present invention, in the method of operating a memory, the memory according to the eleventh aspect is electrically connected between the data end and the first end, and the data current is transferred from the data end to the first end. The transmission further includes a load separation element.

According to a sixteenth aspect of the present invention, there is provided a method for operating a memory, wherein the memory cell according to the eleventh aspect is a metal oxide semiconductor transistor having a floating gate or an ONO.
Metal oxide semiconductor transistor having a gate (SON
OS) or mask type read-only memory.

According to a seventeenth aspect of the present invention, there is provided a method of operating a memory according to the eleventh aspect, wherein the first load element has a first end voltage equal to a second end voltage of the second load element. The current input to the first end is smaller than the current input to the second end of the second load element.

The method of operating a memory according to claim 18, wherein when the data stored in the memory cell according to claim 11 is the first data, the memory cell provides a first data current to the memory cell. When the stored data is second data, the memory cell provides a second data current, the voltage generated by the first data current being input to the first load element, and the second data power. Is a voltage difference from a voltage generated after the first data current is input, and a voltage generated after the first data current is input to the second load element and the second data current are input. A voltage difference from the voltage generated thereafter is set as a second voltage difference, and the first voltage difference is set to be larger than the second voltage difference.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention relates to a memory for temporarily accelerating a memory by utilizing an additional load element when reading data, and further disabling the load element to secure data read sensitivity and a margin. The method provides the method, and the memory includes at least one or more memory cells, a sensing element, a first load element, and a second load element.

In order to explain the structure of such a memory and the characteristics of its operating method, a specific example will be given and described in detail below with reference to the drawings.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 5 discloses a circuit of the memory 30 according to the present invention. The memory 30 is biased by the DC power supply Vdd. In addition, in FIG. 5 of a plurality of memory cells, when only two memory cells 31A and 31B are disclosed and represented as a representative, load separation elements 32A and 32B, a metal oxide semiconductor transistor M1 to be a first load element, and 2 load element 36A, sensing element SA, equalizing element 34
A third load element, a metal oxide semiconductor transistor M3, a fourth load element 36B, and a reference element, a metal oxide semiconductor transistor M7. The memory cells 31A and 31B are metal oxide semiconductor transistors Mm1 and Mm2 having floating gates, respectively.
Save the data by. Transistors MA1 and MA
2 controls data access to the memory cells 31A and 31B, respectively. The gates of the transistors Mm1 and Mm2 control the bias by control voltages Vm1 and Vm2, respectively. The gates of the transistors MA1 and MA2 are controlled by control voltages VA1 and VA2, respectively. In addition, in the memory cell 31A, the transistor MA1 has one electrode other than the gate, which is the transistor Mm.
1, and the other electrode serves as a data terminal for outputting the current of the memory cell 31A, and is connected to the load separation element 32A and the node N5 via the node Nd1. Similarly, one electrode of the transistor MA2 is connected to the transistor Mm2, and the other electrode is the data end of the memory cell 31B and is connected to the node N5 via the node Nd2. The load separation elements 32A and 32B are each an inverter IV.
1, IV2 by the metal oxide semiconductor transistor M
5, control the gate of M6. The gate of the transistor M7 serving as a reference element is controlled by the control voltage Vc,
The other both poles are connected to the power supply Vdd, one end serves as a reference end, is connected to the load separation element 32B at the node N6, and outputs the reference current IR generated by the transistor M7. The sensing element SA is a differential sensing amplifier and has a first comparison end N1c and a second comparison end N2c,
The data signal VR is generated according to the voltage difference between the two comparison terminals. In the equalizing element 34, the metal oxide film semiconductor transistors Mta and Mtb form a transmission gate, and the control voltage Veq and the inverter IV3 control ON / OFF of the transmission gate. When the transmission gate turns on and conducts, the node N
1 (that is, the first comparison end N1c) and the node N3 (that is, the second comparison end N2c) are short-circuited. On the contrary, when the transmission gate in the equalization element is turned off and there is no conduction, the nodes Na1 and Na3 are not short-circuited. The transistor M1 becomes the first load element and is connected to the diode,
One end is connected to the sensing element SA at the node N1 with the first end, and the other end is connected to the ground end G. Based on a layout similar to this, the transistor M3 is used as a third load element, and one end of the transistor M3 is connected to the sensing element SA at the node N3 with its third end connected to the ground end G.

The structure of the memory 30 according to the present invention is different from that of the conventional memory 20 as follows. That is, the present invention has the first load element and the third load element. Further, a second load element 36A and a fourth load element 36B are separately provided. The second load element 36A is provided with metal oxide semiconductor transistors Msa and M2. The transistor Msa is a switching transistor, the gate of which is similarly controlled by the control voltage Veq, and the other ends of which are connected to the transistor Msa. Then, the other end is connected to the sensing element SA at the node N2 with the second end. The transistor M2 is connected to a diode to become a load transistor, and its source is connected to the transistor Msa. Metal oxide semiconductor transistors Msb and M4 are also provided in the fourth load element. The gate of the transistor Msb serving as a switching transistor is similarly controlled by the control voltage Veq, one end of which is connected to the transistor M4 by a diode connection method, and the other end of which is a fourth end, and is connected to the sensing element SA at the node N4. Connecting. Transistor M4 also becomes a load transistor,
Its source is connected to the transistor Msb. When the switching transistor Msa of the second load element 36A is controlled by the control voltage Veq and becomes conductive, a current flows to the load transistor M2 via the transistor Msa, and the load transistor M2 generates a voltage at the node N2. In this case, the second load element 36A is enabled. The switching transistor is turned off by the control voltage Veq, the second load element 36A becomes invalid, and no current is received from the node N2.
The node N2 is in a high input resistance state. The fourth load element 36B operates similarly.

Similar to conventional memory, memory 30 also comprises a plurality of memory cells, each memory cell storing a charge corresponding to digital data by means of a transistor having a floating gate. Under equal gate bias, transistors with different amounts of charge on their floating gates generate different data currents. The sensing element SA may read the data stored in the memory cell based on the voltage generated in each load element by the data current. For example, when the memory 30 reads the data stored in the memory cell 31A, the control voltages Vm1 and VA1 cause the transistors Mm1 and MA1 of the memory cell 31A to be conductive, respectively. The transistor Mm1 generates the data current If based on the charge amount stored in the floating gate, and the data current If flows to the node N5 via the conductive transistor MA1. In this case, at the same time, the memory 30 also controls the transistor M of the memory cell 31B by the control voltage VA2.
A2 is turned off to bring the memory cell 31A into the non-conductive state.
Do not interfere with the data reading inside.

FIG. 6 will be described below in combination with FIG. FIG. 6 is an explanatory diagram showing changes in the voltages of the first comparison terminal N1c and the second comparison terminal N2c with the passage of time in the process of reading the data of the memory 30. The horizontal axis of the drawing represents time, and the vertical axis represents voltage. Curve V (N1c) H, V
(N1c) L represents the change in the voltage of the first comparison terminal N1c, and the curve V (N2c) represents the change in the voltage of the second comparison terminal N2c. Before the time t0, the reading process has not started, and the first comparison end N1c and the second comparison end N2c
Is charged to a high voltage. At time point ta0, the memory cell 31A supplies the data current If, and the control voltage Vc also controls the transistor M7 to supply the reference current Ir. At the same time, the control voltage Veq also causes the transmission gate of the equalization element 34 to conduct, thereby shorting the nodes N1 and N3. In this case, similarly, the control voltage Veq
Of the switching transistors Msa and Ms under the control of
Both b are conductive and enable the second load element 36A and the fourth load element 36B. Therefore, the control current is applied to the load separation elements 32A and 32B and the nodes N1 and N.
2 through load transistor M2 and transistor M
1 (up to the transistors M3 and M4)
Will be diverted to. This has the same effect as increasing the discharge route, and the first comparison end N1c is changed to the second comparison end N2.
The voltage is rapidly decreased together with the voltage of c, and the steady state is approached as disclosed at time T1 from time t0 to time t1 in FIG. At the time T1, the load separation element 32
The inverters Iv1 and Iv2 in A and 32B also change the bias of the transistors M5 and M6, respectively, and increase the equivalent resistance between the source and drain of both transistors to accelerate the transition process. At time t1, the control voltage Veq changes its voltage value, the transmission gate in the equalizing element 34 is turned off and becomes non-conductive, and at the same time, the switching transistors Msa and Msb in the second and fourth load elements are also conductive. Both load elements become invalid. In this case, the data current If stops flowing in the second load element 36A and flows only in the transistor M1 of the first load element, and finally reaches the steady voltage VH or VL (disclosed in FIG. 6) based on the magnitude of the data current If. Is generated. Similarly, the reference current Ir also stops flowing in the fourth load element 36B, flows only in the transistor M3 of the third load element, and generates a stable reference voltage VR.

At time t2, the sensing element SA
Determines the content of the data stored in the memory cell 31A based on the voltage difference between the first comparison terminal N1c and the second comparison terminal N2c, and generates the corresponding data signal Vr.

Summarizing the above, the spirit of the present invention is the process of the transient state of data reading (time T1 disclosed in FIG. 6).
The purpose is to enable the two load elements 36A and 36B added in 1 to shorten the transient state time.
Immediately before reaching the steady state, the second and fourth load elements 36A,
36B is disabled, and the original load element transistor M1
Generates a steady state voltage of the first comparison terminal N1c.
When the present invention is actually implemented, the transistor M1 uses a transistor having a relatively small aspect ratio, and the load transistor M2 uses a transistor having a relatively large aspect ratio. At time T1, the transistor M2 provides a discharge route having a relatively small resistance (compared to the transistor M1), and further lowers the voltage of the first comparison terminal N1c at a high speed together with the discharge route provided by the transistor M1. The transient time can be shortened.

At time T2 (see FIG. 6) after the time point t1, the second load element 36A becomes ineffective, so that the current cannot be captured, and only the transistor M1 completely operates on the basis of the data current If to determine the steady state. The voltage VH or the steady state voltage VL is generated. As described above, a transistor having a relatively small aspect ratio can generate a relatively large steady-state voltage based on the data current If,
It is possible to increase the memory operation margin. Therefore, in the present invention, on the one hand, the transient state time can be shortened and the reading operation can be accelerated, and on the other hand, a more preferable operation margin can be obtained. If the load transistor M2 of the memory 30 according to the present invention and the load transistor TA1 of the conventional memory 20 are the same,
The same applies to each memory cell and load separation circuit,
The curve V (N1B) L disclosed in FIG. 6 is one of curves representing changes in the voltage of the first comparison terminal N1b of the memory 20.
On the other hand, in the present invention, the transient state is short and the operating margin can be efficiently increased.

FIG. 7 is an explanatory diagram showing a circuit related to the sensing element SA of the memory 30 according to the present invention. In the embodiment, the pair of transistors Q1 and Q2 perform differential input, the transistors Q3 and Q4 serve as a dynamic load, and the transistor Q5 is controlled by the control voltage Vi to serve as a bias current supply source.

[0051]

[Second Embodiment] FIG. 8 is an explanatory diagram showing a circuit of a memory 40 according to a third embodiment of the present invention. According to the drawings, memory 40 includes memory cells 41A and 41B, load isolation elements 42A and 42B, an equalization element 44,
Sensing element Sab, transistor QL1 serving as a first load element, and transistor Q serving as a third load element
L3 and the second load element 46A, and the fourth load element 46
B and a transistor QL7 serving as a reference element. The equalization element 44, the second load element 46A, and the fourth load element 46B are similarly controlled by the control voltage Veq2. In the memory 40 and the memory 30, the memory 30 uses a memory cell as a current source and the load element has a current absorption source (curr).
ent sink) is different. The memory 40 uses a load element as a current source and a memory cell as a current absorption source.
When reading data, the memory 40 first discharges the voltages at both comparison ends of the sensing element Sab to a low potential, and further charges the voltages at both comparison ends to a steady-state potential via a load element. To do. In the charging transient state, the equalization element conducts and shorts both comparison ends. At the same time, the second and fourth load elements are enabled to provide a low resistance charging route, thereby shortening the charging transient process. Finally, the second and fourth load elements are invalidated by turning off the equalization element 44, and the transistors QL1 and QL3 of the load elements finally generate a steady state voltage to sense element Sab.
And sensing the content of the data stored in the memory cell by the sensing element Sab and outputting the data signal VR. The operation of the memory 40 has similar features that shorten the reading process and increase the operational margin, as can be seen from the above description. Therefore, it will not be described in detail here as it does not hinder the disclosure of the technique of the present invention. At the same time, the application of the technology of the present invention to other non-volatile memories (mask type read only memory) or metal oxide semiconductor transistors (SONOS) having ONO gates is based on the spirit of the present invention. It is a thing. In other words, the transistor in each memory cell may be a transistor having a floating gate, as described above, or another form of non-volatile storage transistor. Also,
In the present invention, the p-type transistors M1 to M4 which are the load transistors in FIG.
1, similar to QL3). Similarly, FIG.
As the n-type transistors QL1 and QL3 and the load transistors in the load elements 46A and 46B in FIG. 5, a p-type diode connection type metal oxide semiconductor transistor may be used as in the embodiment disclosed in FIG.

Since the conventional memory provides a charging / discharging route with a single load element, it is impossible to achieve both improvement in reading speed and operational margin. On the contrary, the memory according to the present invention can increase the charge / discharge route in the transient state of the read process and effectively increase the read speed with the dynamically enabled additional load element. Also, at the end of the transient process, the additional load element is disabled and loaded with a transistor with a small aspect ratio, eventually achieving a steady state voltage, increasing operating margin. Therefore, the memory of the present invention can shorten the reading process and obtain the data reading accuracy.

The above is a preferred embodiment of the present invention and does not limit the scope of the present invention. Therefore, a modification or change that can be made by a person skilled in the art,
Anything made under the spirit of this invention and having an equivalent effect on this invention shall belong to the scope of the claims of this invention.

[0054]

As described above, the memory and the operating method thereof according to the present invention can increase the operation margin and the reading speed, and can read data at high speed and accurately.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a structure of a conventional memory.

2 is an explanatory diagram showing a time sequence of a voltage change of a node in the process of reading the memory disclosed in FIG. 1. FIG.

FIG. 3 is a circuit diagram showing the structure of another conventional memory.

4A is an explanatory diagram showing a time sequence of a voltage change of a node in the process of reading the memory disclosed in FIG. 3; FIG.

FIG. 4B is an explanatory diagram illustrating a relationship between current and voltage in the load element disclosed in FIG.

FIG. 5 is a circuit diagram showing a structure of a memory according to the present invention.

FIG. 6 is an explanatory diagram showing a time sequence of a voltage change of a node in the process of reading the memory disclosed in FIG. 5;

FIG. 7 is a circuit diagram showing a structure of a sensing element in an example.

FIG. 8 is a circuit diagram showing a structure of a memory according to a second embodiment.

[Explanation of symbols]

10, 30, 40 Memory SA1, SA, Sab Sensing element 11A, 11B, 31A, 31B, 41A, 41B Memory cell 12A, 12B, 32A, 32B, 42A, 42B Load isolation element 24, 34, 44 Equalization element 36A, 46A 2nd load element 36B, 46B 4th load element Iva1, Iva2, Iva3, Iv1-Iv3 inverter Vrp1, Vr data signal N1a, N1c 1st comparison end N2a, N2c 2nd comparison end If1 data current Ir1 reference current Vdd power supply VaH , VaR, VaL, VH, VR, VL voltage ta0, ta2, tb1, tb2, t1, t2 time point Ta, Tb1, Tb2 time Na1, Na3, Na5, Na6, N1-N6, Nd.
1, Nd2 nodes Ta1, Ta3, Ta5, Ta6, Ta7, TA1, T
A2, Ma1, Ma2, Tta, Ttb, MA1, MA
2, Mm1, Mm2, M1-M7, Mta, Mtb, M
sa, Msb, Q1-Q5, QL1, QL3, QL7 Transistors V (N1b) L, V (N1b) H, V (N2b), V (N
1c) L, V (N1c) H, V (N2c), IV1, IV
2 Curves Vma1, Vma2, Vd1, Vd2, Vca, Veq
0, Vm1, Vm2, VA1, VA2, Vc, Veq,
Vi, Vn1, Vn2, VD1, VD2, Veq2, V
d Control voltage DV1, DV2 voltage difference

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) G11C 17/00 634D

Claims (18)

[Claims] 1. A first comparison terminal having at least one memory cell having a data edge, storing data, and providing a data current at the data edge based on the data to be stored, A sensing element that electrically connects the first comparison terminal to a data terminal of the memory cell and generates a corresponding data signal based on a voltage difference between the voltage of the first comparison terminal and a reference current; A first load element having a first end electrically connected to a first comparison end of the sensing element and generating a voltage at the first end based on a voltage input to the first end. , Having a second end, the second end electrically connected to the first comparison end of the sensing element to enable or disable, and the current input to the second end when enabled. Generate a voltage corresponding to the second end based on the A second load element for generating a different voltage corresponding to the current flow and discontinuing the input of the current to the second end when the voltage is disabled, in the case where the memory cell provides the data current, The second load element is first enabled, the data current is input to the first load element and the second load element via the first comparison terminal, and the enabled time of the second load element is a predetermined value. Is exceeded, the second load element becomes invalid, the data current is input to the first load element, and the input to the second load element is stopped, and the sensing element is set to the first load element.
The data signal is generated based on the voltage difference between the voltage at the comparison end and the reference voltage, the memory reads the data stored in the memory cell, the second load element is disabled, and the sensing element changes the 1. A memory, wherein when a data signal is generated based on a voltage difference between a voltage at one comparison terminal and the reference voltage, a voltage at the second terminal is configured to be substantially different from the reference voltage. 2. The sensing element is further provided with a second comparison end, the memory is provided with a separate reference element and a third load element, and the reference element is electrically connected to the second comparison end. A third end connected to the second reference end, the third load element electrically connected to the second comparison end, and the third load element electrically connected to the second reference end. If a voltage is generated based on the current and the second load is disabled, the reference current is the second current.
Is input to the third end of the third load element via the comparison end,
The memory of claim 1, wherein the third load element is configured to generate a reference voltage at the third end. 3. The memory further includes an equalization element connected between the first comparison end and the second comparison end, and the equalization element is activated when the second load element is enabled. When the first comparison end and the second comparison end are short-circuited and the voltage at the first comparison end is made substantially equal to the voltage at the second comparison end, and the second load element is disabled, the 3. The memory according to claim 2, wherein the memory element is configured to prevent the first comparison end from short-circuiting with the second comparison end. 4. The memory further includes a fourth load element having a fourth end electrically connected to the second comparison end, the fourth load element being adapted to receive a current input to the fourth end. When the second load element is enabled, the reference current is input to the third load element and the fourth load element via the second comparison terminal. The memory according to claim 2, which is configured as follows. 5. The memory further comprises a load separation element electrically connected between the reference end and the second comparison end and transmitting the reference current from the reference end to the second comparison end. The memory according to claim 2, wherein: 6. The memory further comprises a load separation element electrically connected between the data end and the first comparison end for transmitting the data current from the data end to the first comparison end. The memory according to claim 1, wherein the memory is a memory. 7. The memory cell is a metal oxide semiconductor transistor having a floating gate or a metal oxide semiconductor transistor (SONO) having an ONO gate.
The memory of claim 1, including S) or a masked read-only memory. 8. The voltage at the first end of the first load element is
When it becomes equal to the second end voltage of the second load element, the first
The memory according to claim 1, wherein the current input to the first end of the load element is smaller than the current input to the second input end of the second load element. 9. If the data stored in the memory cell is first data, the memory cell provides a first data current, and the data stored in the memory cell is second data. A voltage difference between a voltage generated by the memory cell providing a second data current, the first data current input to the first load element, and a voltage generated after the second data power is input. Is a first voltage difference, and a voltage difference between a voltage generated after the first data current is input to the second load element and a voltage generated after the second data current is input is a second voltage difference. 2. The memory according to claim 1, wherein the memory is configured to have a voltage difference, and the first voltage difference is larger than the second voltage difference. 10. The second load element comprises a load transistor having a source and a switching transistor electrically connected between the source and the second end, wherein the second load element is enabled. , The switching transistor is conductive, the current at the second end is input to the source through the switching transistor, and when the second load element is disabled, the switching element is turned off and the current at the second end is 2. The memory according to claim 1, wherein the memory is configured so as not to be substantially inputted to the source via the switching transistor. 11. A method of operating a memory for reading or storing data, the memory having a data end, storing the data, and storing the data at the data end based on the stored data. At least one memory cell providing a current, and a first end, the first end electrically connected to the data end, and the first end based on a voltage input to the first end. And a second load element having a second end, the second end electrically connected to the first end to enable or disable the first load element. When the second load element is enabled, the second load element generates a voltage corresponding to the second end based on the current input to the second end, and is different corresponding to a different input current. If a voltage is generated and becomes invalid, the The method of operating the memory is configured such that the memory cell provides a data current to the data end and enables the second load element to transfer the data current to the first load element. When the second load element is input to the second load element and the enabled time of the second load element exceeds a predetermined value, the second load element is invalidated and the data current is input to the first load element. The step of stopping the input to the second load element and determining the data stored in the memory cell based on the voltage at the first end of the first load element and the reference voltage. Becomes invalid and the sensing element determines the data stored in the memory cell based on the voltage difference between the voltage at the first end and the reference voltage, the voltage at the second end is substantially equal to the reference voltage. To be different from the voltage Operation method of a memory, characterized by. 12. The memory comprises a reference element having a reference end and providing a reference current to the reference end, and a third end, the third end connected to the reference end, and the third end. A third load element that generates a voltage at the third end based on a current input to the third load element, and when the second load element is disabled, the reference current becomes the third load element.
The third load element is configured to generate a reference voltage at the third end by inputting to the end.
1. A method for operating a memory according to 1. 13. When the second load element is enabled, the first end is shorted to the third end so that the voltage at the first end is substantially equal to the voltage at the third end. 13. The method of operating a memory according to claim 12, further comprising the step of preventing the first end and the third end from being short-circuited when the second load element becomes ineffective. 14. The memory further comprises a load separation element electrically connected between the reference end and the third end and transmitting the reference current from the reference end to the third end. The method of operating a memory according to claim 12. 15. The memory further comprises a load separation element electrically connected between the data end and the first end and transmitting the data current from the data end to the first end. The method for operating a memory according to claim 11, wherein 16. The memory cell is a metal oxide semiconductor transistor having a floating gate or an ONO.
Metal oxide semiconductor transistor having a gate (SON
12. The method for operating a memory according to claim 11, further comprising an OS) or a mask type read only memory. 17. If the first end voltage of the first load element is equal to the second end voltage of the second load element, the first end voltage is equal to the first end voltage.
12. The method of operating a memory according to claim 11, wherein the current input to the first end of the load element is smaller than the current input to the second end of the second load element. 18. If the data stored in the memory cell is first data, the memory cell provides a first data current, and if the data stored in the memory cell is second data, the data is stored in the memory cell. A voltage difference between a voltage generated by the memory cell providing a second data current, the first data current input to the first load element, and a voltage generated after the second data power is input. Is a first voltage difference, and a voltage difference between a voltage generated after the first data current is input to the second load element and a voltage generated after the second data current is input is a second voltage difference. 12. The method of operating a memory according to claim 11, wherein the voltage difference is used, and the first voltage difference is larger than the second voltage difference.