KR100695438B1 - Method for fabricating the same of semiconductor device - Google Patents

Method for fabricating the same of semiconductor device Download PDF

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Publication number
KR100695438B1
KR100695438B1 KR1020060038729A KR20060038729A KR100695438B1 KR 100695438 B1 KR100695438 B1 KR 100695438B1 KR 1020060038729 A KR1020060038729 A KR 1020060038729A KR 20060038729 A KR20060038729 A KR 20060038729A KR 100695438 B1 KR100695438 B1 KR 100695438B1
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South Korea
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dry etching
semiconductor device
manufacturing
etching
photoresist
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KR1020060038729A
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Korean (ko)
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김승범
임병혁
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/427—Stripping or agents therefor using plasma means only
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Abstract

A method for manufacturing a semiconductor device is provided to remove scum and to improve the reliability of the device by improving the margin of a photoresist mask process and securing the uniformity of a photoresist pattern using two-step dry etching processes. A plurality of line patterns are formed on a semiconductor substrate(31). A photoresist layer is coated on the entire surface of the resultant structure. A photoresist pattern(34d) for exposing a predetermined portion of the substrate to the outside is formed on the resultant structure by exposing and developing the photoresist layer. Two-step dry etching processes are performed on the resultant structure in order to remove scum.

Description

반도체 소자의 제조방법{METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE}

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 마스크공정을 설명하기 위한 평면도와 TEM사진,1A to 1C are plan views and TEM photographs for explaining a mask process of a semiconductor device according to the prior art;

도 2a는 도 1c의 단면을 설명하기 위한 TEM사진, 도 2b는 종래 기술에 따른 반도체 소자를 설명하기 위한 TEM사진,FIG. 2A is a TEM photograph for explaining the cross section of FIG. 1C, FIG. 2B is a TEM photograph for explaining a semiconductor device according to the prior art;

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도,3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention;

도 4a 내지 도 4c는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 TEM사진.4A to 4C are TEM photographs for explaining a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

31 : 반도체 기판 32 : 소자분리막31 semiconductor substrate 32 device isolation film

33 : 게이트패턴 34,34a,34b,34c,34d : 감광막33: gate pattern 34,34a, 34b, 34c, 34d: photosensitive film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 감광막 스컴을 제거하기 위한 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for removing a photosensitive film scum.

반도체 소자가 고집적화되면서 게이트패턴 등 패턴간의 간격이 좁아지고 있다. 또한, 식각을 위한 마스크패턴 형성시 패터닝이 어려워지고, 식각마진이 증가하여 식각이 어려워졌다. 특히, 패턴사이에 이온주입을 하기위한 마스크공정시 패턴간의 간격이 좁아져서 패턴사이에 형성된 마스크를 완전히 제거하여 패턴사이를 오픈시키기 어렵다.As semiconductor devices are highly integrated, gaps between patterns such as gate patterns are narrowing. In addition, when forming a mask pattern for etching, patterning becomes difficult, and etching margins increase, making etching difficult. In particular, during the mask process for ion implantation between the patterns is narrow the gap between the patterns it is difficult to completely remove the mask formed between the patterns to open between the patterns.

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 제조방법을 설명하기 위한 평면도와 TEM사진이다. 도 1a는 감광막패턴을 형성하기 전의 평면도, 도 1b와 도 1c는 감광막패턴을 형성한 후의 평면도와 TEM사진이다.1A to 1C are plan and TEM photographs illustrating a method of manufacturing a semiconductor device according to the prior art. 1A is a plan view before forming the photoresist pattern, and FIGS. 1B and 1C are plan views and TEM photographs after the formation of the photoresist pattern.

도 1a에 도시된 바와 같이, 반도체 기판(11)에 소자분리막(12)을 형성하여 활성영역(11a)을 정의한다. As shown in FIG. 1A, an isolation region 12 is formed on a semiconductor substrate 11 to define an active region 11a.

이어서, 반도체 기판(11) 상에 활성영역(11a)을 지나는 라인패턴의 게이트패턴(13)을 형성한다.Subsequently, a gate pattern 13 having a line pattern passing through the active region 11a is formed on the semiconductor substrate 11.

도 1b와 도 1c에 도시된 바와 같이, 반도체 기판(11) 상의 게이트패턴(13) 사이에 감광막패턴(14)을 형성한다. 여기서, 감광막패턴(14)은 게이트패턴(13) 사이를 채울때까지 감광막을 형성한 후, 노광 및 현상으로 이온주입 예정지역을 오픈시켜서 형성한다. 이를 셀할로(Cell-HALO)공정 이라고 한다.As shown in FIGS. 1B and 1C, a photosensitive film pattern 14 is formed between the gate patterns 13 on the semiconductor substrate 11. Here, the photoresist pattern 14 is formed by forming the photoresist layer until the gap between the gate patterns 13 is filled, and then opening the ion implantation scheduled region by exposure and development. This is called the Cell-HALO process.

도 2a는 도 1c의 단면을 설명하기 위한 TEM사진, 도 2b는 종래 기술에 따른 반도체 소자를 설명하기 위한 TEM사진이다.2A is a TEM photograph for explaining the cross section of FIG. 1C, and FIG. 2B is a TEM photograph for explaining a semiconductor device according to the prior art.

도 2a에 도시된 바와 같이, 게이트패턴(13) 사이에 감광막패턴(14)이 모두 제거되지 않고 잔류하여 스컴(SCUM, 14a)이 형성된다.As shown in FIG. 2A, all of the photoresist pattern 14 is not removed between the gate patterns 13 to form scums SCAM 14a.

도 2b에 도시된 바와 같이, 일반 스트리퍼(Stripper)장비에서 진행 시 균일도(Uniformity) 불량으로 인해 게이트패턴(13) 사이에 감광막패턴(14)이 이온주입배리어로 존재해야할 부분에 두께가 낮은 곳(14b), 즉 감광막패턴(14)의 두께가 1600Å만 존재하는 곳이 발생된다. As shown in FIG. 2B, where the photoresist pattern 14 should be present as an ion implantation barrier between the gate patterns 13 due to poor uniformity during progress in a general stripper device (FIG. 14b), i.e., where the thickness of the photosensitive film pattern 14 is only 1600 Å occurs.

위와 같이, 종래 기술은 게이트패턴(13) 사이에 이온주입을 하기 위해서 감광막을 형성한 후, 노광 및 현상으로 게이트패턴(13) 사이가 오픈되도록 패터닝을 하였다. 일반적으로 이온주입 배리어를 하기 위한 감광막패턴(14)의 두께는 적어도 2500Å이상이 되어야 한다. As described above, in the prior art, after forming a photosensitive film for ion implantation between the gate patterns 13, patterning is performed so that the gate patterns 13 are opened by exposure and development. In general, the thickness of the photosensitive film pattern 14 for the ion implantation barrier should be at least 2500 kPa.

그러나, 종래기술은 게이트패턴(13) 사이에 감광막패턴(14)이 모두 제거되지 않고 스컴(14a)이 발생하여 후속 이온주입시 불순물이 제대로 주입되지 않는 문제점이 있다. However, the prior art has a problem in that scum 14a is generated without removing all of the photoresist pattern 14 between the gate patterns 13, and impurities are not properly implanted during subsequent ion implantation.

또한, 일반 스트리퍼 장비에서 패터닝 진행시 특정 부분의 과다한 감광막패턴(14)의 손실이 발생하여 이온주입배리어로 사용하기 위한 2500Å에 못미치는 1600Å만이 존재하여 이온주입배리어 역할을 하지 못하는 문제점이 있다.In addition, there is a problem that the loss of the excess photoresist pattern 14 of a specific portion occurs during the patterning process in the general stripper equipment, so that there is only 1600 Å which is less than 2500 사용 for use as an ion implantation barrier, and thus does not serve as an ion implantation barrier.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 감광막패턴이 모두 제거되지 않고 스컴이 잔류하여 후속 이온주입을 방해하고, 또한 일반 스트리퍼 장비의 균일도 불량으로 이온주입배리어를 하기위한 높이에 못미치는 감광막패턴의 손실이 발생하는 것을 방지하기 위한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, the photoresist pattern is not removed all the scum remains to prevent subsequent ion implantation, and also the height for the ion implantation barrier due to poor uniformity of general stripper equipment An object of the present invention is to provide a method for manufacturing a semiconductor device for preventing the loss of photoresist pattern less than that.

본 발명은 반도체 기판 상에 복수의 라인패턴을 형성하는 단계, 상기 라인패턴을 포함한 전면에 감광막을 도포하는 단계, 노광 및 현상을 통해 상기 반도체 기판의 소정 표면을 오픈시키는 감광막패턴을 형성하는 단계, 상기 감광막패턴 형성시 발생된 스컴을 제거하기 위해 두번의 건식식각을 차례로 진행하는 단계를 포함한다.The present invention includes forming a plurality of line patterns on a semiconductor substrate, applying a photoresist film to the entire surface including the line patterns, forming a photoresist pattern for opening a predetermined surface of the semiconductor substrate through exposure and development, In order to remove the scum generated during the formation of the photosensitive film pattern includes the step of performing two dry etching in sequence.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

도 4a 내지 도 4c는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 TEM사진이다. 설명의 편의를 위해 도 3a 내지 도 3d와 도 4a 내지 도 4c를 함께 제시하여 설명하기로 한다.4A to 4C are TEM photographs for describing a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention. For convenience of description, FIGS. 3A to 3D and 4A to 4C will be described together.

도 3a에 도시된 바와 같이, 반도체 기판(31)에 소자분리막(32)을 형성한다. 여기서, 소자분리막(32)은 활성영역을 정의하기 위한 것으로, 반도체 기판(31)을 소정 식각하여 트렌치를 형성하고, 트렌치에 절연막을 매립하여 형성한다.As shown in FIG. 3A, an isolation layer 32 is formed on the semiconductor substrate 31. In this case, the device isolation layer 32 is used to define an active region, and the semiconductor substrate 31 is etched to form a trench, and an insulating film is embedded in the trench.

이어서, 반도체 기판(31) 상에 복수의 게이트패턴(33)을 형성한다. 여기서, 게이트패턴(33)은 폴리실리콘전극, 메탈전극과 게이트하드마스크질화막이 순차로 적층된 구조로 형성한다.Subsequently, a plurality of gate patterns 33 are formed on the semiconductor substrate 31. Here, the gate pattern 33 is formed in a structure in which a polysilicon electrode, a metal electrode, and a gate hard mask nitride film are sequentially stacked.

이어서, 게이트패턴(33) 사이를 채우면서 게이트패턴(33) 상부에 감광막(34)을 형성한다. Subsequently, the photoresist layer 34 is formed on the gate pattern 33 while filling the gate pattern 33.

도 3b와 도 4a에 도시된 바와 같이, 감광막(34)을 노광 및 현상으로 패터닝하여 게이트패턴(33) 사이 이온주입예정지역(바람직하게는, 셀할로(Cell-HALO) 이온주입예정지역)을 오픈시킨다. 3B and 4A, the photosensitive film 34 is patterned by exposure and development to form an ion implantation scheduled region (preferably, a cell-halo ion implantation region) between the gate patterns 33. Open it.

따라서, 이온주입 예정외지역엔 이온주입배리어 역할을 하기 위한 감광막배리어(34a)가 잔류한다. 그러나, 이때 이온주입예정지역에 모두 제거되어야 할 감광막(34)도 마진이 부족하여 모두 제거되지 않고 잔류하는 스컴(34b)이 발생한다.Therefore, the photosensitive film barrier 34a for acting as an ion implantation barrier remains in the region outside the scheduled ion implantation. However, at this time, the photoresist film 34, which should be removed at all of the ion implantation scheduled regions, also lacks a margin, and thus the scum 34b is left without being removed.

위와 같이, 게이트패턴(33) 사이가 좁아지면서 마진이 부족하여 모두 제거되지 못하고 잔류하는 스컴(34b)에 의해 후속 이온주입공정에서 이온주입이 잘되지 않는 문제점이 발생한다.As described above, there is a problem that the ion implantation is not performed well in the subsequent ion implantation process due to the scum 34b remaining after the gate pattern 33 is narrowed and the margins are insufficient.

본 발명은 스컴(34b)을 제거하기위해 통상적인 스트리퍼(Stripper)장비를 사용하지 않고 플라즈마 장비를 사용하여 두번의 건식식각을 차례로 실시한다. 설명의 편의를 위해 도 3c와 도 3d로 나누어 설명하기로 한다.In order to remove the scum 34b, the present invention performs two dry etchings in sequence using plasma equipment without using a conventional stripper equipment. For convenience of explanation, the description will be made by dividing into FIGS. 3C and 3D.

먼저, 도 3c와 도 4b에 도시된 바와 같이, 스컴(34b)을 제거하기 위해 제1건식식각을 실시하되, 이방성건식식각을 실시한다. First, as shown in FIGS. 3C and 4B, the first dry etching is performed to remove the scum 34b, but the anisotropic dry etching is performed.

여기서, 제1건식식각은 이온주입배리어로 잔류하는 감광막배리어(34a)의 모서리(edge)부분이 게이트패턴(33)의 어깨부와 만나기직전까지 즉, 게이트패턴(33)의 측벽이 드러나지 않는 범위까지 실시한다(34c). Here, the first dry etching is a range in which the edge portion of the photoresist barrier 34a remaining as the ion implantation barrier is just before the shoulder portion of the gate pattern 33 is met, that is, the sidewall of the gate pattern 33 is not exposed. Until 34c.

상기 제1건식식각은 CCP(Capacitively Coupled Plasma), ICP(Inductively Coupled Plasma), MERIE(Magnetically Enhanced Reactive Ion Beam Etching), ECR(Electron Cyclotron Resonance) 및 마이크로웨이브(Microwave) 소스로 구성된 그룹 중에서 선택된 어느 하나의 플라즈마 장비에서 실시하되, 5mT∼20mT의 저압력, 100Ｗ∼500Ｗ의 소스파워를 인가하고 바이어스파워는 인가하지 않거나, 적어도 100Ｗ가 넘지 않도록, 즉 0Ｗ∼100Ｗ의 바텀파워를 인가하여 실시한다. 또한, 산소가스를 50sccm∼200sccm의 유량으로 플로우하여 실시한다. The first dry etching is any one selected from the group consisting of Capacitively Coupled Plasma (CCP), Inductively Coupled Plasma (ICP), Magnetically Enhanced Reactive Ion Beam Etching (MERIE), Electron Cyclotron Resonance (ECR), and Microwave (Microwave) sources. In a plasma apparatus of 5 mT to 20 mT, a source power of 100 mW to 500 mW, and no bias power or at least 100 mW, that is, a bottom power of 0 mW to 100 mW. Further, the oxygen gas is flowed at a flow rate of 50 sccm to 200 sccm.

위와같이, 저압을 사용하면 이방성식각특성을 보인다. As above, the use of low pressure shows anisotropic etching characteristics.

도 3d와 도 4c에 도시된 바와 같이, 제2건식식각을 실시하되, 등방성건식식각을 실시한다. 여기서, 제2건식식각은 과도식각으로 실시하되, 과도식각의 타겟은 50％∼200％로 한다.As shown in FIGS. 3D and 4C, the second dry etching is performed, but isotropic dry etching is performed. Here, the second dry etching is performed by transient etching, but the target of the transient etching is 50% to 200%.

상기 제2건식식각은 제1건식식각과 동일한 챔버에서 연속으로 실시하되, 제1건식식각보다 더 높은 압력으로 실시한다. 즉, CCP, ICP, MERIE, ECR 및 마이크로웨이브 소스로 구성된 그룹 중에서 선택된 어느 하나의 플라즈마 장비에서 실시하되, 30mT∼100mT의 고압력, 100Ｗ∼500Ｗ의 소스파워를 인가하고 바이어스파워는 인가하지 않거나, 적어도 100Ｗ가 넘지 않도록, 즉 0Ｗ∼100Ｗ의 바텀파워를 인가하여 실시한다. 또한, 산소가스를 50sccm∼200sccm의 유량으로 플로우하여 실시한다. The second dry etching is performed continuously in the same chamber as the first dry etching, but at a higher pressure than the first dry etching. That is, it is performed in any one of the plasma equipment selected from the group consisting of CCP, ICP, MERIE, ECR, and microwave source, high pressure of 30mT ~ 100mT, source power of 100kW ~ 500kW, but not bias power, or at least Do not exceed 100 kW, that is, apply a bottom power of 0 kW to 100 kW. Further, the oxygen gas is flowed at a flow rate of 50 sccm to 200 sccm.

위와 같이, 고압을 사용하면 등방성식각특성을 나타낸다.As above, the use of high pressure shows isotropic etching characteristics.

상기 제1,2건식식각으로 인해 이온주입배리어로 사용하기 위한 감광막은 34, 34a, 34c, 34d로 프로파일이 변화되지만 제2건식식각이 끝난후 게이트패턴(33)의 표면보다 약간 낮은 깊이로 잔류(34d)하기 때문에 후속 이온주입시 충분한 배리어역할이 가능하고, 과도식각까지 추가로 실시하기 때문에 스컴(34b)이 완전히 제거되어 후속 이온주입을 방해하지 않는다.The photoresist film for use as an ion implantation barrier is changed to 34, 34a, 34c, 34d due to the first and second dry etching, but remains at a depth slightly lower than the surface of the gate pattern 33 after the second dry etching is finished. (34d), a sufficient barrier role is possible in the subsequent ion implantation, and the scum 34b is completely removed because the additional etching is performed further, so that subsequent ion implantation is not prevented.

또한, 바이어스 파워를 인가하지 않거나 적어도 100Ｗ이하의 낮은 파워를 인감으로써 등방성식각특성이 더 부각되어 감광막의 제거를 용이하게 한다. 이는, 바텀파워를 크게하면 게이트패턴(33) 하부의 게이트절연막(도시생략)에 어택(Attack)을 주어 손상되기 때문이다.In addition, by applying a bias power or by sealing a low power of at least 100 kW or less, the isotropic etching characteristic is further highlighted to facilitate the removal of the photoresist film. This is because if the bottom power is increased, an attack is applied to the gate insulating film (not shown) under the gate pattern 33 and is damaged.

상기한 본 발명은, 감광막 패터닝 후 잔류하는 스컴을 제거하기 위한 2단계의 이방성, 등방성건식식각을 실시함으로써 스컴을 완전히 제거하여 후속 이온주입시 방해받는 것을 방지하는 장점이 있다.The present invention described above has the advantage of preventing the interference during subsequent ion implantation by completely removing the scum by performing two-step anisotropic and isotropic dry etching to remove the scum remaining after the photoresist patterning.

또한, 이온주입 예정외 지역에는 충분한 높이의 감광막을 잔류시켜서 장비의 균일도 불량으로 인해 특정부분에 감광막의 높이가 너무 낮아서 배리어 역할이 부족되는 문제를 방지함으로써 이온주입 예정외지역에는 배리어 역할을 충분히 할 수 있는 장점이 있다.In addition, the photoresist film of sufficient height is left in the region not scheduled for ion implantation, and the height of the photoresist film is too low in a certain part due to poor uniformity of the equipment to prevent the problem that the barrier role is insufficient. There are advantages to it.

또한, 본 발명은 설명의 편의를 위해 게이트패턴 형성 후 실시하는 셀할로 이온주입으로 설명하였지만, 본 발명의 바람직한 실시예는 감광막으로 마스크공정 후 스컴을 제거하는 모든 공정에서 적용 가능하다.In addition, the present invention has been described as a cell halo ion implantation performed after the formation of the gate pattern for convenience of description, but the preferred embodiment of the present invention is applicable to all processes of removing scum after the mask process with a photosensitive film.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의한 반도체 소자의 제조방법은 소자의 고집적화에 대한 감광막 마스크공정의 마진을 향상하여 스컴을 제거하고, 감광막패턴의 균일도를 확보하여 소자의 신뢰성을 향상시키는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention as described above has the effect of improving the margin of the photoresist mask process for high integration of the device, eliminating scum, and ensuring the uniformity of the photoresist pattern, thereby improving the reliability of the device.

Claims (10)

반도체 기판 상에 복수의 라인패턴을 형성하는 단계;Forming a plurality of line patterns on the semiconductor substrate; 상기 라인패턴을 포함한 전면에 감광막을 도포하는 단계;Coating a photoresist on the entire surface including the line pattern; 노광 및 현상을 통해 상기 반도체 기판의 소정 표면을 오픈시키는 감광막패턴을 형성하는 단계; 및Forming a photoresist pattern for opening a predetermined surface of the semiconductor substrate through exposure and development; And 상기 감광막패턴 형성시 발생된 스컴을 제거하기 위해 두번의 건식식각을 차례로 진행하는 단계Sequentially performing two dry etching processes to remove scums generated when the photoresist pattern is formed. 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 스컴을 제거하는 단계에서,In the step of removing the scum, 상기 두번의 건식식각은 동일한 플라즈마 식각장비에서 서로 다른 압력으로 차례로 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.Wherein the two dry etching is a semiconductor device manufacturing method, characterized in that to proceed in sequence at different pressures in the same plasma etching equipment. 제2항에 있어서, The method of claim 2, 상기 두번의 건식식각은,The two dry etchings, 제1압력하에서 이방성식각의 제1건식식각을 진행하는 단계; 및Performing a first dry etching of the anisotropic etching under the first pressure; And 상기 제1압력보다 높은 고압의 제2압력하에서 등방성식각의 제2건식식각을 진행하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.And performing the second dry etching of the isotropic etching under the second pressure of the high pressure higher than the first pressure. 제3항에 있어서,The method of claim 3, 상기 제1압력은 5mT∼20mT, 상기 제2압력은 30mT∼100mT로 가하는 것을 특징으로 하는 반도체 소자의 제조방법.The first pressure is 5mT ~ 20mT, the second pressure is 30mT ~ 100mT The manufacturing method of a semiconductor device. 제3항에 있어서,The method of claim 3, 상기 제1건식식각은 상기 감광막패턴의 모서리(edge)부분이 라인패턴의 어깨부와 만나기직전까지 즉, 라인패턴의 측벽이 드러나지 않는 범위까지를 타겟으로 하여 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The first dry etching is performed until the edge portion of the photoresist pattern meets the shoulder portion of the line pattern, that is, to the extent that sidewalls of the line pattern are not exposed. Way. 제3항에 있어서,The method of claim 3, 상기 제2건식식각은 과도식각으로 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The second dry etching is a method of manufacturing a semiconductor device, characterized in that to proceed with the transient etching. 제6항에 있어서,The method of claim 6, 상기 제2건식식각시 과도식각의 타겟은 50％∼200％로 하는 것을 특징으로 하는 반도체 소자의 제조방법.The target of the transient etching during the second dry etching is a method of manufacturing a semiconductor device, characterized in that 50% to 200%. 제3항 내지 제7항 중 어느 한 항에 있어서,The method according to any one of claims 3 to 7, 상기 제1,2건식식각은 CCP, ICP, MERIE, ECR 및 마이크로웨이브로 구성된 그룹 중에서 선택된 어느 하나의 플라즈마 장비에서 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The first and second dry etching is a method of manufacturing a semiconductor device, characterized in that performed in any one of the plasma equipment selected from the group consisting of CCP, ICP, MERIE, ECR and microwave. 제8항에 있어서,The method of claim 8, 상기 제1건식식각은 100Ｗ∼500Ｗ의 소스파워, 0Ｗ∼100Ｗ의 바텀파워, 산소를 50sccm∼200sccm으로 플로우하여 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The first dry etching is a method of manufacturing a semiconductor device, characterized in that the source power of 100 kPa to 500 kPa, bottom power of 0 kPa to 100 kPa, oxygen flows from 50sccm to 200sccm. 제8항에 있어서,The method of claim 8, 상기 제2건식식각은 100Ｗ∼500Ｗ의 소스파워, 0Ｗ∼100Ｗ의 바텀파워, 산소를 50sccm∼200sccm으로 플로우하여 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The second dry etching is a method of manufacturing a semiconductor device, characterized in that the source power of 100 ~ 500 kHz, bottom power of 0 ~ 100 kHz, oxygen flows from 50sccm to 200sccm.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227873A (en) * 1995-02-21 1996-09-03 Nec Corp Manufacture of semiconductor device
US6562726B1 (en) 1999-06-29 2003-05-13 Micron Technology, Inc. Acid blend for removing etch residue
KR20050079743A (en) * 2004-02-06 2005-08-11 주식회사 하이닉스반도체 Method for forming fine pattern of semiconductor device
KR20060000873A (en) * 2004-06-30 2006-01-06 주식회사 하이닉스반도체 Method of manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227873A (en) * 1995-02-21 1996-09-03 Nec Corp Manufacture of semiconductor device
US6562726B1 (en) 1999-06-29 2003-05-13 Micron Technology, Inc. Acid blend for removing etch residue
KR20050079743A (en) * 2004-02-06 2005-08-11 주식회사 하이닉스반도체 Method for forming fine pattern of semiconductor device
KR20060000873A (en) * 2004-06-30 2006-01-06 주식회사 하이닉스반도체 Method of manufacturing semiconductor device

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