KR100693420B1 - Video Display System and Method supporting CMOS Sensor - Google Patents

Abstract

 The present invention relates to a CMOS sensor-assisted image display apparatus, comprising: at least two or more memories in which image data output from a sensor is stored, and which memory is to be stored in which the output image data is stored; An image controller for storing image data, and an interface for transmitting the stored image data to a monitor of a computer.

CMOS, USB, SDRAM, Camera, Video

Description

CMOS display and video display device and method {Video Display System and Method supporting CMOS Sensor}

1 is a general sensor image test method.

2 is an 8M image sensor test method according to an embodiment of the present invention.

3 is a general sensor image structure.

4 is a method for generating VSYNC for each manufacturer.

5 is a rising edge polarity according to an embodiment of the present invention

6 is a falling edge polarity according to an embodiment of the present invention.

7 is a frame rate increasing method according to an embodiment of the present invention.

8 is a ping-pong method for transmitting a sensor image according to an embodiment of the present invention;

{Description of symbols for main parts of the drawing}

200 sensor 201 image control unit

202: memory 203: USB interface

204: Computer

The present invention relates to an image display apparatus and method for supporting a CMOS sensor, and recently, many devices for testing an image of a sensor while attaching a CMOS sensor to a mobile phone have been manufactured. The present invention relates to an apparatus and method capable of displaying images of 8M sensors including 1M images.

The camera function is recognized as one of the most important functions of the current mobile phone.

When a consumer wants to buy a mobile phone, the camera function is already an important part of not only the mobile phone but also other mobile products, so that the performance of the camera determines the consumer's desire to purchase. The core product of the camera module is a CMOS or CCD sensor. In order to test the output image of the sensor, it must be transmitted so that distortion does not occur in the process of transmitting the output image of the sensor. Through this process, the output image of the sensor can be correctly tested.

In addition, in order to test the image quality of the sensor, the image quality of the sensor cannot be tested on the small LCD screen as in a mobile phone, and the quality of each output of the sensor, for example, VGA, XVGA, SVGA or UXGA, etc. It should be displayed on the monitor so that the specific pixel of the sensor can be detected.

However, the existing test equipment can only support VGA and XGA (300,000 or 1 million pixels) pixels because of the limitation of USB 1.0, that is, the data transfer rate through USB 1.0 is 12Mbps. The limitations of USB 1.0 also make it difficult for frame rates to exceed 30 frames per second. As a result, even if the sensor's output image exceeds 30 frames, the frame rate that the test engineer sees on the monitor is reduced, which also prevents the internal problem of the sensor from being tested during the test.

Therefore, as the development speed of the image sensor rapidly develops, a method for delivering an image sensor quality to cope with this needs to be developed.

The present invention has been made to solve the above problems, the object of the present invention is to support a variety of sensors, to increase the frame rate to the maximum, and a display device and method capable of supporting test from VGA to 8M sensor To provide.

The CMOS sensor-assisted image display apparatus of the present invention determines at least two or more memories in which image data output from a sensor is stored, in which memory the output image data is stored, and stores the image data in the determined memory. And an interface for transmitting the stored image data to a monitor of a computer.

In the present invention, it is preferable that the display device further includes a register for setting the number of HSs.

In the present invention, the memory preferably uses SDRAM.

In the present invention, it is preferable that the interface uses a universal serial bus (USB) 2.0.

The CMOS sensor-assisted image display method of the present invention comprises the steps of sequentially storing the image data output from the sensor to at least two memories through the image control unit; And transmitting the image data to the monitor of the computer through a predetermined interface when the image data is stored in the memory.

In the method of storing image data in the memory in the present invention, it is preferable to recognize the number of HSs of the sensors in advance, count the number of HSs in advance, and then generate and store the internal VS.

In the present invention, it is preferable that the interface can select the polarity of the sensor.

 Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In adding reference numerals to the components of the following drawings, the same components only have the same reference numerals as much as possible even if displayed on different drawings, it is determined that may unnecessarily obscure the subject matter of the present invention Detailed descriptions of well-known functions and configurations will be omitted.

2 is a connection diagram showing an 8M image sensor testing apparatus according to an embodiment of the present invention.

In this embodiment, the 8M image sensor testing device includes an image control unit, SDAM, USB, and computer.

Referring to FIG. 2, the output of the sensor is stored using an image controller and two 256M SDRAMs of the output of the sensor. The reason why there are two 256 SDRAMs is that the image of the sensor is stored in one SDRAM, and then the next image is stored in another SDRAM. Send to the monitor. USB2.0 supports 480Mbps of bandwidth, resulting in the best frame rate.

First, one of the most important features in the sensor I / F section is 'Internal Global Virtual VSYNC Generation'. Sensor I / F manufactured by sensor manufacturer does not have international standard, and there are various sensor I / Fs with different interfaces for each sensor manufacturer. In order to support these various sensor I / F, it is the concept of 'Internal Global Virtual VSYNC' that finds and supports common denominator for each sensor. The basic concept starts from the following point of view.

3 is a schematic diagram showing how one image is constructed. In general, when we say 640x480 image, it means that the image line of the image viewer area shown in FIG. 3 is composed of 640 lines, and one image line is composed of 480 pixels. However, here, we can see that there are H blank areas and V blank areas in addition to the image area seen by the user. First, the H blank area is a dummy space existing between one image line and one image line, and typically has a period of about 10 cycles, which varies slightly from company to company.

Next is the V blank area. These two concepts are common to all sensors. The V blank region refers to the space between one frame and the next one. This period also varies slightly from sensor to sensor, but usually requires two to three lines.

Referring to FIG. 4, in general, after the VSYNC signal is activated, HSYNC is generated, and the data of the image viewer area shown in FIG. 3 is output in the period where HSYNC is high. However, the problem is that the active time of the VSYNC existing between one frame and the next one is slightly different from each other. A company may activate VSYNC immediately after the last HSYNC of the previous frame is output, and another company's VSYNC generation may be activated just before the first HSYNC of the next frame is activated.

However, the concept introduced to support these various sensors is 'Global Virtual VSYNC'. As can be seen in Figure 4 it can be seen that the position of the VS is variable according to the type of sensor. Accordingly, the number of HSs of the sensors is recognized in advance in order to correspond to the position of the variable VS. Also, the period from the last HS polling edge of the previous screen to the rising edge of the HS of the next screen should be at least 1024 clocks based on the FPGA main clock. If the above two assumptions are met, the host sets a register (8 bits * 2) to set the number of HSs, and if the above two assumptions are met, the host counts the number of HSs internally and then internal VS. To support various sensors.

Another feature in the sensor I / F section is the ability to select the polarity of the sensor.

5 is a rising edge portion of a clock for explaining the rising polarity and latching the input data. 6 is a part for explaining the falling edge polarity. The latch of the incoming data is performed at the falling edge of the clock. To support both, it has an internal register that allows the host to select the polarity. That is, when the polarity register is 1, the rising edge may be selected, and when the polarity register is 0, the falling edge may be selected.

The following is the MCU I / F part. MCU I / F part is supported for host and interface. That is, this part is for supporting a host to read or write the internal register of the image controller. Another important feature here is how to increase the maximum frame rate by separating the clock used for the MCU I / F and the clock delivered to USB 2.0 to increase the plane rate delivered to the host.

In general, the interface between USB 2.0 and the image sensor uses a clock output from USB 2.0, which determines the speed of data transferred to USB 2.0 by the output clock coming from USB. However, the clock cycle for register control between the image controller and USB 2.0 does not affect the frame rate even if it is not a fast cycle, but the clock delivered to USB 2.0 has a direct and decisive effect on the frame rate displayed by the host. have. Therefore, as shown in the right side of Figure 7, by using the independent clock of the USB 2.0 and MCU I / F, it is possible to increase the frame rate up to twice or more.

8 is a ping-pong image transfer method using an SDRAM used as a frame buffer according to an embodiment of the present invention. Referring to FIG. 8, first, data output from a sensor is first stored in an up buffer of two SDRAMs (UP_BUFFER on the image controller in FIG. 1 and DN_BUFFER below), and then MUC I / F is stored. When the host knows that one frame buffer is full, the host detects this and reads data from the frame buffer filled via USB 2.0. If the sensor outputs while performing this process, the image controller stores the image data coming into another frame buffer. If all the data in the buffer previously delivered to the host is completed during the data storage process, the host informs that all data has been transferred via USB 2.0. This ping-pong process is performed to deliver the maximum frame buffer.

 As described above, it has been described with reference to the preferred embodiment of the present invention, but those skilled in the art various modifications and changes of the present invention without departing from the spirit and scope of the present invention described in the claims below I can understand that you can.

As described above, according to the present invention, an image of a sensor can be output in real time in a sensor test field used in a camera module, which is one of the key factors driving the market of a mobile phone, which is one of the attractive points of the current market.

And since it uses Global Virtual VSYNC internally, it can support all sensors used in the market, so it can be used to compare and evaluate images of various sensors.

Also, by separating MCU I / F clock and USB 2.0 clock, it brings the effect of maximizing frame rate of image delivered to host by using USB 2.0. Therefore, delay of frame rate is minimized by increasing pixel of image sensor. You can see the effect.

Claims (7)

At least two memories for storing image data output from the sensor; An image controller which determines in which memory the output image data is to be stored and stores the image data in the determined memory; An interface for transmitting the stored image data to a monitor of a computer; And CMOS sensor support image display device including a register for setting the number of HS. delete The image display apparatus of claim 1, wherein the memory uses an SDRAM. The image display apparatus of claim 1, wherein the interface uses a universal serial bus (USB) 2.0. Sequentially storing image data output from the sensor in at least two memories through an image controller; Recognizing the number of HSs of the sensor in advance, counting the number of HSs in advance, and generating and storing internal VS; And And transmitting the image data to the monitor of the computer through a predetermined interface when the image data is stored in the memory and is full. delete 6. The method of claim 5, wherein the interface selects a polarity of the sensor.

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