KR100692848B1 - Driving method of electro-luminescence display panel - Google Patents

Abstract

The present invention relates to an apparatus for driving an electro-luminescence display panel which can reduce the size of a scan driver.

An EL display panel driving apparatus of the present invention comprises: an electro-luminescence display panel including m x n electro-luminescence pixel elements formed at each intersection of m gate lines and n data lines; A data driver for driving data lines; A scan driver for driving the gate lines; And a controller for supplying the data control signals along with the rearranged data signals according to the driving order of the gate lines to the data driver, and for supplying the gate control signals including the start pulse and the clock signal and the select signal to the scan driver. ; The scan driver includes: m / 2 shift registers for shifting and outputting a start pulse in response to a clock signal supplied from a controller; A gate of any one of two gate lines connected between the output terminal of each of the shift registers and the gate lines of two of the m gate lines and connected to the output line of each of the shift registers according to a select signal supplied from the controller. And m / 2 switching elements for connection to the line.

Description

Electro-luminescence display panel drive device {DRIVING METHOD OF ELECTRO-LUMINESCENCE DISPLAY PANEL}             

1 is a cross-sectional view showing the structure of a conventional organic EL element.

Fig. 2 is a block diagram showing the structure of a driving apparatus of a conventional organic EL display panel.

3 is an equivalent circuit diagram of the EL cell shown in FIG.

4 is a diagram illustrating an output waveform of the scan driver shown in FIG. 2;

5 is a block diagram showing the configuration of an organic EL display panel driving apparatus according to an embodiment of the present invention.

FIG. 6 is a diagram showing a detailed configuration of the scan driver shown in FIG. 5; FIG.

FIG. 7 is a view showing output waveforms of the scan driver shown in FIG. 6; FIG.

8 is a view showing another detailed configuration of the scan driver shown in FIG.

FIG. 9 is a view showing output waveforms of the scan driver shown in FIG. 8; FIG.

<Description of Symbols for Main Parts of Drawings>

2 metal electrode 4 electron injection layer

6: electron transport layer 8: light emitting layer

10 hole transport layer 12 hole injection layer

14 transparent electrode 20, 30 EL display panel

22, 32, 40: scan driver 24, 34: data driver

26: PE driving circuit 28, 36: controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electroluminescent display device, and more particularly, to a driving device of an electroluminescent display panel capable of reducing the size of a scan driver.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays, field emission displays, plasma display panels, and electro-luminescence (hereinafter, EL). And display devices.

Among them, the EL display device is a self-luminous device that emits a fluorescent material by recombination of electrons and holes, and is classified into inorganic EL and organic EL according to its material and structure. Such an EL display device has an advantage that the response speed is as fast as that of a cathode ray tube as compared to a passive light emitting device requiring a separate light source like a liquid crystal display device. In addition, since the EL display device has a low DC driving voltage and can be made ultra thin, the EL display device can be applied to a wall-mount type or a portable device.

1 is a cross-sectional view showing a general organic EL structure for explaining the light emission principle of an EL display device. The organic EL has an electron injection layer 4, an electron transport layer 6, a light emitting layer 8, a hole transport layer 10, and a hole injection layer 12 stacked between the metal electrode 2 and the transparent electrode 14. do.

When a voltage is applied between the transparent electrode 14 and the metal electrode 2, electrons generated from the metal electrode 2 move toward the light emitting layer 8 through the electron injection layer 4 and the electron transport layer 6. In addition, holes generated from the transparent electrode 48 move toward the light emitting layer 8 through the hole injection layer 12 and the hole transport layer 10. Accordingly, in the light emitting layer 8, light is generated by collision and recombination of electrons and holes supplied from the electron transport layer 6 and the hole transport layer 10, and the light is emitted to the outside through the transparent electrode 14. To display an image.

2 is a block diagram schematically showing a general EL display panel driver. The EL display panel driver shown in Fig. 2 includes an EL display panel 20 including pixels PE arranged at each of intersections of the gate line GL and the data line DL, and the EL display panel 20. Scan driver 22 for driving the gate lines GL of the plurality of gate lines GL, a data driver 24 for driving the data lines DL of the EL display panel 20, a scan driver 22 and a data driver A controller 28 for controlling 24.

Each of the pixels PE is driven when the gate signals of the gate line GL are enabled to generate light corresponding to the magnitude of the pixel signal on the data line DL.

The controller 28 supplies the gate control signals GCS to the scan driver 22 as well as the control signals along with the data to the data driver 24.

The scan driver 22 sequentially scans the gate lines GL as shown in FIG. 4 in response to the gate control signals GCS from the controller 28, that is, the start pulse and the clock signal. Supply a pulse SP. To this end, the scan driver 22 transmits a plurality of shift registers (not shown) for shifting the start pulse from the controller 28 and scan signals output from the shift registers of the EL display panel 20. A plurality of level shifters are provided for level shifting to a voltage suitable for driving the gate lines GL. The shift registers and the level shifters are connected in a one-to-one correspondence, and an output terminal of each of the level shifters is connected to each of the gate lines GL of the EL display panel 20. The shift registers are supplied to the gate lines GL via the level shifters while sequentially shifting start pulses to the first stage shift register using clock signals commonly input from the controller 28. Accordingly, when m gate lines GL are disposed on the EL display panel 20, the scan driver 22 includes m shift registers to be connected to each of the m gate lines GL, and m number of shift registers. Level shifters are needed.

The data driver 24 supplies the data signal from the controller 28 to the pixels PE through the data lines DL in response to the control signals supplied from the controller 28. In this case, the data driver 24 supplies one horizontal line of data to the data lines DL for each scan period in which each of the gate lines GL is driven by the scan driver 22.

As described above, the pixels PE driven by the scan driver 22 and the data driver 24 include the EL cell EL connected to the supply voltage source VDD and the EL cell ( And a cell driver 26 for driving the EL). The cell driver 26 may include a first thin film transistor Q1 connected between the data line DL, the gate line GL, and the first node N1, and a first thin film transistor Q1. The second TFT Q2 connected between one node N1 and the EL cell EL and the ground voltage source GND, and the capacitor C1 connected between the first node N1 and the ground voltage source GND are connected. Equipped.

The first TFT Q1 is turned on when the enabled gate signal is applied to the gate line GL, and supplies the data signal supplied to the data line DL to the first node N1. The capacitor C1 charges the voltage of the data signal supplied from the data line DL to the first node N1 through the first TFT Q1 and transfers the charged data voltage to the gate electrode of the second TFT Q2. To feed. The second TFT Q2 is connected to the base voltage source GND and the cathode of the EL cell EL by the data voltage charged in the capacitor C1. As a result, the EL cell EL is driven by the voltage difference between the supply voltage VDD and the ground voltage GND to generate light corresponding to the voltage difference.

As described above, in the conventional EL display panel driver, when m gate lines GL are formed on the EL display panel 20, the scan driver 22 drives m shifts to drive each of the m gate lines GL. Must contain registers Accordingly, when the number of gate lines GL in the EL display panel 20 increases in accordance with a trend toward higher resolution, shift registers and level shifters for driving them increase, thereby increasing the volume of the scan driver. .

Accordingly, it is an object of the present invention to provide a driving device of an EL display panel which can reduce the size of a scan driver.

In order to achieve the above object, an EL display panel driving apparatus according to the present invention is an electro-luminescence device having m x n electro-luminescence pixel elements formed at each intersection of m gate lines and n data lines. A necessity display panel; A data driver for driving data lines; A scan driver for driving the gate lines; And a controller for supplying the data control signals along with the rearranged data signals according to the driving order of the gate lines to the data driver, and for supplying the gate control signals including the start pulse and the clock signal and the select signal to the scan driver. ; The scan driver includes: m / 2 shift registers for shifting and outputting a start pulse in response to a clock signal supplied from a controller; A gate of any one of two gate lines connected between the output terminal of each of the shift registers and the gate lines of two of the m gate lines and connected to the output line of each of the shift registers according to a select signal supplied from the controller. And m / 2 switching elements for connection to the line. In addition, there is further provided m / 2 level shifters connected between each of the m / 2 shift registers and the switching elements to level shift the signal output from the shift register to a voltage suitable for driving the gate line.

The switching element is commonly connected to the odd-numbered gate line and the even-numbered gate line to connect one of the odd-numbered and even-numbered gate lines to the output terminal of the shift register according to the select signal.

Alternatively, the switching device is commonly connected to the upper gate line and the lower gate line of the panel to connect one of the gate lines of the upper and lower gate lines to the output terminal of the shift register according to the select signal.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 9.

Fig. 5 is a block diagram schematically showing an EL display panel driver according to the embodiment of the present invention. The EL display panel driver shown in FIG. 5 includes an EL display panel 30 having pixels PE arranged at each of intersections of the gate line GL and the data line DL, and the EL display panel 30. Scan driver 32 for driving the gate lines GL of the plurality of gate lines GL, a data driver 34 for driving the data lines DL of the EL display panel 30, a scan driver 32 and a data driver ( A controller 36 for controlling 34.

Each of the pixels PE is driven when the gate signals of the gate lines GL1 to GLm are enabled to generate light corresponding to the magnitude of the pixel signals on the data lines DL1 to DLn. Here, the pixel elements PE are constituted of an EL cell EL connected to a supply voltage source VDD and a cell driver 26 for driving the EL cell EL, as shown in FIG. The EL display panel 30 is driven in an active manner in which the pixel elements PE are independent. On the other hand, when each of the pixels PE is constituted by an EL cell (not shown) connected between the gate lines GL1 to GLm and the data lines DL1 to DLn, it is driven in a passive manner.

The controller 36 supplies the select signal SEL and the gate control signals GCS to the scan driver 32 as well as the control signals along with the data to the data driver 34. In particular, the controller 36 causes the scan driver 32 to selectively drive the gate lines GL1 to GLm of the EL display panel 30 using the select signal SEL. In addition, the controller 36 rearranges the data corresponding to the gate lines GL1 to GLm selected by the select signal SEL, and supplies the data to the data driver 34.

The data driver 34 supplies the data signal from the controller 36 to the pixels PE through the data lines DL1 to DLn in response to control signals supplied from the controller 36. In this case, the data driver 34 supplies one horizontal line of data to the data lines DL1 to DLn for each scan period of driving the gate lines GL1 to GLm in the scan driver 32.

The scan driver 32 scan pulses for selectively enabling the gate lines GL1 in response to the select signal SEL and the gate control signals GCS from the controller 36, that is, the start pulse and the clock signal. Supply (SP).

In detail, the scan driver 32 includes m / 2 shift registers SR1 to SRm / 2 and shift registers as shown in FIG. 6 to drive m gate lines GL1 to GLm. M / 2 level shifters LS1 to LSm / 2 connected to the output terminals of SR1 to SRm / 2 and output terminals of the level shifters LS1 to LSm / 2 to two gate lines, respectively. M / 2 switching elements SW1 to SWm / 2 for selectively connecting. The shift registers SR1 to SRm / 2 sequentially shift start pulses supplied from the controller 36 to the first shift register SR1 by using the clock signals input from the controller 36. The level shifters LS1 to LSm / 2 level shift the signals output from the shift registers SR1 to SRm to voltages suitable for driving the gate lines GL1 to GLm and output the scan signals. The switching elements SW1 to SWm / 2 select one of the two gate lines connected to their output terminal according to the select signal SEL input from the controller 36 to select the level shifters LS1 to SW1 to SWm / 2. LSm / 2) allows scan signals outputted from each to be supplied.

For example, as shown in FIG. 7, when the select signal SEL is in a low state, the switching elements SW1 to SWm / 2 have the odd-numbered gate line GL1 among the two gate lines connected to the output terminal thereof. , GL3, ..., GLm-1) are selected so that scan signals output from each of the level shifters LS1 to LSm / 2 are supplied. Accordingly, the scan pulse SP is sequentially supplied to the odd-numbered gate lines GL1, GL3, ..., GLm-1 during the period in which the select signal SEL is low.

Subsequently, when the select signal SEL is in a high state, the switching elements SW1 to SWm / 2 have the even-numbered gate lines GL2, GL4,..., GLm among the two gate lines connected to their output terminals. Is selected so that the scan signals output from each of the level shifters LS1 to LSm / 2 are supplied. Accordingly, the scan pulse SP is sequentially supplied to the even-numbered gate lines GL2, GL4, ..., GLm during the period in which the select signal SEL is high.

8, a detailed configuration of a scan driver 40 according to another embodiment of the present invention is shown. The scan driver 40 shown in FIG. 8 includes m / 2 shift registers SR1 to SRm / 2 and m / 2 level shifters connected to output terminals of the shift registers SR1 to SRm / 2, respectively. M / 2 switching elements SW1 to SWm / 2 for selectively connecting each of the LS1 to LSm / 2 and the output terminals of the level shifters LS1 to LSm / 2 to two gate lines. It is provided.

The shift registers SR1 to SRm / 2 sequentially shift start pulses supplied from the controller 36 to the first shift register SR1 by using the clock signals input from the controller 36. The level shifters LS1 to LSm / 2 level shift the signals output from the shift registers SR1 to SRm to voltages suitable for driving the gate lines GL1 to GLm and output the scan signals. The switching elements SW1 to SWm / 2 select one of the two gate lines connected to their output terminal according to the select signal SEL input from the controller 36 to select the level shifters LS1 to SW1 to SWm / 2. LSm / 2) allows scan signals outputted from each to be supplied. In particular, each of the switching elements SW1 to SWm / 2 selects one of a gate line disposed at an upper end of the EL display panel 30 and a gate line disposed at a lower end according to the select signal SEL.

For example, as shown in FIG. 9, when the select signal SEL is in the low state, the switching elements SW1 to SWm / 2 have the upper gate line GL1 to the upper one of the two gate lines connected to their output terminal. GLm / 2) is selected so that the scan signals output from each of the level shifters LS1 to LSm / 2 are supplied. Accordingly, the scan pulse SP is sequentially supplied to the upper gate lines GL1 to GLm / 2 during the period in which the select signal SEL is low.

Subsequently, when the select signal SEL is in a high state, the switching elements SW1 to SWm / 2 select the lower gate line GLm / 2 + 1 to GLm from two gate lines connected to its output terminal. The scan signals output from the level shifters LS1 to LSm / 2 are supplied. Accordingly, the scan pulse SP is sequentially supplied to the lower gate lines GLm / 2 + 1 to GLm during the period in which the select signal SEL is high.

Accordingly, the number of shift registers and level shifters included in the scan drivers 32 and 40 can be reduced by half as compared with the related art.

As described above, in the EL display panel driver according to the present invention, the number of sheet registers and level shifters included in the scan driver can be reduced to m / 2 to drive m gate lines using a select signal. do. As a result, in the EL display panel driving apparatus according to the present invention, the size of the scan driver can be significantly reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

an electro-luminescence display panel having m x n electro-luminescence pixel elements formed at each intersection of m gate lines and n data lines; A data driver for driving the data lines; A scan driver for driving the gate lines; A controller for supplying data control signals along with rearranged data signals in accordance with the driving order of the gate lines to the data driver, and supplying gate control signals including a start pulse and a clock signal and a select signal to the scan driver. With; The scan driver, M / 2 shift registers for shifting and outputting the start pulse in response to a clock signal supplied from the controller; Two gate lines connected between an output terminal of each of the shift registers and two gate lines of the m gate lines, and the output terminal of each of the shift registers according to a select signal supplied from the controller A device for driving an electro-luminescence display panel, comprising: m / 2 switching elements for connecting to any one of the gate lines. The method of claim 1, M / 2 level shifters connected between each of the m / 2 shift registers and the switching elements to level shift a signal output from the shift register to a voltage suitable for driving the gate line. A device for driving an electroluminescent display panel. The method of claim 1, And the switching device is connected in common to the odd-numbered gate line and the even-numbered gate line to connect one of the odd-numbered and even-numbered gate lines to an output terminal of the shift register according to the select signal. Driving device of luminescence display panel. The method of claim 1, The switching element is connected to an upper gate line and a lower gate line of the panel in common and connects one of the gate lines of the upper and lower gate lines to an output terminal of the shift register according to the select signal. Driving device of luminescence display panel.

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