KR100691015B1 - Formative method of flip chip bump - Google Patents

Formative method of flip chip bump Download PDF

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KR100691015B1
KR100691015B1 KR1020050107718A KR20050107718A KR100691015B1 KR 100691015 B1 KR100691015 B1 KR 100691015B1 KR 1020050107718 A KR1020050107718 A KR 1020050107718A KR 20050107718 A KR20050107718 A KR 20050107718A KR 100691015 B1 KR100691015 B1 KR 100691015B1
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metal layer
solder
bump
stacked
flip chip
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KR1020050107718A
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Korean (ko)
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정영희
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A method for forming a flip chip bump is provided to guarantee a maximum height of a solder bump in a limited area by easily adjusting the quantity of solder necessary for forming a bump. A first metal layer(20) is stacked on a core(10) constituting a substrate. Solder resist(30) is stacked on both side ends of the first metal layer. A photomask is stacked on the center of the first metal layer, separated from each solder resist at both the side ends of the first metal layer by the same interval. A second metal layer(50) is stacked on the exposed first metal layer between the solder resist and the photomask. The photomask between the second metal layers is removed. Solder is stacked on the first metal layer exposed by removal of the second metal layer and the photomask. The solder on the second metal layer is transferred to the solder on the first metal layer by a reflow of the stacked solder to form a bump(70). The second metal layer is made of an Al layer, and a non-wetting region is formed on the second metal layer without generating spreading of the solder.

Description

플립 칩 범프 형성 방법{Formative method of flip chip bump}Format method of flip chip bump

도 1a 내지 도 1g는 본 발명의 일 실시예에 따른 플립 칩 범프 형성방법을 순차적으로 나타낸 단면도.1A to 1G are cross-sectional views sequentially illustrating a flip chip bump forming method according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10... 코어 20... 제1메탈층10 ... core 20 ... first metal layer

30... 솔더 레지스트 40... 솔더 마스크30 ... solder resist 40 ... solder mask

50... 제2메탈층 60... 솔더50 ... Second metal layer 60 ... Solder

70... 범프70 ... bump

본 발명은 플립 칩 범프 형성방법에 관한 것으로서, 특히 파인 피치의 솔더 범프 높이를 충분히 확보할 수 있는 플립 칩 범프 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming flip chip bumps, and more particularly, to a method for forming flip chip bumps capable of sufficiently securing the solder bump height of a fine pitch.

최근 전자 기기의 소형화, 박형화 추세에 따라 반도체 소자를 외부 환경으로부터 보호하는 패키지 기술에 있어서 고속, 고동작, 고밀도 실장 등이 요구되고 있다.In recent years, with the trend toward miniaturization and thinning of electronic devices, high speed, high operation, high density mounting, and the like are required in a package technology for protecting a semiconductor device from an external environment.

이러한 요구에 부응하기 위하여 웨이퍼에서 얻어진 베어 칩을 기판에 직접 접착하는 플립 칩 실장 기술이 등장하게 되었다.To meet these demands, flip chip mounting technology has emerged, in which bare chips obtained from wafers are directly bonded to a substrate.

이 플립 칩 실장 기술은 반도체 칩을 패키징하지 않고, 반도체 칩의 상부에 형성되어 있는 패드 위에 범프를 형성하고, 범프와 인쇄회로기판에 인쇄된 접속 패드를 솔더링 방식으로 접속시키는 기술을 말한다.This flip chip mounting technique refers to a technique of forming a bump on a pad formed on an upper portion of the semiconductor chip without packaging the semiconductor chip, and connecting the bump and the connection pad printed on the printed circuit board by soldering.

여기서, 플립 칩에의 범프 형성방법은 일정한 면적에 형성해 놓은 금속의 범프 패드 위에 도금이나 스크린 프린트 방식에 의하여 솔더를 도금하거나 도포한 후, 리플로우에 의하여 솔더 범프를 형성하는 방법을 사용하고 있다.Here, a bump forming method on a flip chip uses a method of forming solder bumps by reflow after plating or applying solder on a metal bump pad formed in a predetermined area by plating or screen printing.

그런데, 이와 같은 플립 칩 범프 형성방법은 제한된 면적과 도금(도포) 두께의 한계로 인하여 범프 형성 시, 범프의 높이가 제한되는 문제점이 있다.However, the flip chip bump formation method as described above has a problem in that the bump height is limited when the bump is formed due to the limited area and the thickness of the plating (coating).

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 제한된 면적에서 솔더 범프의 높이를 최대로 확보할 수 있도록 개선된 플립 칩 범프 형성방법을 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an improved flip chip bump forming method for securing the maximum height of solder bumps in a limited area.

상기의 목적을 달성하기 위한 본 발명의 플립 칩 범프 형성 방법은, 기판을 구성하는 코어 상에 제1메탈층을 적층하는 단계; 상기 제1메탈층의 양측단부에 솔더 레지스트를 적층하는 단계; 상기 양측단부의 솔더 레지스트 각각과 동일한 간격 이격되어 상기 제1메탈층 중심부에 포토 마스크를 적층하는 단계; 상기 솔더 레지스트와 상기 포토 마스크 사이의 노출된 제1메탈층 상에 제2메탈층을 적층하는 단계; 상기 제2메탈층 사이의 포토 마스크를 제거하는 단계; 상기 제2메탈층 및 상기 포토 마스크의 제거에 의하여 노출된 제1메탈층 상에 솔더를 적층하는 단계; 및 상기 적층된 솔더의 리플로우에 의하여 상기 제2메탈층 상의 솔더를 상기 제1메탈층 상의 솔더측으로 이동시켜 범프를 형성하는 단계를 포함한 것이 바람직하다.Flip chip bump forming method of the present invention for achieving the above object comprises the steps of: laminating a first metal layer on a core constituting a substrate; Stacking solder resists on both side ends of the first metal layer; Stacking a photo mask on the center of the first metal layer at equal intervals from each of the solder resists at both ends; Depositing a second metal layer on the exposed first metal layer between the solder resist and the photo mask; Removing the photo mask between the second metal layers; Depositing solder on the first metal layer exposed by removing the second metal layer and the photo mask; And moving the solder on the second metal layer to the solder side on the first metal layer by the reflow of the stacked solder to form bumps.

여기서, 상기 제2메탈층은 Al층으로, 상기 제2메탈층 상에서 상기 솔더의 퍼짐이 없는 논 웨팅(non wetting) 영역을 형성하는 것이 바람직하다.Here, the second metal layer is an Al layer, and preferably forms a non-wetting region without spreading of the solder on the second metal layer.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1g는 본 발명의 일 실시예에 따른 플립 칩 범프 형성방법을 순차적으로 나타낸 단면도이다.1A to 1G are cross-sectional views sequentially illustrating a flip chip bump forming method according to an exemplary embodiment of the present invention.

도면을 참조하면, 플림 칩 범프 형성방법은 먼저 도 1a와 같이 기판을 구성하는 코어(10) 상에 회로 패턴을 형성하기 위하여 Cu 등으로 이루어진 제1메탈층(20)을 적층한 후, 도 1b와 같이 제1메탈층(20)의 양측단부에 솔더 레지스트(30)를 적층한다.Referring to the drawing, in the method of forming a chip chip bump, first, a first metal layer 20 made of Cu or the like is formed on the core 10 constituting the substrate as shown in FIG. 1A, and then FIG. 1B. As described above, the solder resists 30 are laminated at both ends of the first metal layer 20.

다음으로, 도 1c와 같이 제1메탈층(20)의 중심부, 즉 양측단부에 마련된 솔더 레지스트(30) 각각으로부터 동일한 간격 이격된 중심부에 포토 마스크(40)를 적층한다.Next, as illustrated in FIG. 1C, the photomask 40 is stacked in the center of the first metal layer 20, that is, in the center spaced apart from each of the solder resists 30 provided at both ends.

이와 같이 포토 마스크(40)를 적층하게 되면, 포토 마스크(40)와 솔더 레지스트(30) 사이의 제1메탈층(20)은 외부로 노출되게 된다.When the photo mask 40 is stacked in this manner, the first metal layer 20 between the photo mask 40 and the solder resist 30 is exposed to the outside.

다음으로, 도 1d와 같이 포토 마스크(40)와 솔더 레지스트(30) 사이의 노출된 제1메탈층(20) 상에 Al 등으로 이루어진 제2메탈층(50)을 적층한다.Next, as shown in FIG. 1D, a second metal layer 50 made of Al or the like is stacked on the exposed first metal layer 20 between the photomask 40 and the solder resist 30.

이 제2메탈층(50)은 후술할 솔더(60)와 고용체를 형성하지 않는 성분으로, 제2메탈층(50) 상에 솔더(60)를 도포 시, 도포된 솔더(60)가 제2메탈층(50) 상에서 퍼지지 않는 성질을 가진 논 웨팅(non wetting) 영역을 형성한다.The second metal layer 50 is a component that does not form a solder 60 and a solid solution to be described later. When the solder 60 is applied onto the second metal layer 50, the applied solder 60 is formed as a second component. A non-wetting region having a property of not spreading is formed on the metal layer 50.

다음으로, 도 1e와 같이 포토 마스크(40)를 제거한 후, 도 1f와 같이 양측단부에 마련된 솔더 레지스트(30)에 의하여 형성된 공간, 즉 포토 마스크(40)의 제거에 의하여 노출된 제1메탈층(20)과 제2메탈층(50)을 덮도록 솔더(60)를 도포한다.Next, after removing the photo mask 40 as shown in FIG. 1E, the first metal layer exposed by the removal of the photo mask 40, that is, the space formed by the solder resists 30 provided at both ends as shown in FIG. 1F. Solder 60 is applied to cover 20 and the second metal layer 50.

마지막으로, 도 1g와 같이 도포된 솔더(60)를 리플로우하여 제2메탈층(50) 상에 존재하는 솔더(60)를 제1메탈층(20) 상으로 이동시켜 범프(70)를 형성한다.Finally, as shown in FIG. 1G, the coated solder 60 is reflowed to move the solder 60 present on the second metal layer 50 onto the first metal layer 20 to form a bump 70. do.

여기서, 범프 형성 과정에 대하여 좀 더 상세히 설명하면, 리플로우 시, 도포된 솔더는 액상으로 용융되며, 이때 표면장력은 솔더의 응집력과 표면 에너지를 줄이려는 방향으로의 물리 작용에 의해 솔더가 웨팅되지 않는 제2메탈층 상의 솔더는 제1메탈층 상으로 이동하여 범프를 형성하게 된다.Here, the bump formation process will be described in more detail. During reflow, the applied solder is melted in the liquid phase, and the surface tension does not wet the solder due to physical action in the direction of reducing the cohesion and surface energy of the solder. Solder on the non-second metal layer is moved onto the first metal layer to form bumps.

이와 같은 플립 칩 범프 형성방법에 의하면, 파인 피치의 솔더 범프 형성 시, 충분한 양의 솔더에 의하여 원하는 높이 및 원하는 피치의 범프를 적절하게 형성할 수 있게 되고, 범프 형성에 필요한 솔더량의 제어가 용이한 장점이 있다.According to this flip chip bump forming method, when forming a fine pitch solder bump, it is possible to form a bump of a desired height and a desired pitch properly by a sufficient amount of solder, and it is easy to control the amount of solder required for bump formation. There is one advantage.

상술한 바와 같이 본 발명의 플립 칩 범프 형성방법에 의하면, 파인 피치의 솔더 범프 형성 시, 충분한 양의 솔더에 의하여 원하는 높이로 원하는 피치의 범프를 적절하게 형성할 수 있게 되고, 범프 형성에 필요한 솔더량의 제어를 용이하게 조절할 수 있는 효과를 제공한다.As described above, according to the flip chip bump forming method of the present invention, when forming a fine pitch solder bump, a bump of a desired pitch can be appropriately formed at a desired height by a sufficient amount of solder, and the solder required for bump formation Provides an effect that can easily control the amount of control.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (2)

기판을 구성하는 코어 상에 제1메탈층을 적층하는 단계; Stacking a first metal layer on a core constituting the substrate; 상기 제1메탈층의 양측단부에 솔더 레지스트를 적층하는 단계; Stacking solder resists on both side ends of the first metal layer; 상기 양측단부의 솔더 레지스트 각각과 동일한 간격 이격되어 상기 제1메탈층 중심부에 포토 마스크를 적층하는 단계; Stacking a photo mask on the center of the first metal layer at equal intervals from each of the solder resists at both ends; 상기 솔더 레지스트와 상기 포토 마스크 사이의 노출된 제1메탈층 상에 제2메탈층을 적층하는 단계; Depositing a second metal layer on the exposed first metal layer between the solder resist and the photo mask; 상기 제2메탈층 사이의 포토 마스크를 제거하는 단계; Removing the photo mask between the second metal layers; 상기 제2메탈층 및 상기 포토 마스크의 제거에 의하여 노출된 제1메탈층 상에 솔더를 적층하는 단계; 및Depositing solder on the first metal layer exposed by removing the second metal layer and the photo mask; And 상기 적층된 솔더의 리플로우에 의하여 상기 제2메탈층 상의 솔더를 상기 제1메탈층 상의 솔더측으로 이동시켜 범프를 형성하는 단계를 포함한 것을 특징으로 하는 플립 칩 범프 형성방법.And forming bumps by moving the solder on the second metal layer to the solder side on the first metal layer by reflow of the stacked solder. 제1항에 있어서,The method of claim 1, 상기 제2메탈층은 Al층으로, 상기 제2메탈층 상에서 상기 솔더의 퍼짐이 없는 논 웨팅(non wetting) 영역을 형성하는 것을 특징으로 하는 플립 칩 범프 형성방법.And the second metal layer is an Al layer, and forms a non-wetting region without spreading of the solder on the second metal layer.
KR1020050107718A 2005-11-10 2005-11-10 Formative method of flip chip bump KR100691015B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020019782A (en) * 2000-09-07 2002-03-13 이진구 manufacturing method of bump for flip chip
KR20020092041A (en) * 2001-06-01 2002-12-11 한국전자통신연구원 Fabrication method of interconnection bump with high density and high aspect ratio

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020019782A (en) * 2000-09-07 2002-03-13 이진구 manufacturing method of bump for flip chip
KR20020092041A (en) * 2001-06-01 2002-12-11 한국전자통신연구원 Fabrication method of interconnection bump with high density and high aspect ratio

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