KR100685623B1 - A flash memory device - Google Patents

Abstract

A flash memory device is provided to reduce the difference of program speed between word lines by using memory cells having gate electrodes, each of which has a different width. A drain select transistor(DST) is connected to a bit line. A source select transistor(SST) is connected to a source line. A plurality of memory cells(MC0,...,MC31) are connected in serial between the drain select transistor and the source select transistor. Gate electrodes of the memory cells have widths that are increased as they approach to the source select transistor or the drain select transistor. Therefore, the difference of program speed between word lines is reduced.

Description

Flash memory device

1 is a cross-sectional view showing a string structure of a flash memory device according to the present invention.

* Explanation of symbols for main parts of drawings *

MC: memory cell SST: source select transistor

DST: Drain Select Transistor

The present invention relates to a semiconductor device, and more particularly to a flash memory device.

In a NAND flash memory device, a program disturb phenomenon occurs in which a cell which is not programmed is programmed at a predetermined time during a program operation of the NAND flash memory device.

The program disturb phenomenon that occurs during the program operation of the NAND flash memory device is caused by a lowering of the boosting level (hereinafter referred to as 'normal program disturb') or a high boosting level of the memory cell. Hot carriers are generated at the edges of the source select transistors of the memory cells adjacent to the source select transistors to occur in the memory cells (memory cells adjacent to the source select transistors). program disturb), which reduces the speed of the NAND flash memory device.

In addition, due to the interference effect between adjacent word lines during the operation of the device, the distribution of the program is affected and the distribution becomes wider, thereby increasing the speed in a program using an incremental step pulse program (ISPP). Will be affected.

Therefore, there is a demand for a technique capable of preventing a decrease in program speed during a program operation of a NAND flash memory device.

An object of the present invention for solving the above problems is to provide a flash memory device that can prevent the program speed degradation during the program operation of the NAND flash memory device.

The idea of the present invention for achieving the above object is a plurality of drain select transistor connected to a bit line, a source select transistor connected to a source line and a plurality of series connected between the drain select transistor and the drain select transistor and the source select transistor in series. And a plurality of memory cells, wherein the plurality of memory cells gradually decrease in width away from the source select transistor and the drain select transistor. The plurality of memory cells are 32, and the thirty-second memory cells having different widths are memory cells adjacent to the drain select transistor and a first memory cell which is a memory cell adjacent to the source select transistor having a gate electrode width of 1; The gate electrode width of the thirteenth memory cell, which is a cell, and the gate electrode width of the first and thirty-second memory cells, The tenth to twelve memories having a ratio of the gate electrode width to the gate electrode width of the thirteenth memory cell, the fourteenth memory cell, the sixteenth to eighteenth memory cells, and the first and the thirtieth memory cells having a ratio of 0.92 to the ratio of 0.94. Cells, 19-21 memory cells, 7--9 memory cells having a gate electrode width ratio of 0.96 to gate electrode widths of the first and 32nd memory cells, 22- 24th memory cells, the fourth to sixth memory cells, the 25th to 27th memory cells and the first and the 32nd memory cells having a ratio of the gate electrode width to the gate electrode width of the first and 32nd memory cells of 0.98 The second to third memory cells have a ratio of the gate electrode width to the gate electrode width of 1, inclusive.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.

1 is a cross-sectional view showing a string structure of a flash memory device according to the present invention.

Referring to FIG. 1, a string of a NAND flash memory according to the present invention includes a source select transistor SST having a common source S, a drain select transistor DST having a drain D connected to a bit line, Flash memory cells MC1 to MCn are formed in series between the source select transistor SST and the drain select transistor DST. Here, 16 or 32 flash memory cells MC0 to MC31 are formed in series between the source select transistor SST and the drain select transistor DST, and each of the flash memory cells MC0 to MC31 is connected to the junction S. , D) share.

Here, the gate line of the drain select transistor DST is a drain select line, the gate line of the source select transistor SST is a source select line, and the gate lines of the memory cells MC0 to MC31 are first to first, respectively. n becomes a word line.

The gate electrode width of the first memory cell MC0, which is a memory cell adjacent to the source select transistor SST, and the gate electrode width of the thirty-second memory cell MC31, which is a memory cell adjacent to the drain select transistor DST have a width of 1. Has a ratio (A).

Further, the gate electrode width of the fifteenth memory cell MC14 has a ratio of 0.9 (0.9 = B of A) to the gate electrode widths of the first and thirty-second memory cells MC0 and MC31 having a ratio of one.

In addition, the gate electrode widths of the thirteenth memory cell MC12, the fourteenth memory cell MC13, and the sixteenth to eighteenth memory cells MC15 ˜ 17 have a ratio of 1 to the first and thirteenth memory cells MC0. , MC31 has a ratio of 0.92 (A of 0.92 = C) to the gate electrode width.

In addition, the gate electrode widths of the 10th through 12th memory cells MC9 ˜ MC11 and the 19th through 21th memory cells MC18 ˜ MC20 have a ratio of 1 to that of the first and 32nd memory cells MC0 and MC31. It has a ratio of 0.94 (not shown) with respect to the gate electrode width.

In addition, the gate electrode widths of the seventh to ninth memory cells MC6 to MC8 and the twenty-second to twenty-fourth memory cells MC21 to MC23 have a ratio of 1 to that of the first and thirty-second memory cells MC0 and MC31. It has a ratio of 0.96 (not shown) with respect to the gate electrode width.

In addition, the gate electrodes of the fourth to sixth memory cells MC3 to MC5 and the twenty-fifth to twenty-seventh memory cells MC24 to MC26 have gate widths of the first and thirty-second memory cells MC0 and MC31 having a ratio of one. It has a ratio of 0.98 (not shown) to the width.

In addition, the gate electrode widths of the second to third memory cells MC1 to MC2 have a ratio of 1 (not shown) to the gate electrode widths of the first and 32nd memory cells MC0 and MC31 having a ratio of 1.

In the prior art, the gate electrode widths of the first to thirty-second memory cells have the same width, thereby showing a difference in program speed of each of the memory cells, that is, word lines. Each having a different width, that is, 1, 0.9, 0.92, 0.94, 0.96, 0.98, can reduce the program speed difference of each word line.

On the other hand, by forming the gate electrode widths of the first to 32nd memory cells differently as described above, it can be seen that the existing first to 32nd memory cells are reduced by about 22% compared to the distributed chip size.

According to the present invention, the gate electrode widths of the first to thirty-second memory cells have different widths, so that the program speed difference of each word line can be reduced, thereby preventing a program speed decrease during the program operation of the NAND flash memory device. can do.

As described above, according to the present invention, the gate electrode widths of the first to thirty-second memory cells have different widths, so that the program speed difference of each word line can be reduced, so that the program operation of the NAND flash memory device can be performed. There is an effect that can prevent the slow down of the program.

Although the present invention has been described in detail only with respect to specific embodiments, it will be apparent to those skilled in the art that modifications and variations can be made within the scope of the technical idea of the present invention, and such modifications or changes are defined in the claims of the present invention. Will belong.

Claims (3)

A drain select transistor connected to the bit line; A source select transistor connected to the source line; And And a plurality of memory cells connected in series between the drain select transistor and the source select transistor, wherein the plurality of memory cells increase in width as they become closer to the source select transistor or the drain select transistor. The method of claim 1, wherein the plurality of memory cells 32 flash memory elements. 3. The memory device of claim 2, wherein the thirty-two memory cells having different widths from each other A first memory cell that is a memory cell adjacent to the source select transistor having a gate electrode width of 1 and a 32nd memory cell that is a memory cell adjacent to the drain select transistor; A fifteenth memory cell having a ratio of a gate electrode width to a width of a gate electrode of the first and thirty-second memory cells in a ratio of 0.9; A thirteenth memory cell, a fourteenth memory cell, and a sixteenth through eighteenth memory cell, each having a ratio of a gate electrode width to a gate electrode width of 0.92 in the first and thirty-second memory cells; A tenth to twelfth memory cell and a nineteenth to twenty-first memory cell having a ratio of a gate electrode width to a width of a gate electrode of 0.94 in the first and thirty-second memory cells; A seventh to ninth memory cell and a twenty-second to twenty-fourth memory cell having a ratio of the gate electrode width to the width of the gate electrode of the first and thirty-second memory cells of 0.96; A fourth to sixth memory cell and a twenty-fifth to twenty fifth memory cell having a ratio of a gate electrode width to a gate electrode width of the first and thirty-second memory cells in a ratio of 0.98; And And a second to third memory cells having a ratio of a gate electrode width to a gate electrode width of each of the first and thirty-second memory cells.

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