KR100681205B1 - Semiconductor device for esd circuit - Google Patents

Abstract

The present invention is to provide a semiconductor device for an electrostatic discharge protection circuit that can increase the highest current value that the electrostatic discharge protection circuit can withstand while reducing the area of the electrostatic discharge protection circuit. The semiconductor device may include a semiconductor substrate, a gate oxide film and a gate electrode stacked on a selected surface on the semiconductor substrate, a gate spacer formed on both sidewalls of the stacked structure of the gate oxide film and the gate electrode, and formed in the semiconductor substrate on one side of the gate electrode. A source region connected to a ground, and a drain region formed in the semiconductor substrate on the other side of the gate electrode and having a first region and a second region isolated from the first region, and connected to a pad. You can use GGNMOS or PMOS as a protection circuit Separating and drain regions coupled to the pad in two By forming a path for the ESD current one it is capable of preventing the effect that given further made that the current concentration at the edge of the drain region.

Electrostatic Discharge Protection, ESD, GGNMOS, Ground, BJT

Description

Semiconductor device for electrostatic discharge protection circuit {SEMICONDUCTOR DEVICE FOR ESD CIRCUIT}             

1 is a circuit diagram showing the structure of the electrostatic discharge protection circuit according to the prior art,

Figure 2 is a cross-sectional view showing the structure of a GGNMOS used as a static discharge protection circuit according to the prior art,

3 is a cross-sectional view showing the structure of a GGNMOS for an electrostatic discharge protection circuit according to a first embodiment of the present invention;

4 is a cross-sectional view showing the structure of a GGNMOS for an electrostatic discharge protection circuit according to a second embodiment of the present invention;

5 is a cross-sectional view showing the structure of a PMOS for an electrostatic discharge protection circuit according to a third embodiment of the present invention;

6 is a cross-sectional view showing the structure of a PMOS for an electrostatic discharge protection circuit according to a fourth embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 p-type semiconductor substrate 32 gate oxide film

33: gate electrode 34: gate spacer

35: n ⁺ source region 36: n ⁺ drain region

36a: first drain region 36b: second drain region

37: p ⁺ ground voltage pick-up area 38: pad

39: device isolation layer 40: resistance

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to an electrostatic discharge protection circuit that protects a semiconductor integrated circuit from damage caused by electrostatic discharge (ESD).

Semiconductor integrated circuits are very sensitive to electrostatic discharge (ESD) pulses, and are particularly susceptible to physical damage by the high voltages and currents produced by electrostatic discharge (ESD) pulses. In particular, since the size of a semiconductor device has recently been reduced, the size of an electrostatic discharge (ESD) protection circuit is also reduced, and the size of a voltage that can withstand without damage is also reduced. In addition, since the speed of the device is increasing, the ESD protection circuit should be designed within a range that does not affect the operation speed of the device.

As described above, the ESD protection circuit removes the applied ESD discharge pulses quickly when an ESD discharge pulse having high voltage and high current is applied to the semiconductor device.

In general, an ESD protection circuit is composed of a bipolar junction transistor (BJT) or a diode, but recently, a grounded gate NMOS transistor (GGNMOS) is used.

The GGNMOS is a gate-grounded transistor. Instead of turning on and operating by channel formation like a conventional MOS transistor, the internal NPN structure operates like a BJT by a breakdown phenomenon so that a large amount of current flows.

1 is a circuit diagram showing the structure of the electrostatic discharge protection circuit according to the prior art.

Referring to FIG. 1, a drain is connected to the pad 11 between an internal integrated circuit 12 and a pad 11 connected to the internal integrated circuit 12, and a GGNMOS 13 is connected to a gate and a source connected to the ground Vss.

Figure 2 is a cross-sectional view showing the structure of the GGNMOS used as the electrostatic discharge protection circuit according to the prior art.

As shown in FIG. 2, the GGNMOS includes a p-type semiconductor substrate 21, a gate oxide film 22, a gate electrode 23, and a gate oxide film 22 stacked on a selected surface on the p-type semiconductor substrate 21. A gate spacer 24 formed on both sidewalls of the stacked structure of the gate electrode 23, n ⁺ source region 25 and n ⁺ drain region 26 formed in the p-type semiconductor substrate 21 on both sides of the gate electrode 23, The p ⁺ ground voltage pick-up region 27 is separated through the n ⁺ source region 25 and the device isolation layer 28 and formed on the p-type semiconductor substrate 21 for picking up the ground voltage.

In FIG. 2, the n + drain region 26 is connected to the pad 11, and the gate electrode 23, the n + source region 25, and the p + ground voltage pick-up region 27 are connected to the ground GND.

In the GGNMOS having the configuration as shown in FIGS. 1 and 2, when an ESD pulse occurs in the pad 11, the charges are collected in the n + drain region 26 until turned on until the ESD pulse is turned on. As avalanche breakdown occurs between the type semiconductor substrates 21, the parasitic NPN BJT operation causes the ESD current I to go to ground, thus protecting the internal circuits from the electrostatic discharge ESD.

However, in the prior art, when the current exceeding the highest current It2 that the ESD protection circuit can withstand, n ⁺ drain region 26 suffers thermal damage, thereby destroying the ESD protection circuit.

As shown in FIG. 2, since the ESD current 'I' uses the path having the lowest impedance to escape from the n ⁺ drain region 26 to the ground VSS, the n ⁺ drain region (close to the gate electrode 23) is eventually used. Current is concentrated at the edge of 26), which causes the temperature of this part to rise.

This heat causes a failure, such as contact spiking or melting by current filamentation, to destroy the electrostatic discharge protection circuit.

Therefore, to make a strong ESD protection circuit, it is necessary to increase the DCGS (Drain Contact to Gate Space) to increase the ballast resistance. In this case, the area of the ESD protection circuit is significantly increased, so that it is difficult to satisfy the pin capacitance specification or the area ratio of the ESD protection circuit in the high density circuit increases. .

The present invention has been proposed to solve the problems of the prior art, a semiconductor device for an electrostatic discharge protection circuit that can increase the highest current value that the electrostatic discharge protection circuit can withstand while reducing the area of the electrostatic discharge protection circuit The purpose is to provide.

A semiconductor device for an electrostatic discharge protection circuit of the present invention for achieving the above object is formed on both sides of a semiconductor substrate, a gate oxide film and a gate electrode stacked on a selected surface on the semiconductor substrate, the sidewalls of the stacked structure of the gate oxide film and the gate electrode A pad comprising a gate spacer, a source region formed in the semiconductor substrate on one side of the gate electrode and connected to ground, and a second region formed in the semiconductor substrate on the other side of the gate electrode and isolated from the first region And a drain region connected to the drain region, wherein the first region and the second region are separated by an isolation layer, wherein the first region and the second region are separated from each other in the drain region. Is a dummy formed on the semiconductor substrate between the first region and the second region. Characterized in that the turn-by isolation.

In addition, a semiconductor device for an electrostatic discharge protection circuit of the present invention includes a semiconductor substrate, a well region formed in the semiconductor substrate, a gate oxide film and a gate electrode stacked on a selected surface of the well region, and a stacked structure of the gate oxide film and the gate electrode. A gate spacer formed on both side walls, a source region formed in the well region of one side of the gate electrode and connected to a power voltage terminal, and formed in the well region of the other side of the gate electrode and isolated from the first region and the first region; And a drain region formed in two regions and connected to a pad, wherein the first region and the second region are separated by an isolation layer in the drain region, and the first region in the drain region. And the second region are further formed on the well region between the first region and the second region. Characterized in that the isolated by the pattern.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a cross-sectional view showing the structure of a GGNMOS for an electrostatic discharge protection circuit according to a first embodiment of the present invention.

As shown in FIG. 3, the gate oxide film 32, the gate electrode 33, the gate oxide film 32, and the gate electrode are stacked on a selected surface on the p-type semiconductor substrate 31 and the p-type semiconductor substrate 31. A gate spacer 34 formed on both sidewalls of the stacked structure (33), n ⁺ source region 35 and n ⁺ drain region 36 formed in the p-type semiconductor substrate 31 on both sides of the gate electrode 33, and the ground; It is composed of a p ⁺ ground voltage pick-up region 37 formed in the p-type semiconductor substrate 31 at a predetermined distance from the n + source region 35 for voltage pickup. Here, the gate electrode 33, the n + source region 35 and the ground voltage pick-up region 37 are grounded (Vss), and the n + drain region 36 is connected to the pad 38.

In the GGNMOS having the above configuration, the n + drain region 36 is divided into two differently from the n + source region 35 to make the n + drain region 36 and the n + source region 35 asymmetric. That is, the n + drain region 36 is separated into a first drain region 36a near the gate electrode 33 and a second drain region 36b far from the gate electrode 33, and the first drain region ( The pad 38 is connected to 36a).

In addition, an isolation layer 39 having an STI structure is formed between the first drain region 36a and the second drain region 36b for electrical separation between the two drain regions. The device isolation layer 39 prevents diffusion between the first drain region 36a and the second drain region 36b.

In addition, a resistor 40 is connected between the first drain region 36a near the gate electrode 33 and the pad 38 among the two drain regions, and the resistor 40 is gated after a predetermined time. The second drain region 36b far from the electrode 33 also serves to induce the electrostatic discharge current path to occur. The resistor 40 inserts at least 1 Ω or more.

In the GGNMOS as shown in FIG. 2, since the ESD current is concentrated at the edge of the drain region under the gate oxide layer 32 after the turn-on, the drain region is thermal when the ESD current exceeds the highest current It2 that the ESD protection circuit can withstand. There was a problem of damage (thermal damage).

In order to prevent the current from being concentrated at the edge of the drain region, in the first embodiment as shown in FIG. 3, the n + drain region 36 is divided into two, the first drain region 36a and the second drain region 36b. 2, a resistor 40 is inserted between the first drain region 36a serving as the drain region of FIG. 2 and the pad 38 to induce a current to flow through the second drain region 36b.

As described above, in the GGNMOS according to the first embodiment of the present invention, the drain region has a double drain region.

Since the two drain regions divide the drain region of FIG. 2 into two, each drain region is about half the area of the drain region of FIG. 2 to prevent the increase of the pin capacitance.

An operation of the GGNMOS as shown in FIG. 3 will be described.

First, when an electrostatic discharge occurs, the same voltage is applied to both the first drain region 36a and the second drain region 36b before the GGNMOS is turned on. In this case, the ESD current I flows first by turning on the first drain region 36a further affected by the gate electrode 33. However, since the resistor 40 exists between the first drain region 36a and the pad 38, an I-R drop occurs as the current flows, and the amount of current decreases to flow by the current 'I1'. Then, the reduced current flows toward the second drain region 36b which is relatively non-resistive, thereby forming a current path 'I2'. Thus, the total ESD current I is the sum of I1 and I2.

As a result, unlike the general GGNMOS, the drain region is divided into two to form the first drain region 36a close to the gate electrode 33 and the second drain region 36b far from the gate electrode 33, thereby forming a current path. Making one more will reduce the concentration of current in the existing drain region. This prevents the temperature of the edge of the first drain region 36a from increasing significantly.

Therefore, the highest current It2 that an electrostatic discharge (ESD) protection circuit can withstand is higher than a typical GGNMOS structure. In fact, simulation results using MEDICI not only increased It2, but also found that the threshold voltage (VT1) was lower than that of the general GGNMOS.

According to the first embodiment described above, it is possible to expect the effect of improving the ESD Robustness to the electrostatic discharge (ESD) without further processing.

In addition, since the area of the double drain region is only half of that of the existing GGNMOS, the electrostatic discharge (ESD) protection characteristics can be improved without a large increase in the pin capacitance. Therefore, it is possible to cope with the increasingly integrated semiconductor circuit without much increase in the area of the electrostatic discharge protection circuit.

4 is a cross-sectional view showing the structure of a GGNMOS for an electrostatic discharge protection circuit according to a second embodiment of the present invention.

As shown in FIG. 4, the gate oxide film 42, the gate electrode 43, the gate oxide film 42, and the gate electrode are stacked on a selected surface on the p-type semiconductor substrate 41 and the p-type semiconductor substrate 41. A gate spacer 44 formed on both sidewalls of the stacked structure of (43), n ⁺ source region 45 and n ⁺ drain region 46 formed in the p-type semiconductor substrate 41 on both sides of the gate electrode 43, and the ground; It is composed of a p ⁺ ground voltage pick-up region 47 formed in the p-type semiconductor substrate 41 at a predetermined distance from the n + source region 45 for voltage pickup. Here, the gate electrode 43, the n + source region 45 and the ground voltage pick-up region 47 are grounded, and the n + drain region 46 is connected to the pad 48.

In the GGNMOS having the above configuration, the n + drain region 46 is divided into two differently from the n + source region 45 to make the n + drain region 46 and the n + source region 45 asymmetric. That is, the n + drain region 46 is separated into a first drain region 46a near the gate electrode 43 and a second drain region 46b far from the gate electrode 43, and the first drain region ( The pad 48 is connected to 46a).

The dummy gate oxide film 42a and the dummy gate electrode 43a are disposed on the p-type semiconductor substrate 41 between the first drain region 46a and the second drain region 46b for electrical separation between the two drain regions. Dummy patterns stacked in the order of are formed. In this dummy pattern, the dummy gate electrode 43a is grounded.

In addition, a resistor 49 is connected between the first drain region 46a near the gate electrode 43 and the pad 48 among the two drain regions, and the resistor 49 is gated after a predetermined time. The second drain region 46b far from the electrode 43 also serves to induce the electrostatic discharge current path to occur. The resistor 49 inserts at least 1 Ω or more.

In the above-described second embodiment, the dummy gate oxide film 42a and the dummy gate electrode 43a are stacked in a structure for separating the drain region into two and separating the first drain region 46a and the second drain region 46b. Use a dummy pattern consisting of.

5 is a cross-sectional view showing the structure of a PMOS for an electrostatic discharge protection circuit according to a third embodiment of the present invention.

As shown in FIG. 5, the gate oxide film 52 stacked on the selected surfaces of the p-type semiconductor substrate 51, the n-type well 51a formed in the p-type semiconductor substrate 51, and the n-type well 51a. And p ⁺ source regions formed in the gate spacers 54 formed on both sidewalls of the stacked structure of the gate electrode 53, the gate oxide film 52, and the gate electrode 53, and the n-type wells 51a on both sides of the gate electrode 53. And a p ⁺ drain region 56 and an n ⁺ ground voltage pick-up region 57 formed in the n-type well 51a at a predetermined distance from the p + source region 55 for the ground voltage pickup. . Here, the gate electrode 53, the p + source region 55 and the ground voltage pick-up region 57 are connected to the power supply voltage terminal VDD, and the p + drain region 56 is connected to the pad 58.

In the PMOS having the above configuration, the p + drain region 56 is separated into two differently from the p + source region 55 to make the p + drain region 56 and the p + source region 55 asymmetric. That is, the p + drain region 56 is separated into a first drain region 56a near the gate electrode 53 and a second drain region 56b far from the gate electrode 53, and the first drain region ( The pad 58 is connected to 56a).

A device isolation film 59 having an STI structure is formed between the first drain region 56a and the second drain region 56b to electrically separate the two drain regions. The device isolation layer 59 prevents diffusion between the first drain region 56a and the second drain region 56b.

A resistor 60 is connected between the first drain region 56a near the gate electrode 53 and the pad 58 among the two drain regions, and the resistor 60 is gated after a predetermined time. The second drain region 56b far from the electrode 53 also serves to induce the electrostatic discharge current path to occur. The resistor 60 inserts at least 1 Ω or more.

6 is a cross-sectional view showing the structure of a PMOS for an electrostatic discharge protection circuit according to a fourth embodiment of the present invention.

As shown in FIG. 6, the gate oxide film 62 stacked on the selected surfaces of the p-type semiconductor substrate 61, the n-type well 61a formed in the p-type semiconductor substrate 61, and the n-type well 61a. And p ⁺ source regions formed in the gate spacer 64 formed on both sidewalls of the stacked structure of the gate electrode 63, the gate oxide film 62, and the gate electrode 63, and in the n-type well 61a on both sides of the gate electrode 63. And a p ⁺ drain region 66 and an n ⁺ ground voltage pick-up region 67 formed in the n-type well 61a at a predetermined distance from the p + source region 65 for pickup of the ground voltage. . Here, the gate electrode 63, the p + source region 65 and the ground voltage pick-up region 77 are connected to a power supply voltage terminal, and the p + drain region 66 is connected to the pad 68.

In the PMOS having the above configuration, the p + drain region 66 is divided into two differently from the p + source region 65 to make the p + drain region 66 and the p + source region 65 asymmetric. That is, the p + drain region 66 is separated into a first drain region 66a near the gate electrode 63 and a second drain region 66b far from the gate electrode 63, and the first drain region ( Connect the pad 68 to 66a).

The dummy gate oxide layer 62a and the dummy gate electrode 63a may be formed on the n-type well 61a between the first drain region 66a and the second drain region 66b for electrical separation between the two drain regions. Dummy patterns stacked in sequence are formed. In this dummy pattern, the dummy gate electrode 63a is grounded.

A resistor 69 is connected between the first drain region 66a near the gate electrode 63 and the pad 68 among the two drain regions, and the resistor 69 is gated after a predetermined time. The second drain region 66b far from the electrode 63 also serves to induce the electrostatic discharge current path to occur. The resistor 69 inserts at least 1 Ω or more.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, when the GGNMOS or the PMOS is used as an element for the electrostatic discharge protection circuit, the drain region connected to the pad is formed in two to make an additional pass of the ESD current so that the current is concentrated at the edge of the drain region. There is an effect that can be prevented.

In addition, the present invention increases the maximum current value that the electrostatic discharge protection circuit can withstand, making the area of the electrostatic discharge protection circuit smaller, and reducing the capacitance, thereby being applicable to the electrostatic discharge protection circuit of a high-density, high-speed semiconductor integrated circuit. There is.

Claims (10)

Semiconductor substrates; A gate oxide film and a gate electrode stacked on a selected surface on the semiconductor substrate; A gate spacer formed on opposite sidewalls of the stacked structure of the gate oxide film and the gate electrode; A source region formed in the semiconductor substrate on one side of the gate electrode and connected to a ground; And A drain region formed in the semiconductor substrate on the other side of the gate electrode and having a first region and a second region separated from the first region, and connected to a pad; Semiconductor device for electrostatic discharge protection circuit comprising a. The method of claim 1, In the drain region, And the first region and the second region are separated by an isolation layer. The method of claim 1, In the drain region, And the first region and the second region are separated by a dummy pattern formed on the semiconductor substrate between the first region and the second region. The method of claim 3, wherein The dummy pattern is, And a dummy gate electrode formed on the semiconductor substrate and a dummy gate electrode formed on the dummy gate oxide film, wherein the dummy gate electrode is grounded. The method of claim 1, And the source region and the drain region are n-type conductivity, and the semiconductor substrate is a p-type conductivity type. Semiconductor substrates; A well region formed in the semiconductor substrate; A gate oxide film and a gate electrode stacked on a selected surface of the well region; A gate spacer formed on opposite sidewalls of the stacked structure of the gate oxide film and the gate electrode; A source region formed in the well region of one side of the gate electrode and connected to a power supply voltage terminal; And A drain region formed in the well region of the other side of the gate electrode and having a first region and a second region separated from the first region, and connected to a pad; Semiconductor device for electrostatic discharge protection circuit comprising a. The method of claim 6, In the drain region, And the first region and the second region are separated by an isolation layer. The method of claim 6, In the drain region, And the first region and the second region are separated by a dummy pattern formed on a well region between the first region and the second region. The method of claim 8, The dummy pattern is, And a dummy gate electrode formed on the well region and a dummy gate electrode formed on the dummy gate oxide film, wherein the dummy gate electrode is grounded. The method of claim 1, And the well region is of an n-type conductivity type.

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