KR100678015B1 - Method for manufacturing in semiconductor device - Google Patents

Method for manufacturing in semiconductor device Download PDF

Info

Publication number
KR100678015B1
KR100678015B1 KR1020050070548A KR20050070548A KR100678015B1 KR 100678015 B1 KR100678015 B1 KR 100678015B1 KR 1020050070548 A KR1020050070548 A KR 1020050070548A KR 20050070548 A KR20050070548 A KR 20050070548A KR 100678015 B1 KR100678015 B1 KR 100678015B1
Authority
KR
South Korea
Prior art keywords
pattern
copper
generated
particles
semiconductor device
Prior art date
Application number
KR1020050070548A
Other languages
Korean (ko)
Inventor
조보연
Original Assignee
동부일렉트로닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부일렉트로닉스 주식회사 filed Critical 동부일렉트로닉스 주식회사
Priority to KR1020050070548A priority Critical patent/KR100678015B1/en
Application granted granted Critical
Publication of KR100678015B1 publication Critical patent/KR100678015B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a semiconductor device is provided to eliminate protrusions generated by large particles on a copper pattern by selectively eliminating an intermetallic oxide film. After a contact hole is formed on a substrate, the contact hole is buried with copper(103), and the buried copper is planarized to form a copper pattern. An intermetallic dielectric is deposited on particles generated on the substrate and the copper pattern to form protrusions. A photoresist film is applied on the intermetallic dielectric to eliminate the protrusions generated by the particles and thus form a photoresist film. The intermetallic dielectric is selectively eliminated by using the photoresist pattern as a mask to eliminate the protrusions. The photoresist pattern is eliminated, and a photoresist masking(111) is formed.

Description

반도체 소자의 제조방법{METHOD FOR MANUFACTURING IN SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING IN SEMICONDUCTOR DEVICE}

도 1a 내지 도 1i는 본 발명에 따른 반도체 소자의 제조방법에서 구리 패턴 상에 발생되는 큰 파티클(Large PT)에 의해 생성된 돌출부를 제거하기 위한 과정을 나타내는 공정 순서도.1A to 1I are process flowcharts illustrating a process for removing protrusions generated by large particles (Large PT) generated on a copper pattern in a method of manufacturing a semiconductor device according to the present invention.

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게 이중 다마신(Dual Damascene) 공정에 있어서, 구리(Cu) 화학적 기계적 연마(Chemical Mechanical Polishing, CMP) 공정을 수행한 후 구리 패턴 상에 발생되는 큰 파티클(Large PT)에 의해 생성된 돌출부를 제거할 수 있는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, in a dual damascene process, the copper pattern is formed on a copper pattern after performing a copper (Cu) chemical mechanical polishing (CMP) process. A method can be used to remove protrusions generated by large particles.

주지된 바와 같이, 반도체 소자의 집적도가 증대함으로 기판 상에 도전층을 다층으로 제작하여 형성한다. 이러한 다층 배선은 반도체 소자의 면적 축소 및 디자인 룰이 감소함으로 인하여 더 높은 집적도를 달성할 수 있다. 다층 배선을 수행하기 위하여 배선 사이즈 감소는 필수적이며, 배선 사이즈를 줄이기 위하여 더욱 진보된 배선 구조 및 새로운 대체 물질이 지속적으로 연구, 개발되어야 한다.As is well known, as the degree of integration of semiconductor elements increases, a conductive layer is formed and formed on a substrate in multiple layers. Such a multi-layered wiring can achieve higher integration due to the reduction of the area of the semiconductor device and the reduction of design rules. In order to carry out the multi-layered wiring, it is necessary to reduce the wiring size, and further advanced wiring structures and new alternative materials must be continuously researched and developed to reduce the wiring size.

상기와 같이 배선 사이즈를 줄이기 위한 배선 구조의 하나로 이중 다마신 공정이 있다. 이중 다마신 공정은 게이트 전극과 대응하는 트랜치 및 선택된 접합 영역을 노출시키는 비아홀을 형성한 후, 트랜치 및 비아홀 내부에 도전재료를 동시에 매립시키는 기술이다. 즉, 이중 다마신 공정에 있어서 도전재료는 전형적으로 구리 및 구리합금의 금속에 의해 매립되며, CMP 공정에 의해 평탄화하는 과정을 통해 구리 패턴을 형성한다. As described above, one of the wiring structures for reducing the wiring size is a dual damascene process. The dual damascene process is a technique for forming a via hole exposing a gate electrode and a corresponding trench and a selected junction region, and then simultaneously embedding a conductive material in the trench and via hole. That is, in the dual damascene process, the conductive material is typically embedded by the metal of copper and copper alloy, and forms a copper pattern through the planarization process by the CMP process.

그러나, 상기와 같이 이중 다마신 공정을 수행함에 있어서, CMP 공정에 의해 매립된 구리 및 구리합금의 금속을 평탄화할 수 있는데, 평탄화하는 과정에서 스크래치나 파티클 등으로 인하여 평탄화가 완전하게 되지 않아 구리 패턴간에 큰 파티클(PT)이 발생한다. 이러한 큰 파티클(PT)은 발생함과 동시에 검사하여 불량 웨이퍼로서 폐기시켜야 하나, 현재로서는 발생된 큰 파티클(PT)을 검사하지 않은 상태에서 바로 후속 공정, 즉 IMD를 거쳐 더욱더 성장할 경우, 반도체 소자의 제품 불량을 발생하게 하여 반도체 소자의 수율을 현저하게 감소시키게 되는 문제점을 갖는다. However, in performing the double damascene process as described above, the metal of the copper and copper alloy buried by the CMP process can be planarized. In the planarization process, the planarization is not completed due to scratches or particles. Large particles (PT) are generated in the liver. These large particles (PT) should be generated and inspected and discarded as defective wafers, but at present, if the large particles (PT) generated are grown in the immediate process, i. There is a problem that the product defects are caused to significantly reduce the yield of the semiconductor device.

이에, 본 발명은 상술한 문제점을 해결하기 위해 안출한 것으로, 그 목적은 이중 다마신 공정에 있어서, 구리 매립 공정 및 구리 CMP 공정과, IMD 산화막 증착 및 PR 도포와, PR 패턴 마스크로 IMD 산화막 선택적 제거, PR 패턴 제거 공정을 거쳐 구리 패턴 상에 발생되는 큰 파티클(PT)에 의해 생성된 돌출부를 제거할 수 있는 반도체 소자의 제조방법을 제공함에 있다. Accordingly, the present invention has been made to solve the above-mentioned problems, the purpose of the dual damascene process, copper buried process and copper CMP process, IMD oxide film deposition and PR coating, IMD oxide film selective with PR pattern mask The present invention provides a method of manufacturing a semiconductor device capable of removing protrusions generated by large particles (PT) generated on a copper pattern through removal and PR pattern removal processes.

이러한 목적을 달성하기 위한 본 발명의 관점에서 반도체 소자의 제조방법은 기판상에 이중 다마신 구조의 콘택 홀을 형성한 후, 구리(Cu)를 매립시키며, 매립된 구리를 CMP 공정을 통해 평탄화하여 구리 패턴을 형성하는 과정과, 평탄화 과정에서 발생된 기판상의 파티클(PT) 및 형성된 구리 패턴 상에 IMD 산화막을 전면 증착하면, 발생된 파티클로 인하여 돌출부가 생성되는 과정과, IMD 산화막 증착이 완료된 후, 파티클로 인하여 생성된 돌출부를 제거하기 위해 감광막(Photo Resist, PR)을 도포하여 PR 패턴을 형성하는 과정과, 형성된 PR 패턴을 마스크로 이용하여 IMD 산화막을 선택적으로 제거하여 파티클에 의해 생성된 돌출부를 제거하는 과정과, 형성된 PR 패턴을 제거하고, 후속 공정인 PR 마스킹을 형성하는 과정을 포함하는 것을 특징으로 한다. In the aspect of the present invention for achieving the above object, a method of manufacturing a semiconductor device is formed by forming a contact hole of a double damascene structure on a substrate, and then embedded copper (Cu), and planarized copper by a CMP process Forming a copper pattern, and depositing an IMD oxide film on the substrate (PT) and the formed copper pattern on the substrate generated during the planarization process, the protrusions are generated by the generated particles, and after the deposition of the IMD oxide film is completed A process of forming a PR pattern by applying a photoresist (PR) to remove the protrusion generated by the particles, and selectively removing the IMD oxide film using the formed PR pattern as a mask, generates the protrusion formed by the particles. And removing the formed PR pattern and forming a PR masking which is a subsequent process.

또한, 상술한 목적을 달성하기 위한 본 발명의 다른 관점에서 반도체 소자의 제조방법은 기판상에 이중 다마신 구조의 콘택 홀을 형성한 후, 구리를 매립시키며, 매립된 구리를 CMP 공정을 통해 평탄화하여 구리 패턴을 형성하는 제1과정과, 평탄화 과정에서 발생된 기판상의 파티클 및 형성된 구리 패턴 상에 IMD 산화막을 전면 증착하면, 발생된 파티클로 인하여 돌출부가 생성되는 제2과정과, IMD 산화막 증착이 완료된 후, 파티클로 인하여 생성된 돌출부를 제거하기 위해 PR을 도포하여 PR 패턴을 형성하는 제3과정과, 형성된 PR 패턴을 마스크로 이용하여 IMD 산화막을 선택적으로 제거하여 파티클에 의해 생성된 돌출부를 제거하는 제4과정과, 형성된 PR 패턴을 제거하는 제5과정과,제3과정 내지 제5과정을 반복 실시하는 제6과정을 포함하는 것을 특징으로 한다. In addition, in another aspect of the present invention for achieving the above object is a method of manufacturing a semiconductor device is formed in the contact hole of the double damascene structure on the substrate, and then buried copper, planarizing the embedded copper through the CMP process The first step of forming a copper pattern, the entire surface of the particle formed on the substrate generated during the planarization process and the entire surface of the IMD oxide film formed on the formed copper pattern, the second process of generating a protrusion due to the generated particles, and the IMD oxide film deposition After completion, a third process of forming a PR pattern by applying PR to remove the protrusions generated by the particles, and selectively removing the IMD oxide film using the formed PR pattern as a mask to remove the protrusions generated by the particles And a fifth process of removing the PR pattern, and a sixth process of repeating the third to fifth processes. The.

이하, 본 발명의 실시예는 다수개가 존재할 수 있으며, 이하에서 첨부한 도면을 참조하여 바람직한 실시 예에 대하여 상세히 설명한다. 이 기술 분야의 숙련자라면 이 실시 예를 통해 본 발명의 목적, 특징 및 이점들을 잘 이해하게 될 것이다. Hereinafter, a plurality of embodiments of the present invention may exist, and a preferred embodiment will be described in detail with reference to the accompanying drawings. Those skilled in the art will appreciate the objects, features and advantages of the present invention through this embodiment.

본 발명의 핵심 기술요지는, 이중 다마신 공정에서의 패턴 형성을 위한 기판(101) 상에 이중 다마신 구조의 콘택 홀을 형성한 후, 구리(103)(혹은, 구리 합금)를 매립시킨다. 이후, 매립된 구리(103)를 CMP 공정을 통해 평탄화하여 구리(103) 패턴을 형성한다. 다음으로, CMP 공정에 의해 구리(103) 패턴이 평탄화되는 과정에서 일 예로, 큰 파티클(105)이 발생면서 평탄화된 구리(103) 패턴 상에 IMD 산화막(107)을 전면 증착하면 큰 파티클(105)로 인하여 돌출부(108)가 생성된다.
IMD 산화막(107) 증착이 완료된 후, IMD 산화막(107) 상에 발생된 큰 파티클(PT)(105)로 인하여 생성된 돌출부(108)를 제거하기 위해 PR을 도포하게 되면, PR 패턴(109)이 형성된다.
이후, 공지의 포토리소그라피 공정에서의 노광 및 현상 기술에 의하여 PR 패턴(109)을 마스크로 이용하여 IMD 산화막(107)을 선택적으로 제거하면, 결론적으로 큰 파티클(PT)(105)에 의해 생성된 돌출부(108)가 제거된다.
마지막으로, PR 패턴(109)을 제거한 후, 후속 정상 PR 마스킹(111) 공정을 진행하는 것으로, 이러한 기술적 수단을 통해 본 발명에서 목적으로 하는 바를 쉽게 달성할 수 있다.A key technical aspect of the present invention is to form a contact hole of a dual damascene structure on a substrate 101 for pattern formation in a dual damascene process, and then embed copper 103 (or a copper alloy). Thereafter, the embedded copper 103 is planarized through a CMP process to form a copper 103 pattern. Next, in the process of planarizing the copper 103 pattern by the CMP process, for example, when the large particle 105 is generated and the entire surface of the IMD oxide film 107 is deposited on the planarized copper 103 pattern, the large particle 105 is formed. Protrusions 108 are created by < RTI ID = 0.0 >
After deposition of the IMD oxide layer 107 is completed, PR is applied to remove the protrusion 108 generated due to the large particle (PT) 105 generated on the IMD oxide layer 107. Is formed.
Subsequently, if the IMD oxide film 107 is selectively removed using the PR pattern 109 as a mask by exposure and development techniques in a known photolithography process, in conclusion, it is generated by the large particle (PT) 105. The protrusion 108 is removed.
Finally, after the PR pattern 109 is removed, a subsequent normal PR masking 111 process is performed, and thus, the object of the present invention can be easily achieved through such technical means.

도 1a 내지 도 1i는 본 발명에 따른 반도체 소자의 제조방법에서 구리 패턴 상에 발생되는 큰 파티클(Large PT)을 제거하기 위한 과정을 나타내는 공정 순서도이다. 1A to 1I are process flowcharts showing a process for removing large particles (Large PT) generated on a copper pattern in a method of manufacturing a semiconductor device according to the present invention.

도 1a를 참조하면, 이중 다마신 공정에서의 패턴 형성을 위한 기판(101) 상에 이중 다마신 구조의 콘택 홀을 형성한 후, 도 1b와 같이 구리(103)(혹은, 구리 합금)를 매립시킨다. Referring to FIG. 1A, after forming a contact hole having a dual damascene structure on a substrate 101 for pattern formation in a dual damascene process, embedded copper 103 (or a copper alloy) as shown in FIG. 1B. Let's do it.

이후, 도 1c에 도시된 바와 같이, 매립된 구리(103)를 CMP 공정을 통해 평탄화하면, 도 1d와 같이 구리(103) 패턴이 형성되는데, 도시된 바와 같이, 연마하는 과정에서 스크래치나 파티클 등으로 인하여 평탄화가 완전하게 되지 않아 구리(103) 패턴 상에 큰 파티클(PT)(105)이 발생할 수도 있다. 여기서, CMP 공정을 통해 연마하는 과정에서 스크래치나 파티클 없이 평탄화할 경우, 구리(103) 패턴간에 큰 파티클(PT)(105)이 발생하지 않는다. Subsequently, as shown in FIG. 1C, when the embedded copper 103 is planarized through a CMP process, a copper 103 pattern is formed as shown in FIG. 1D. As illustrated, scratches, particles, and the like are polished. Due to this, the planarization may not be completed, and large particles (PT) 105 may be generated on the copper 103 pattern. Here, in the case of planarization without scratches or particles in the polishing process through the CMP process, large particles (PT) 105 are not generated between the copper 103 patterns.

다음으로, CMP 공정에 의해 구리(103) 패턴이 평탄화되는 과정에서 일 예로, 도 1e에 도시된 바와 같이 큰 파티클(105)이 발생면서 평탄화된 구리(103) 패턴 상에 층간 물질(Intermetallic dielectric, IMD) 산화막(107)을 전면 증착하면 도시된 바와 같이 발생된 큰 파티클(105)로 인하여 돌출부(108)가 생성된다. Next, in the process of planarizing the copper 103 pattern by the CMP process, for example, as shown in FIG. 1E, as the large particles 105 are generated, an intermetallic dielectric, Full deposition of the IMD) oxide film 107 produces a protrusion 108 due to the large particles 105 generated as shown.

IMD 산화막(107) 증착이 완료된 후, 일 예로, 도 1f에 도시된 바와 같이, IMD 산화막(107) 상에 발생된 큰 파티클(PT)(105)로 인하여 생성된 돌출부(108)를 제거하기 위해 감광막(Photo Resist, PR)을 도포하게 되면, 도시된 바와 같이 PR 패턴(109)이 형성된다. 여기서, PR은 적어도 5000Å 이하의 두께로 적용한다. After the deposition of the IMD oxide layer 107 is completed, for example, as shown in FIG. 1F, to remove the protrusion 108 generated due to the large particles (PT) 105 generated on the IMD oxide layer 107. When the photoresist (PR) is applied, a PR pattern 109 is formed as shown. Here, PR is applied with a thickness of at least 5000 mm 3 or less.

이후, 공지의 포토리소그라피 공정에서의 노광 및 현상 기술에 의하여 PR 패턴(109)을 마스크로 이용하여 IMD 산화막(107)을 선택적으로 제거하면, 일 예로, 도 1g와 같이 결론적으로 큰 파티클(PT)(105)에 의해 생성된 돌출부(108)가 제거된다. Thereafter, if the IMD oxide film 107 is selectively removed using the PR pattern 109 as a mask by exposure and development techniques in a known photolithography process, for example, as shown in FIG. The protrusion 108 created by 105 is removed.

다음으로, 도 1h에 도시된 바와 같이, PR 패턴(109)을 제거한다. Next, as shown in FIG. 1H, the PR pattern 109 is removed.

여기서, 도 1i는 도 1a 내지 도 1g에 도시된 공정 과정과 같이, 큰 파티클(PT)(105)에 의해 생성된 돌출부(108)가 제거된 후, 후속 정상 PR 마스킹(111) 공정을 진행한 도면이다. Here, FIG. 1I illustrates the process of the normal PR masking 111 process after the protrusion 108 generated by the large particle PT 105 is removed, as shown in FIGS. 1A to 1G. Drawing.

한편, 상기와는 달리 본 발명은, 도 1f에서의 PR(109) 도포, 도 1g에서의 PR(109) 패턴을 마스크로 이용하여 IMD 산화막(107)을 선택적으로 제거, 도 1h에서의 PR(109) 패턴 제거 공정을 반복 실시하여 큰 파티클(PT)(105)에 의해 생성된 돌출부(108)를 보다 확실하게 제거할 수 있다. On the other hand, unlike the above, the present invention selectively removes the IMD oxide film 107 by using the PR 109 coating in FIG. 1F, the PR 109 pattern in FIG. 1G as a mask, and the PR (FIG. 109) The pattern removing process may be repeatedly performed to more reliably remove the protrusion 108 generated by the large particle PT 105.

따라서, 이중 다마신 공정에 있어서, 구리 매립 공정 및 구리 CMP 공정과, IMD 산화막 증착 및 PR 도포와, PR 패턴 마스크로 IMD 산화막 선택적 제거, PR 패턴 제거 공정을 거쳐 구리 패턴 상에 발생되는 큰 파티클(PT)에 의해 생성된 돌출부를 제거함으로써, 기존에서와 같이 큰 파티클(PT)을 검사하지 않은 상태에서 바로 후속 공정, 즉 IMD를 거쳐 더욱더 성장할 경우, 발생되는 반도체 소자의 제품 불량을 해결할 수 있어 반도체 소자의 수율을 향상시킬 수 있다. Therefore, in the dual damascene process, a large particle generated on the copper pattern through a copper buried process and a copper CMP process, an IMD oxide deposition and PR coating, and an IMD oxide selective removal with a PR pattern mask and a PR pattern removal process ( By removing the protrusions generated by PT), it is possible to solve product defects in the semiconductor device, which is generated when further growing through the subsequent process, that is, IMD, without inspecting the large particle PT as before. The yield of the device can be improved.

또한, 본 발명의 사상 및 특허청구범위 내에서 권리로서 개시하고 있으므로, 본원 발명은 일반적인 원리들을 이용한 임의의 변형, 이용 및/또는 개작을 포함할 수도 있으며, 본 명세서의 설명으로부터 벗어나는 사항으로서 본 발명이 속하는 업계에서 공지 또는 관습적 실시의 범위에 해당하고 또한 첨부된 특허청구범위의 제한 범위 내에 포함되는 모든 사항을 포함한다. In addition, since the present invention is disclosed as a right within the spirit and claims of the present invention, the present invention may include any modification, use and / or adaptation using general principles, and the present invention as a matter deviating from the description of the present specification. It includes everything that falls within the scope of known or customary practice in the art to which it belongs and falls within the scope of the appended claims.

상기에서 설명한 바와 같이, 본 발명은 이중 다마신 공정에 있어서, 구리 매립 공정 및 구리 CMP 공정과, IMD 산화막 증착 및 PR 도포와, PR 패턴 마스크로 IMD 산화막 선택적 제거, PR 패턴 제거 공정을 거쳐 구리 패턴 상에 발생되는 큰 파티클(PT)에 의해 생성된 돌출부를 제거함으로써, 기존에서와 같이 큰 파티클(PT)을 검사하지 않은 상태에서 바로 후속 공정, 즉 IMD를 거쳐 더욱더 성장할 경우, 발생되는 반도체 소자의 제품 불량을 해결할 수 있어 반도체 소자의 수율을 향상시킬 수 있는 효과가 있다. As described above, in the dual damascene process, the copper pattern is subjected to a copper embedding process and a copper CMP process, an IMD oxide deposition and PR coating, and an IMD oxide selective removal with a PR pattern mask and a PR pattern removal process. By removing the protrusions generated by the large particles PT generated on the phase, the semiconductor device is generated when it grows further through the subsequent process, that is, IMD, without inspecting the large particles PT as before. Product defects can be solved, thereby improving the yield of the semiconductor device.

삭제delete

Claims (3)

반도체 소자의 제조 방법으로서, As a manufacturing method of a semiconductor device, 기판상에 이중 다마신 구조의 콘택 홀을 형성한 후, 구리(Cu)를 매립시키며, 상기 매립된 구리를 CMP 공정을 통해 평탄화하여 구리 패턴을 형성하는 과정과, Forming a contact hole having a double damascene structure on the substrate, then embedding copper (Cu), and planarizing the embedded copper through a CMP process to form a copper pattern; 상기 평탄화 과정에서 발생된 기판상의 파티클(PT) 및 형성된 구리 패턴 상에 층간 물질(Intermetallic dielectric, IMD) 산화막을 전면 증착하면, 상기 발생된 파티클로 인하여 돌출부가 생성되는 과정과, When the entire surface of the interlayer material (IMD) oxide film is deposited on the PT and the copper pattern formed on the substrate generated during the planarization, a protrusion is generated by the generated particles; 상기 IMD 산화막 증착이 완료된 후, 상기 파티클로 인하여 생성된 돌출부를 제거하기 위해 감광막(Photo Resist, PR)을 도포하여 PR 패턴을 형성하는 과정과, After the deposition of the IMD oxide film is completed, the process of forming a PR pattern by applying a photosensitive film (Photo Resist, PR) to remove the protrusions generated by the particles, 상기 형성된 PR 패턴을 마스크로 이용하여 IMD 산화막을 선택적으로 제거하여 상기 파티클에 의해 생성된 돌출부를 제거하는 과정과, Selectively removing the IMD oxide layer using the formed PR pattern as a mask to remove the protrusions generated by the particles; 상기 형성된 PR 패턴을 제거하고, 후속 공정인 PR 마스킹을 형성하는 과정Removing the formed PR pattern and forming a PR mask that is a subsequent process 을 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 PR은, 적어도 5000Å 이하의 두께로 도포하는 것을 특징으로 하는 반도체 소자의 제조 방법.Said PR is apply | coated to thickness of at least 5000 GPa, The manufacturing method of the semiconductor element characterized by the above-mentioned. 반도체 소자의 제조 방법으로서, As a manufacturing method of a semiconductor device, 기판상에 이중 다마신 구조의 콘택 홀을 형성한 후, 구리를 매립시키며, 상기 매립된 구리를 CMP 공정을 통해 평탄화하여 구리 패턴을 형성하는 제1과정과, Forming a contact hole having a double damascene structure on the substrate, and then burying copper, and planarizing the embedded copper through a CMP process to form a copper pattern; 상기 평탄화 과정에서 발생된 기판상의 파티클 및 형성된 구리 패턴 상에 IMD 산화막을 전면 증착하면, 상기 발생된 파티클로 인하여 돌출부가 생성되는 제2과정과, A second process of forming a protrusion due to the generated particles when the IMD oxide film is entirely deposited on the formed copper pattern and the particles on the substrate generated in the planarization process; 상기 IMD 산화막 증착이 완료된 후, 상기 파티클로 인하여 생성된 돌출부를 제거하기 위해 PR을 도포하여 PR 패턴을 형성하는 제3과정과, After the deposition of the IMD oxide film is completed, a third process of forming a PR pattern by applying PR to remove protrusions generated by the particles; 상기 형성된 PR 패턴을 마스크로 이용하여 IMD 산화막을 선택적으로 제거하여 상기 파티클에 의해 생성된 돌출부를 제거하는 제4과정과, A fourth process of selectively removing an IMD oxide film using the formed PR pattern as a mask to remove protrusions generated by the particles; 상기 형성된 PR 패턴을 제거하는 제5과정과,A fifth process of removing the formed PR pattern; 상기 제3과정 내지 제5과정을 반복 실시하는 제6과정Sixth process to repeat the third to fifth process 을 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a.
KR1020050070548A 2005-08-02 2005-08-02 Method for manufacturing in semiconductor device KR100678015B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050070548A KR100678015B1 (en) 2005-08-02 2005-08-02 Method for manufacturing in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050070548A KR100678015B1 (en) 2005-08-02 2005-08-02 Method for manufacturing in semiconductor device

Publications (1)

Publication Number Publication Date
KR100678015B1 true KR100678015B1 (en) 2007-02-02

Family

ID=38105233

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050070548A KR100678015B1 (en) 2005-08-02 2005-08-02 Method for manufacturing in semiconductor device

Country Status (1)

Country Link
KR (1) KR100678015B1 (en)

Similar Documents

Publication Publication Date Title
JP2002026016A (en) Semiconductor device and method of manufacturing the same
JP2005039244A (en) Electronic device and method of forming multilayer wiring
TWI288459B (en) A dual-damascene process for manufacturing semiconductor device
JP3880929B2 (en) Method for marking an alignment mark on a semiconductor wafer
KR100791697B1 (en) Metal line structure and method for forming metal line of semiconductor device
KR100734690B1 (en) Method for manufacturing in semiconductor device
KR100678015B1 (en) Method for manufacturing in semiconductor device
JP3408746B2 (en) Method for manufacturing semiconductor device
US6452110B1 (en) Patterning microelectronic features without using photoresists
KR100677987B1 (en) Method for manufacturing in semiconductor device
KR20070008118A (en) Method for forming the metal contact of semiconductor device
US6486049B2 (en) Method of fabricating semiconductor devices with contact studs formed without major polishing defects
KR100798275B1 (en) Guard ring of semiconductor device and method for manufacturing the same
KR100363642B1 (en) Method for forming contact hole of semiconductor devices
KR20010009036A (en) A method of forming conductive lines and interconnection thereof
US5854130A (en) Method of forming multilevel interconnects in semiconductor devices
JP2000058647A (en) Manufacture of semiconductor device
KR101069167B1 (en) Method for forming metal line of semiconductor device
KR100349696B1 (en) Method of forming damascene structure for metal interconnection of semiconductor device using chemical swelling process
JP2005079441A (en) Method for manufacturing semiconductor device
JP2007287731A (en) Manufacturing method of semiconductor device
US20020081840A1 (en) Method of manufacturing a semiconductor device including dual-damascene process
JP2001102448A (en) Formation method for wiring
JP2004040019A (en) Method for forming metal wiring
KR20030066999A (en) Method for forming metal wiring of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20111220

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee