KR100677199B1 - Interrupt processing apparatus - Google Patents

Abstract

The present invention relates to an interrupt processing apparatus. In the conventional interrupt processing apparatus, when the interrupt request signal is cleared, the method of clearing after a predetermined time may be ignored due to the host's circumstances. When the read method is cleared, since the interrupt request signal is not cleared by subsequent interrupt sources, the host may not recognize the interrupt re-request, so that the interrupt request may be ignored in any of the above methods. Accordingly, the present invention provides a mask register configured by an external host to accept a plurality of interrupt sources and filter out unwanted interrupts; A first state register storing an interrupt source passed through the mask register; A second state register configured to receive and store the contents of the first state register one clock late; The interrupt request signal is output by the value of the first state register and the interrupt mode set by the external host, or is output after the interrupt request signal is held for a set time, and is cleared by the signal of the external host. The interrupt request signal is cleared by setting the interrupt mode through the configured interrupt processor, and the interrupt request signal is not only held for the set period but also accumulated and stored in the first state register. The host can recognize all interrupt request signals so that there is no lost interrupt request signal.

Description

Interrupt handler {INTERRUPT PROCESSING APPARATUS}

1 is a block diagram of a general interrupt processing apparatus.

2 is an interrupt generation timing diagram of a conventional interrupt processing apparatus.

3 is a general interrupt clear timing diagram of a conventional interrupt processing apparatus.

4 is an unusual interrupt clear timing diagram of a conventional interrupt processing apparatus.

5 is a block diagram of an interrupt processing apparatus of the present invention.

6 is an interrupt clear timing diagram of the present invention.

*** Explanation of symbols for main parts of drawing ***

10: interrupt generation and clearing section 11: interrupt initialization section

12: Status register calculating section 13: Interrupt storing and clearing section

14: interrupt delay unit 15: interrupt generator

30: first state register 40: second state register

The present invention relates to an interrupt processing apparatus. In particular, an interrupt processing apparatus that receives a plurality of interrupt sources to generate a single interrupt request signal effectively clears the interrupt request signal so that the interrupt can be correctly recognized by the external host. One interrupt handler is concerned.

1 is a general interrupt processing apparatus, which includes a mask register 20 set by an external host (not shown) to receive a plurality of interrupt sources IS_1 to IS_N to filter out unwanted interrupts as shown in the figure; A first state register 30 for storing interrupt sources IS_1 to IS_N which have passed through the mask register 20; A second state register 40 which receives and stores the contents of the first state register 30 by one clock; The interrupt request signal IRQ is output according to the value of the first state register 30, and the interrupt generation and clear unit 10 is configured to clear the first state register 30 by a signal of an external host.

The case of operating the above-described general interrupt processing apparatus in a conventional manner will be described in detail as follows.

The interrupt processor 1 is selected by setting a pre-assigned address Add in the external host, and the data DATA is transmitted to set the N-bit mask register 20 to a desired value.

Then, the interrupt sources IS-1 to IS_N inputted by the set mask register 20 are filtered and applied to the N-bit first state register 30, and the interrupt generation and clearing unit 10 is The OR of all contents of the first state register 30 is ORed, and if any one is 1, the interrupt request signal IRQ is output to the host.

At this time, the interrupt sources IS_1 to IS_N are configured to disappear after a predetermined time, and the second state register 40 receives the contents of the first state register 30 after one clock delay.

When the host recognizes the interrupt request signal IRQ, the interrupt processing apparatus 1 is designated by using an address Add, and the value of the first state register 30 is read through the data DATA line. Run the interrupt subroutine.

At this time, the first state register 30 is cleared to reset the interrupt request signal IRQ. In this method, the host reads the value of the first state register 30 and uses the first clear signal at the same time. There is a method of clearing all bits of the state register 30 and a method of resetting all bits by unilaterally sending a clear signal to the first state register 30 from the interrupt generation and clearing unit 10 after a predetermined time elapses.

Among the two methods, the second method of unilaterally clearing the interrupt request signal (IRQ) after a predetermined time elapses can be ignored by interrupting the interrupt request signal (IRQ) when the host is busy processing other tasks. Otherwise, it is difficult to apply, so the first method of clearing the host while reading the value of the first state register will be described.

2 is an interrupt generation timing diagram of a conventional interrupt processing apparatus. As shown in FIG. 2, all operations operate in response to a rising clock in which a constant clock signal clk changes from a low potential to a high potential, and any of interrupt sources IS_1 to IS_N If one is set, the signal is applied to the first state register through the mask register to the next clock, as shown here, which is only set for one clock.

SR1 represents one bit value of the first state register connected to the source of the change among the interrupt sources IS_1 to IS_N, and SR2 represents the second state register bit value of the same position as the first state register. As described above, since the interrupt sources IS_1 to IS_N are set, the corresponding first state register bit SR1 is set at the next clock, thereby simultaneously setting the interrupt request signal IRQ regardless of the clock.

The interrupt request signal IRQ is set even if only one bit of the N-bit first state register is set.

Then, at the next clock, the contents of the first state register are applied to the second state register.

Since the clear signal clear shown is continuously reset, the first state register and the second state register maintain their values, and the interrupt request signal IRQ by the value of the second register also maintains the value.

FIG. 3 is a general interrupt clear timing diagram of a conventional interrupt processing apparatus. As shown in FIG. 3, interrupt source IS_1 to IS_N are set so that the corresponding first phase register bit SR1 is set to the next clock. Accordingly, the interrupt request signal IRQ irrespective of the clock is simultaneously set.

Then, at the next clock, the contents of the first state register are applied to the second state register.

When the host reads the first state register to check the interrupt request signal IRQ, the illustrated clear signal clear is set. At this time, the first state register and the second state register are XORed to perform an Exclusive OR operation. Is stored in the first state register.

Then, since the first and second state registers are set in the clock, the result of XOR becomes 0. Since the value is applied to the first state register in the next clock, the first state register and the interrupt request signal IRQ are It is reset.

FIG. 4 is an unusual interrupt clear timing diagram of a conventional interrupt processing apparatus. As shown in FIG. 4, a portion except for the third of the interrupt sources IS_1 to IS_N is set, and corresponding first and second state register bits are set. The interrupt request signal IRQ is set accordingly.

In the above state, when the third interrupt source IS_3 is set for one additional clock as shown before the clear signal clear is applied, the third bit SR1_3 of the first state register reset at the next clock is shown. ) Is set.

In this case, if a clear signal (clear) is applied to the clock by chance, since the first state register and the second state register performs an XOR operation, all but the third bit SR1_3 of the first state register is reset but the first state. Since the values of the third bit SR1_3 of the register and the third bit SR2_3 of the second state register are different from each other, the first and second state registers remain set even after clearing, and accordingly the interrupt request signal IRQ. It also keeps three.

In this case, the host may not know that the interrupt has been requested again.

In the case of clearing the interrupt request signal, the conventional interrupt processing apparatus as described above may be cleared after a predetermined time. The method may be cleared when the host reads the first state register. Since the host may not recognize the interrupt re-request because the interrupt request signal is not cleared by the incoming interrupt source, the interrupt request may be ignored in any of the above methods.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an interrupt processing apparatus which can prevent the interrupt request signal from being lost by preventing the interrupt request signal from occurring successively.

An interrupt processing apparatus for achieving the object of the present invention as described above comprises a mask register set by an external host to accept a plurality of interrupt sources to filter out unwanted interruptions; A first state register storing an interrupt source passed through the mask register; A second state register configured to receive and store the contents of the first state register one clock late; After interrupting the interrupt request signal for a predetermined period of time by the value of the first state register and the interrupt mode set by the external host, and outputting the same, and performing an XOR operation on the first state register and the second state register according to the clear signal of the external host. And as a result, an interrupt generating and clearing unit for updating the first state register.

The interrupt generation and clearing unit may include an interrupt initialization unit for outputting an interrupt initial signal by a clock signal and an external reset signal; A state register OR operation unit for ORing all bits of the first state register; An interrupt delay unit configured to receive an interrupt mode from an external host, receive an clock signal, and generate an interrupt enable signal to externally output an interrupt request signal within a delay time set for each mode; XOR-operates the first state register and the second state register according to the interrupt enable signal and the clear signal, and clears the first state register with the value, or stores the interrupt source information in which the interrupt request signal is not output, in the first state register. An interrupt storing and clearing unit; And an interrupt generator that is initialized by the output of the interrupt initializer and outputs or suspends an interrupt request signal by the output of the status register OR operator and the state of the interrupt enable signal of the interrupt delay unit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Referring to the configuration and operation of the present invention with reference to the embodiment of Figure 1 and 5 as follows.

A mask register 20 set by an external host to accept a plurality of interrupt sources IS_1 to IS_N to filter out unwanted interrupts; A first state register 30 for storing interrupt sources IS_1 to IS_N which have passed through the mask register 20; A second state register 40 which receives and stores the contents of the first state register 30 by one clock; The interrupt request signal IRQ is output by the value of the first state register 30 and the interrupt mode set by the external host, or is output after the interrupt request signal IRQ is held for a set time, and is output by the signal of the external host. 30 is configured to generate an interrupt generation and clear section 10 to clear.

The interrupt generation and clearing unit 10 includes an interrupt initiation unit 11 for outputting an interrupt initial signal by a clock signal clk and an external reset signal reset; A state register OR operator 12 for ORing all bits of the first state register 30; An interrupt delay unit configured to set an interrupt mode from an external host, receive a clock signal clk, and generate an interrupt enable signal intr_en that does not output an interrupt request signal IRQ to the outside within a delay time set for each mode. 14; The first state register 30 and the second state register 40 are calculated by using the interrupt enable signal intr_en and the clear signal clear of the interrupt delay unit 14, and the first state register 30 is calculated using the interrupt register 14 and the second state register 40. ), Or an interrupt storing and clearing unit 13 for storing interrupt sources IS_1 to IS_N for which the interrupt request signal IRQ is not output to the first state register 30; The interrupt request signal IRQ is initialized by the output of the interrupt initiation unit 11 and is output by the output of the state register OR operation unit 12 and the state of the interrupt enable signal intr_en of the interrupt delay unit 14. It consists of the interrupter generation part 15 which outputs or is suspended.

Looking at the operation of the present invention configured as described above in detail.

Set the pre-allocated address Add in the external host to select the interrupt processing apparatus 1, and transmit the data DATA to set the N-bit mask register 20 and the interrupt delay unit 14 to a desired value. do.

The interrupt delay unit 14 determines the interrupter mode according to the setting of the host. The interrupter mode determines how long the output of the interrupt request signal (IRQ) is prohibited and then resumes the output. Print (intr_en).

Then, the input interrupt sources IS-1 to IS_N are filtered by the set mask register 20 and applied to the first N-bit state register 30 of N bits, and the state register OR operator 12 is made of the first. The contents of the one state register 30 are ORed together and output to the interrupt generator 15.

At this time, the interrupt sources IS_1 to IS_N are configured to disappear after a predetermined time, and the second state register 40 receives the contents of the first state register 30 after one clock delay.

When the host recognizes the interrupt request signal IRQ, the interrupt processor 1 is designated by using an address Add, and the value of the first state register 30 is read through the data line to match the interrupt processing device 1. Run the interrupt subroutine.

In this case, when the address (Add) is interpreted or a clear signal is generated using another signal and applied to the interrupt storage and clearing unit 13, the interrupt storing and clearing unit 13 is the first state register. (30) and the second state register 40 are subjected to XOR operation, the value is applied to the first state register 30 to clear the first state register 30, and this information is applied to the interrupt delay unit 14. To interrupt the interrupt request signal IRQ output by other interrupt sources IS_1 to IS_N for a preset time.

In addition, the interrupt storing and clearing unit 13 supplies an interrupt source IS_1 to IS_N applied to the first state register 30 every clock when the interrupt request signal IRQ is held by the interrupt enable signal intr_en. XOR operation is performed only when the change occurs by monitoring the change of the first state register 30 and the second state register 40, and the value is applied to the same bit of the first state register 30 to interrupt the source. Accumulate and store IS_1 ~ IS_N) requests.

FIG. 6 is an interrupt clear timing diagram according to an embodiment of the present invention as described above. As shown in FIG. 6, a part except for the third of the interrupt sources IS_1 to IS_N is set, and corresponding first and second states are shown. The register bit is already set, and the interrupt request signal IRQ is set accordingly.

In the above state, when the third interrupt source IS_3 is set for one additional clock as shown before the clear signal clear is applied, the third bit SR1_3 of the first state register reset at the next clock is shown. ) Is set.

At this time, if a clear signal (clear) is applied to the clock by chance, the first state register is applied to the first state register by XOR operation of the first state register and the second state register in the interrupt storing and clearing unit 13. All but the 1st bit SR1_3 are reset, but the values of the 3rd bit SR1_3 of the first state register and the 3rd bit SR2_3 of the second state register are different from each other. Bit SR1_3 maintains the set.

The interrupt delay unit 14, which has received the information from the interrupt storing and clearing unit 13, holds the output of the interrupt request signal IRQ by D clock in accordance with the preset interrupt mode. ", The output is suspended for 7 clocks.

By recognizing that the interrupt is requested again to the host through the above-described method, the interrupt sources IS_1 to IS_N generated in the suspended clock D are stored in the first status register so that the interrupt request signal (if IRQ) can be output to notify the host without missing an interrupt.

As described above, the interrupt processing apparatus of the present invention sets the interrupt mode to clear the interrupt request signal and then accumulates the contents of the interrupt source generated during the suspended period as well as the interrupt request signal for the set period. By storing the interrupt request signal, the host can recognize all the interrupt request signals.

Claims (2)

 A mask register set by an external host to accept multiple interrupt sources and filter out unwanted interrupts; A first state register storing an interrupt source passed through the mask register; A second state register configured to receive and store the contents of the first state register one clock late; After interrupting the interrupt request signal for a predetermined period of time by the value of the first state register and the interrupt mode set by the external host, and outputting the same, and performing an XOR operation on the first state register and the second state register according to the clear signal of the external host. And as a result, an interrupt generating and clearing unit for updating the first state register. The method of claim 1, wherein the interrupt generation and clearing unit An interrupt initialization unit for outputting an interrupt initial signal by a clock signal and an external reset signal; A state register OR operation unit for ORing all bits of the first state register; An interrupt delay unit configured to receive an interrupt mode from an external host, receive an clock signal, and generate an interrupt enable signal to externally output an interrupt request signal within a delay time set for each mode; XOR-operates the first state register and the second state register according to the interrupt enable signal and the clear signal, and clears the first state register with the value, or stores the interrupt source information in which the interrupt request signal is not output, in the first state register. An interrupt storing and clearing unit; And an interrupt generator which is initialized by the output of the interrupt initiator and outputs or suspends an interrupt request signal according to the output of a status register OR operator and the state of the interrupt enable signal of the interrupt delay unit.

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