KR100676223B1 - Apparatus for controling nand flash memory - Google Patents

Abstract

A control device for a NAND flash memory is provided to enable a baseband modem to control the NAND flash memory by using an LCD(Liquid Crystal Display) bypass function included in a camera control processor, thereby removing a necessity to assign a special port for controlling the NAND flash memory to the baseband modem. A control device for a NAND flash memory comprises the followings: a NAND flash memory(403) which includes a NAND_CE(Chip Enable) pin, a NAND_CLE(Command Latch Enable) pin, a NAND_WE(Write Enable) pin, a NAND_RE(Read Enable) pin, a NAND_ALE(Address Latch Enable) pin, a NAND_R/B(Ready/Busy) pin and at least one NAND_D pin; a camera control processor; and a baseband modem(401) which controls to read and write data to the NAND flash memory(403) by being connected to the camera control processor.

Description

Control device for NAND flash memory {Apparatus for controling NAND Flash Memory}

1 is a block diagram of a mobile terminal to which a NAND flash memory according to the prior art is applied.

2 is a diagram illustrating a coupling relationship between a baseband modem and a NAND flash memory according to the related art.

3 is a block diagram of a camera control processor for performing the LCD bypass function according to an embodiment of the present invention.

4 is a block diagram of a NAND flash memory control device according to an embodiment of the present invention.

5 is a timing diagram of a process of reading data from a NAND flash according to an embodiment of the present invention.

6 is a timing diagram of a process of writing data to a NAND flash according to a preferred embodiment of the present invention.

7 is a timing diagram of a process of erasing data in a NAND flash according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

303: Camera Control Processor (CCP)

309: LCD

401: baseband modem

403: NAND Flash Memory

The present invention relates to a control device of a NAND flash memory, and more particularly, to an apparatus for controlling a NAND flash memory in a baseband modem using an LCD bypass line included in a camera control processor and a GPIO port included in an LCD bypass. It is about.

ROM, a nonvolatile memory, retains its data without loss even when the power is turned off.It includes a mask ROM that is factory programmed by the manufacturer and an EEPROM that can be electrically programmed and erased repeatedly. There are several kinds. Flash memory refers to an improved form of EEPROM in which an electrical erase operation is performed in units of desired blocks, sectors, or entire chips, and a program can be performed in units of one bit. The flash memory is similar in structure to a disk type auxiliary storage device in which a storage unit is divided into sectors and formatted.

Flash memory architecture can be divided into NOR-type structure in which cells are arranged in parallel between a bit line and a ground line, and NAND-type structure in series. In addition, NOR type is a modified structure. It can be divided into AND type, DINOR type and VGA (Virtual Ground Array) type. NOR flash memory has an advantage in that address decoding for read and program operations is similar to DRAM, thereby simplifying peripheral circuits and reducing read access time. However, NOR flash memory has a disadvantage in that the cell area is larger than NAND flash memory because a contact electrode of a bit line is required for each cell. NAND flash memory has to select the block before the read operation, and the read speed is relatively slow because each cell is connected in series and the operation resistance is large. However, NAND flash memory has a disadvantage compared to NOR flash memory. It has the advantage of excellent density and low price.

Flash memory products can be divided into card type products used for storing memory data of computer memory cards and digital cameras and single chip type products used for micro-code storage of a computer's BIOS (Built-in Operating System) or mobile phones. Can be. A method of controlling a NAND flash memory in a mobile terminal to which a NAND flash memory according to the prior art is applied will now be described with reference to FIGS. 1 and 2.

1 is a block diagram of a mobile terminal to which a NAND flash memory according to the prior art is applied.

Referring to FIG. 1, a conventional mobile terminal includes a baseband modem 101, an LCD bypass 103, an LCD 105, and a NAND type flash memory 107. In particular, the mobile terminal is a terminal including a digital camera function, and the function of the LCD bypass 103 is included in a camera control processor (CCP). The baseband modem 101 performs a normal call function and, although not shown, receives image data from an image sensor and a digital signal processor included in the mobile terminal to perform a digital camera function. That is, the baseband modem 101 receives the image data captured by the image sensor and encoded by the digital signal processor, and transmits the image data to the LCD 105 through the LCD bypass 103. The image data is output to the display unit in the mobile terminal. do. At this time, the NAND flash memory 107 temporarily stores a still image. In this case, the baseband modem 101 receives a separate port to directly control the NAND flash memory 107 in order to control the NAND flash memory 103.

2 is a diagram illustrating a coupling relationship between a baseband modem and a NAND flash memory. As shown in FIG. 2, six control pins (CE, CLE, WE, RE, ALE, R / B) and eight data pins (D [7) are used to read and write data to the NAND flash memory in the baseband modem. ..0]) is required, and it can be seen that the base bend modem 101 is directly coupled with the NAND flash memory 107 by receiving a separate port.

As described above, a method of controlling a NAND flash memory in a conventional mobile terminal requires setting a port for controlling a NAND flash memory in a baseband modem or using a separate chip including a function of controlling a NAND flash memory. There are disadvantages.

An object of the present invention for solving the above problems is to provide a NAND flash memory control device using an LCD bypass line without a separate port allocation for controlling the NAND flash memory in the baseband modem.

Another object of the present invention is to provide a NAND flash memory control apparatus using an LCD bypass line that can reduce the number of ports of a baseband modem and effectively control the NAND flash memory.

In order to achieve the above objects, according to an aspect of the present invention, a NAND flash memory including a NAND_CE pin, a NAND_CLE pin, a NAND_WE pin, a NAND_RE pin, a NAND_ALE pin, a NAND_R / B pin, and at least one NAND_D pin, and the NAND_CE pin. At least four GPIOs coupled to the pin, the NAND_CLE pin, the NAND_ALE pin, and the NAND_R / B pin, LCD_CS pin, LCD_WR pin coupled to the NAND_WE pin, LCD_RD pin coupled to the NAND_RE pin, and the NAND_D pin. And a baseband modem coupled with the camera control processor to control reading and writing of data to the NAND flash memory. A control device can be provided.

In one preferred embodiment, the camera control processor includes LCD_CS pin, LCD_WR pin, LCD_RD pin and LCD_D pin, LCD_WE pin, LCD_RE pin and at least one LCD_D pin, respectively. It further comprises a receiving LCD. Also, the LCD_CS pin, the LCD_WR pin, the LCD_RD, and the LCD_D pin may perform an LCD bypass function. In addition, the NAND_CE pin is a chip enable control signal, the NAND_CLE pin is a command latch enable control signal, the NAND_WE pin is a write enable control signal, the NAND_RE pin is a read enable control signal, the NAND_ALE pin is an address latch enable control signal. The NAND_R / B pins transmit ready / busy control signals, and the NAND_D pins transmit and receive data input / output signals. The baseband modem and the camera control processor may be coupled through an MCS control signal line, an MREN control signal line, an MWEN control signal line, an address control signal line, and a data signal line.

According to another aspect of the present invention, a NAND flash memory including a NAND_CE pin, a NAND_CLE pin, a NAND_WE pin, a NAND_RE pin, a NAND_ALE pin, a NAND_R / B pin, and at least one NAND_D pin, the NAND_CE pin, the NAND_CLE pin, and the A camera control processor including at least three GPIOs coupled to a NAND_ALE pin, an LCD_CS pin coupled to the NAND_WE pin, an LCD_WR pin coupled to the NAND_WE pin, an LCD_RD pin coupled to the NAND_RE pin, and at least one LCD_D pin coupled to the NAND_D pin And a baseband modem coupled to the LCD bypass to control reading and writing of data to the NAND flash memory, wherein the NAND_R / B pin uses a register inside the NAND flash memory. A control device for a flash memory can be provided.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a camera control processor performing a bypass function according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a camera control processor (CCP) according to the present invention is an LCD for coupling with a host interface 305 and an LCD 309 for coupling with a host processor 301. Interface 307, and performs the LCD bypass function. The host processor 301 couples to the host interface 305 of the camera control processor 303 through an MCS control signal, an MREN control signal, an MWEN control signal, an address (ADDR) control signal, and a data signal line. The LCD interface 307 of the camera control processor 303 also couples with the LCD 309 via LCS control signals, LREN control signals, and data signal lines. Here, the MCS control signal and the LCS control signal are for chip selection, the MREN control signal and the LREN control signal are for writing data to the LCD 309, and the MREN control signal and the LREN control signal are for the data of the LCD 309. For reading, the data signal is for sending and receiving data information.

When the host processor 301 attempts to write data to the LCD 309, the host processor 301 writes data to the camera control processor 303, but the host processor 301 uses the LCD 309 as indicated by a dotted line. The data is written to the LCD 309 by operating as if it is directly connected to the same. According to the present invention, when the host processor 301 is a baseband modem, an extra general purpose input / output pin (GPIO) port included in the camera control processor 303 and an LREN signal line and an LWEN signal line used for an LCD bypass function. And a device for controlling a NAND flash memory in a baseband modem using a data signal line.

4 is a block diagram of a control device of a NAND flash memory according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the NAND flash memory control apparatus includes a baseband modem 401, a camera control processor (CCP) 303, a NAND flash memory 403, and an LCD 309. ). The camera control processor 303 shows only the spare GPIO to be used as the control signal line of the LCD bypass and the NAND flash memory 403.

The baseband modem 401 refers to an integrated circuit for wireless communication including a high frequency processor as a baseband processor and performs a normal call function. In addition, the baseband modem 401 transfers the captured image data to the LCD 309 through the camera control processor 303 to perform a function such as a camera, wherein the NAND flash memory 403 pauses the image. Save function.

The CS pin, WR pin, RD pin, A [2..1] pin and D [15..0] pin of the baseband modem 401 are the MCS pin, MWEN pin, MREN pin, Coupling with MA [2..1] pin and MD [15..0] pin respectively. The LCD_CS pin, LCD_WR pin, LCD_RD pin, and LCD_D [15..0] pin of the camera control processor 303 are the LCD_CE pin, LCD_WE pin, LCD_LCD_RE pin, and LCD_D [7..0] pin (or LCD_D) of the LCD 309. And [15..0]) respectively. In addition, the LCD_WR pin, the LCD_RD pin, and the LCD_D [15..0] pin of the camera control processor 303 may also correspond to the NAND_WE pin, the NAND_RE pin, and the NAND_D [7..0] pin of the NAND flash memory 403. To combine. The extra GPIOs of the camera control processor 303 couple with the NAND_CE pin, the NAND_CLE pin, the NAND_ALE pin, and the NAND_R / B pin of the NAND flash memory 403, respectively. A feature of the present invention is that the LCD_WR pin, the LCD_RD pin and the LCD_D [15..0] pin of the camera control processor 303 are shared with the NAND flash memory 403 as well as the LCD 309. .

The NAND flash memory 403 includes six control pins and eight data pins (NAND_D [7..0]) of NAND_CE pin, NAND_CLE pin, NAND_WE pin, NAND_RE pin, NAND_ALE pin, and NAND_R / B pin. In this case, the NAND_CE pin controls a chip enable (CE) control signal, the NAND_CLE pin controls a command latch enable (CLE) control signal, the NAND_WE pin controls a write enable (WE) control signal, and the NAND_RE pin controls a read enable (RE) control. Signal, the NAND_ALE pin receives the address latch enable (ALE) control signal, and the NAND_R / B pin transmits the ready / busy control signal, and the NAND_D pin transmits and receives data input / output signals. Perform.

The camera control processor 303 additionally requires four general purpose input / output pin (GPIO) ports to control the NAND flash memory 403. In this case, the four GPIOs are coupled to the NAND_CE pin, the NAND_CLE pin, the NAND_ALE pin, and the NAND_R / B pin of the NAND flash memory 403, respectively. Accordingly, the baseband modem 401 does not need a separate port for controlling the NAND flash memory 403. When the baseband modem 401 attempts to write data to the NAND flash memory 403, the MWEN signal and the MD [7..0] signal are shared so that the data is synchronized with a write enable (WE) control signal clock. In this case, other control signals required for the NAND flash memory 403 are generated using the GPIO of the camera control processor 303. When the baseband modem 401 tries to read the data of the NAND flash memory 403, the MREN signal and the MD [7..0] signal are shared to read data in accordance with a RE (Read Enable) control signal clock.

The NAND_R / B pin may not be coupled with the GPIO of the camera control processor 303. In this case, the NAND_R / B pin may use an internal register of the NAND flash memory 403. This may reduce the number of GPIOs required for the camera control processor 303.

5 is a timing diagram of a process of reading data from a NAND flash according to an exemplary embodiment of the present invention.

Referring to FIG. 5, it is assumed that the CLE, CE, ALE, and R / B signals of the timing signals use the GPIO ports of the camera control processor (CCP), and in turn, GPIO1, GPIO2, GPIO3, and GPIO4. Among the timing signals, the WE and RE / I / O signals use the LCD Bypass signal of the camera control processor. The operation sequence is as follows.

First, the basebend modem uses the GPIO2 pin of the camera control processor to activate the NAND flash chip with the chip enable signal low (step 1). The baseband modem then uses the GPIO1 pin to enable the Command Latch Enable (CLE) signal high to enable the command latch (step 2), then through the I / O signal line of the LCD bypass to read the command signal. Transfer (Read Command) to the NAND flash memory (step 3). The baseband modem then uses the GPIO1 pin to pull the Command Latch Enable (CLE) signal low (step 4). At this time, the baseband modem sets the address latch high (ALE) signal to high to enable the address latch (step 5), and then writes address data to the NAND flash memory through the I / O signal line (step 5). 6 to step 8). The baseband modem then sets the Address Latch Enable (ALE) signal to Low (step 9), and the R / B (Read / Busy) signal connected to the GPIO4 pin will go from low to high. Wait for it (step 10). When the read / busy (R / B) signal is high and ready, the baseband modem reads data stored in the NAND flash memory through the I / O signal line (steps 11 to m). The baseband modem deactivates the NAND-type flash memory chip by setting the CE (Chip Enable) signal high after reading the data (step m + 1).

6 is a timing diagram of a process of writing data to a NAND flash according to an exemplary embodiment of the present invention. NAND flash memory is made up of blocks, and one block is made up of pages. The timing diagram of this figure shows a timing diagram which writes data to one page of a NAND flash memory.

Referring to FIG. 6, it is assumed that CLE, CE, ALE, and R / B signals of the timing signals use the GPIO ports of the camera control processor (CCP), and in turn, GPIO1, GPIO2, GPIO3, and GPIO4. Among the timing signals, the WE and RE / I / O signals use the LCD Bypass signal of the camera control processor. The operation sequence is as follows.

First, the basebend modem uses the GPIO2 pin of the camera control processor to activate the NAND flash chip with the chip enable signal low (step 1). The baseband modem then uses the GPIO1 pin to set the command latch enable (CLE) high to enable the command latch (step 2), and then write command signals through the I / O signal line of the LCD bypass. (Sequential Data Input Command) is transferred to the NAND flash memory (step 3). The baseband modem then uses the GPIO1 pin to pull the Command Latch Enable (CLE) signal low (step 4). The baseband modem then uses the GPIO3 pin to turn the address latch enable (ALE) signal high to enable the address latch (step 5), and then the address data to the NAND flash memory via the I / O signal line. (Step 6 to step 8). The baseband modem then uses the GPIO3 pin to turn the Address Latch Enable (ALE) signal low (step 9), then writes data to the NAND flash memory via the I / O signal line in accordance with the WE signal clock. (Step 10 to step m).

The baseband modem then uses the GPIO1 pin to bring the command latch enable (CLE) signal high to enable the command latch (step m + 1). The baseband modem then sends the program command to the NAND flash memory via the I / O signal line of the LCD bypass (step m + 2), and read / busy (R / B) signals connected to the GPIO4 pins. Wait until L goes from low to high (step m + 3). When the R / B (Read / Busy) signal is high and ready, the baseband modem transmits a read status command signal to the NAND flash memory through the I / O signal line. (m + 4). The baseband modem uses the GPIO1 pin to bring the CLE (Command Latch Enable) signal low (step m + 5), and the status register of the NAND flash memory through the I / O signal line in accordance with the clock of the RE signal. Read the Status Register value (step m + 6).

7 is a timing diagram of a process of erasing data in a NAND flash according to an exemplary embodiment of the present invention. The timing diagram of this figure shows a timing diagram for erasing data in units of blocks in a NAND flash memory.

Referring to FIG. 7, it is assumed that the CLE, CE, ALE, and R / B signals of the timing signals use the GPIO ports of the camera control processor (CCP), and in turn, GPIO1, GPIO2, GPIO3, and GPIO4. Among the timing signals, the WE and RE / I / O signals use the LCD Bypass signal of the camera control processor. The operation sequence is as follows.

First, the basebend modem uses the GPIO2 pin of the camera control processor to activate the NAND flash chip with the chip enable signal low (step 1). The baseband modem then uses the GPIO1 pin to enable the command latch using the Command Latch Enable (CLE) signal high (step 2), then clears the block automatically through the I / O signal line on the LCD bypass. The command signal for setting (Auto Block Erase Setup Command) is transmitted to the NAND flash memory (step 3). The baseband modem then uses the GPIO1 pin to pull the Command Latch Enable (CLE) signal low (step 4). The baseband modem then uses the GPIO3 pin to turn the address latch enable (ALE) signal high to enable the address latch (step 5), and then the address data to the NAND flash memory via the I / O signal line. (Step 6, Step 7). The baseband modem then uses the GPIO3 pin to bring the ALE (Address Latch Enable) signal low (step 8) and the GPIO1 pin to set the CLE (Command Latch Enable) signal high. Enable the latch (step 9). The baseband modem then sends an erase command signal to the NAND flash memory via the I / O signal line of the LCD bypass (step 10). The baseband modem pulls the Command Latch Enable (CLE) signal low using the GPIO1 pin (step 11). It then waits for the R / B (Read / Busy) signal connected to the GPIO4 pin to go from low to high (step 12). When the R / B (Read / Busy) signal is high and ready, the baseband modem uses the command latch by setting the Command Latch Enable (CLE) signal high using the GPIO1 pin. Enable it (step 13). The baseband modem then sends a read status command signal (Read Status Command) to the NAND flash memory via the I / O signal line (step 14). The baseband modem then uses the GPIO1 pin to bring the Command Latch Enable (CLE) signal low (step 15), and the status register of the NAND flash memory through the I / O signal line in accordance with the clock of the RE signal. Register) value is read (step 16).

As shown in FIGS. 5 to 7, the baseband modem provides a chip enable (CE) control signal, a command latch enable (CLE) control signal, an address latch enable (ALE) control signal, and a read / busy (R / B) control signal. The GPIO1, GPIO2, GPIO3, and GPIO4 pins of the camera control processor communicate with the NAND flash memory. In addition, the baseband modem uses the LCD bypass of the camera control processor for read enable (RE) control, write enable (WE) control, and data signals to read and write data to and from the NAND flash memory.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

According to the present invention, since the baseband modem controls the NAND flash memory using the LCD bypass function included in the camera control processor, the baseband modem does not need to allocate a separate port for controlling the NAND flash memory.

Claims (6)

A NAND flash memory including a NAND_CE pin, a NAND_CLE pin, a NAND_WE pin, a NAND_RE pin, a NAND_ALE pin, a NAND_R / B pin, and at least one NAND_D pin; At least four GPIOs coupled to the NAND_CE pin, the NAND_CLE pin, the NAND_ALE pin, and the NAND_R / B pin, LCD_CS pin, LCD_WR pin coupled to the NAND_WE pin, LCD_RD pin coupled to the NAND_RE pin, and the NAND_D A camera control processor comprising at least one LCD_D pin coupled to the pin; And Baseband modem in combination with the camera control processor to control reading and writing data to the NAND flash memory Control device of the NAND flash memory comprising a. The method of claim 1, An LCD_CE pin, an LCD_WE pin, an LCD_RE pin, and at least one LCD_D pin coupled with LCD_CS pin, LCD_WR pin, LCD_RD, and LCD_D pins of the camera control processor, respectively, and an LCD controlled by the baseband modem. The control device of the NAND flash memory further comprising. The method of claim 2, The LCD_CS pin, the LCD_WR pin, the LCD_RD, and the LCD_D pin perform an LCD bypass function. NAND flash memory control device characterized in that. The method of claim 1, The NAND_CE pin receives a Chip enable control signal from the baseband modem through the GPIO of the camera control processor, and the NAND_CLE pin receives a command latch enable control signal from the baseband modem through the GPIO of the camera control processor. Respectively, wherein the NAND_WE pin receives a write enable control signal from the baseband modem through the LCD_WR pin of the camera control processor, and the NAND_RE pin receives a read enable control signal from the baseband modem to the camera control processor. The NAND_ALE pin receives an address latch enable control signal from the baseband modem through the GPIO of the camera control processor, and the NAND_R / B pin receives a ready / busy control signal from the camera control. The base via the processor's GPIO Transmitting a de-modem, and said NAND_D pin is to transmit and receive the baseband modem and the data input and output signals through LCD_D pin of the camera control processor NAND flash memory control device characterized in that. The method of claim 1, Combining the baseband modem and the camera control processor through an MCS control signal line, an MREN control signal line, an MWEN control signal line, an address control signal line, and a data signal line; NAND flash memory control device characterized in that. A NAND flash memory including a NAND_CE pin, a NAND_CLE pin, a NAND_WE pin, a NAND_RE pin, a NAND_ALE pin, a NAND_R / B pin, and at least one NAND_D pin; At least three GPIOs coupled to the NAND_CE pin, the NAND_CLE pin and the NAND_ALE pin, an LCD_WR pin coupled to the NAND_WE pin, an LCD_RD pin coupled to the NAND_RE pin, and at least one coupled to the NAND_D pin. A camera control processor including at least an LCD_D pin; And Baseband modem in combination with the camera control processor to control reading and writing data to the NAND flash memory Wherein the NAND_R / B pin uses a register inside the NAND flash memory. NAND flash memory control device characterized in that.

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