KR100674897B1 - Semiconductor device with low-dielectric insulating interlayer and method therefor - Google Patents

Semiconductor device with low-dielectric insulating interlayer and method therefor Download PDF

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KR100674897B1
KR100674897B1 KR1020000061027A KR20000061027A KR100674897B1 KR 100674897 B1 KR100674897 B1 KR 100674897B1 KR 1020000061027 A KR1020000061027 A KR 1020000061027A KR 20000061027 A KR20000061027 A KR 20000061027A KR 100674897 B1 KR100674897 B1 KR 100674897B1
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film
insulating film
semiconductor substrate
dielectric constant
contact hole
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KR20020030411A (en
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김영대
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 저유전율 막을 사용한 층간 절연막 형성 방법 및 이에 의해 형성된 반도체 소자에 관한 것이다. 콘택홀 플러그가 형성되는 영역에는 PE-TEOS 막과 HDP(High Density Plasma) 막의 이중막으로 이루어진 절연막을 형성하고 나머지 영역에는 저유전율 막으로 구성하여 층간 절연막 구조를 이원화함으로써 기생 캐패시턴스의 실질적 증가가 없으면서도 콘택홀 내에 도전성 물질이 채워져 플러그를 형성할 때, 플러그 내의 보이드 형성을 억제하여 안정적인 콘택홀 구조를 포함한 층간 절연막을 얻을 수 있다.       The present invention relates to a method for forming an interlayer insulating film using a low dielectric constant film and a semiconductor device formed thereby. An insulating film composed of a PE-TEOS film and an HDP (High Density Plasma) film is formed in the area where the contact hole plug is formed, and a low dielectric film is formed in the remaining area so that the interlayer insulating film structure is dualized without substantially increasing the parasitic capacitance. Also, when a conductive material is filled in the contact hole to form a plug, void formation in the plug can be suppressed to obtain an interlayer insulating film including a stable contact hole structure.

Description

저유전율 막을 층간 절연막으로 사용한 반도체 소자 및 그 형성 방법 {Semiconductor device with low-dielectric insulating interlayer and method therefor}Semiconductor device using low dielectric constant film as interlayer insulating film and its formation method {Semiconductor device with low-dielectric insulating interlayer and method therefor}

도 1은 종래 기술에 따라 형성된 금속 배선간 절연막을 포함한 반도체 소자의 단면도이다.           1 is a cross-sectional view of a semiconductor device including an inter-wire insulating film formed according to the prior art.

도 2a 내지 도 2c는 본 발명에 의한 금속 배선간 절연막 형성 방법을 나타내는 단면도들이다.           2A to 2C are cross-sectional views illustrating a method for forming an inter-wire insulating film according to the present invention.

본 발명은 반도체 소자 및 그 형성 방법에 관한 것으로, 특히 저유전율 막을층간 절연막으로 사용한 금속 배선간 절연막 형성 방법 및 이에 의해 형성된 층간 절연막을 구비한 반도체 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a method for forming an inter-wire insulating film using a low dielectric constant film as an interlayer insulating film, and a semiconductor device having an interlayer insulating film formed thereby.

반도체 소자가 고집적화되고 소자의 고속 동작이 요구됨에 따라 금속 배선 구조에 있어서 다층 배선 구조의 적용은 필수적이다. 반도체 소자의 집적도가 높아짐에 따라 금속 배선들 간의 간격이 감소되어 기생 캐패시턴스(parasitic capacitance)가 증가되는 문제가 있다. 기생 캐패시턴스의 증가는 시상수를 증가시 켜 신호 지연 등 반도체 소자의 동작 속도를 감소시킨다. 따라서, 가능한 기생 캐패시턴스를 작게 해야 한다. 캐패시터 유전막의 유전율이 작을수록 캐패시턴스는 감소되므로 기생 캐패시턴스를 줄이기 위해 층간 절연막 또는 금속간 절연막으로서 저유전율 막을 사용한다. 유전율이 약 3이하인 저유전율 막으로서 유동성 산화물(Flowable Oxide, Si-O-H 계; 이하 FOX)이 범용적으로 사용되고 있다. As semiconductor devices are highly integrated and high speed operation of the devices is required, application of a multilayer wiring structure to a metal wiring structure is essential. As the degree of integration of semiconductor devices is increased, there is a problem that parasitic capacitance is increased due to a decrease in the distance between metal lines. Increasing the parasitic capacitance increases the time constant, reducing the operating speed of semiconductor devices such as signal delay. Therefore, the parasitic capacitance should be made as small as possible. As the dielectric constant of the capacitor dielectric film is smaller, the capacitance is decreased, so a low dielectric constant film is used as the interlayer insulating film or the intermetallic insulating film to reduce the parasitic capacitance. As a low dielectric constant film having a dielectric constant of about 3 or less, a flexible oxide (Si-O-H type; FOX) is commonly used.

도 1은 종래 기술에 의해 금속 배선간 층간 절연막을 형성하는 방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a method for forming an interlayer insulating film between metal wirings according to the prior art.

도 1에서 반도체 기판(100)상에 하부 금속층(110), 층간 절연막(120,130) 및 상부 금속층(150)이 순차적으로 형성되고, 상부 금속층(150)과 하부 금속층(110)은 층간 절연막(120,130)의 비아홀 플러그(140)를 통해 연결되어 있다. 상기 층간 절연막은 저유전율 막으로서의 FOX 막(120)과 FOX 막(120) 상부에 형성된 PE-TEOS(Plasma Enhanced Tetra Ethyl Ortho Silicate)(130)의 이중막으로 이루어져 있다.In FIG. 1, the lower metal layer 110, the interlayer insulating layers 120 and 130, and the upper metal layer 150 are sequentially formed on the semiconductor substrate 100, and the upper metal layer 150 and the lower metal layer 110 are interlayer insulating layers 120 and 130. It is connected via the via hole plug 140. The interlayer insulating layer includes a double layer of a FOX film 120 as a low dielectric constant film and a Plasma Enhanced Tetra Ethyl Ortho Silicate (PE-TEOS) 130 formed on the FOX film 120.

그런데, 상술한 바와 같은 종래의 저유전율 막을 사용하여 층간 절연막을 형성하는 방법에서 상하로 연결된 FOX 막(120)과 PE-TEOS 막(130)을 사용할 경우 층간 절연막의 전체 유전율이 감소되어 반도체 소자의 동작 속도는 개선된다.그러나, FOX 막은 점도가 있는 물질이므로 비아홀에 텅스텐과 같은 도전성 물질을 채우기 위한 열처리 공정을 진행할때 FOX 막으로부터 방출되는 가스에 의해 비아홀 플러그 내에 보이드(void)가 형성되어 도전성의 감소로 인한 소자 불량, 수율 저하 및 신뢰성 불량 등의 문제점이 있다. However, in the method of forming the interlayer insulating film using the conventional low dielectric constant film as described above, when the FOX film 120 and the PE-TEOS film 130 connected up and down are used, the overall dielectric constant of the interlayer insulating film is reduced, so that However, the operating speed is improved. However, since the FOX film is a viscous material, voids are formed in the via hole plug by the gas emitted from the FOX film during the heat treatment process to fill the via hole with a conductive material such as tungsten. There are problems such as device defects, yield degradation and poor reliability due to the reduction.

따라서, 본 발명이 이루고자 하는 기술적 과제는 층간 절연막 구조를 변경하여 기생 캐패시턴스를 감소시키면서 보이드 없는 안정적인 콘택홀 플러그를 형성할 수 있는 층간 절연막 구조를 구비하는 반도체 소자 및 그 형성 방법을 제공하는데 있다. Accordingly, an aspect of the present invention is to provide a semiconductor device having an interlayer insulating film structure capable of forming a void-free stable contact hole plug while reducing the parasitic capacitance by changing the interlayer insulating film structure, and a method of forming the same.

본 발명이 이루고자 하는 기술적 과제를 달성하기 위하여, 본 발명의 일견지에 따른 저유전율 막을 절연막으로 사용한 반도체 소자는 반도체 기판상에 형성된 금속층, 반도체 기판과 금속층을 연결하는 콘택홀 플러그, 반도체 기판 상에 형성되고 콘택홀 플러그를 둘러싸는 PE-TEOS 막과 HDP 산화막의 이중막으로 이루어진 제1 절연막 및 반도체 기판 상에 형성되고 제1 절연막을 둘러싸는 제2 절연막을 포함한다.In order to achieve the technical problem to be achieved by the present invention, a semiconductor device using a low dielectric constant film according to an aspect of the present invention as an insulating film is a metal layer formed on a semiconductor substrate, a contact hole plug connecting the semiconductor substrate and the metal layer, on the semiconductor substrate And a first insulating film formed of a double layer of a PE-TEOS film and an HDP oxide film formed around the contact hole plug and a second insulating film formed on the semiconductor substrate and surrounding the first insulating film.

또한, 본 발명의 기술적 과제를 달성하기 위하여, 본 발명의 다른 견지에 따르면 반도체 기판상에 PE-TEOS 막과 HDP 산화막의 이중막으로 이루어진 제1 절연막을 형성한다. 제1 절연막의 중앙 부분 일부를 남기고 반도체 기판이 노출될 때까지 제1 절연막을 식각한 후 반도체 기판이 노출된 부분을 제1 절연막의 높이까지 채워 제2 절연막을 형성한다. 남아있는 제1 절연막의 일부를 식각하여 반도체 기판을 노출시키는 콘택홀을 형성하고 콘택홀을 도전 물질로 채워 플러그를 형성한다. 다음, 잔존하는 제1 절연막 상면, 제2 절연막 상면 및 플러그 상에 금속층을 형성한다.       Further, in order to achieve the technical problem of the present invention, according to another aspect of the present invention to form a first insulating film consisting of a double film of a PE-TEOS film and an HDP oxide film on a semiconductor substrate. After etching the first insulating film until the semiconductor substrate is exposed while leaving a part of the central portion of the first insulating film, the second insulating film is formed by filling the exposed portion of the semiconductor substrate to the height of the first insulating film. A portion of the remaining first insulating film is etched to form a contact hole exposing the semiconductor substrate, and the contact hole is filled with a conductive material to form a plug. Next, a metal layer is formed on the upper surface of the remaining first insulating film, the upper surface of the second insulating film, and the plug.                     

이하, 첨부도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다. 그러나, 본 발명의 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 본 발명의 실시예는 본 발명의 개시가 완전해지도록 하며, 당 업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위하여 제공되어지는 것이다. 도면 상에서 동일한 부호로 표시된 요소는 동일한 구성 요소를 의미한다. 또한, 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 라고 기재되는 경우에 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제3의 막이 개재되어질 수도 있다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are intended to complete the present disclosure and to provide a more complete description of the present invention to those skilled in the art. Elements denoted by the same reference numerals in the drawings means the same components. In addition, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween.

이하 도 2a 내지 도 2c를 참고로 본 발명을 상세히 설명한다.      Hereinafter, the present invention will be described in detail with reference to FIGS. 2A to 2C.

도 2a에서 반도체 기판(200) 상에 하부 금속층(210), 절연막(미도시)을 순차적으로 형성한다. 절연막은 PE-TEOS 막과 HDP(High Density Plasma) 막이 순차적으로 구성되는 이중막으로 형성한다. 절연막 상부에 포토 레지스트 마스크(미도시)를 형성하여 비아홀이 형성될 중앙 부분을 둘러싸도록 상기 절연막을 식각하여 제1 절연막(220)을 형성하고 하부 금속층(210)의 표면(230,240)을 노출시킨다. 또한 도 2a 및 도 2b를 참조하면 상기 제1 절연막(220)의 높이방향 두께는 상기 비아홀(260)의 깊이와 동일한 것이 바람직하다. 그리고, 상기 제1 절연막(도 2a의 220)의 측방향 폭은 상기 비아홀(260)의 직경의 두 배 정도가 바람직하다. 따라서 상기 비아홀 형성을 위한 식각 후 남는 제1 절연막(도 2b의 220)은 상기 비아홀(260)을 상기 비아홀의 반경 정도의 두께로 둘러싸는 것이 바람직하다.       In FIG. 2A, a lower metal layer 210 and an insulating layer (not shown) are sequentially formed on the semiconductor substrate 200. The insulating film is formed of a double film in which a PE-TEOS film and an HDP (High Density Plasma) film are sequentially formed. A photoresist mask (not shown) is formed on the insulating film to etch the insulating film so as to surround the central portion where the via hole is to be formed, thereby forming the first insulating film 220 and exposing the surfaces 230 and 240 of the lower metal layer 210. 2A and 2B, the thickness of the first insulating layer 220 in the height direction may be the same as that of the via hole 260. In addition, the lateral width of the first insulating layer 220 of FIG. 2A is preferably about twice the diameter of the via hole 260. Therefore, it is preferable that the first insulating film 220 (FIG. 2B) remaining after the etching for forming the via hole surrounds the via hole 260 with a thickness about the radius of the via hole.

도 2b에서 하부 금속층(210)의 노출된 부분(230,240)이 포함된 기판(200) 전면에 다른 절연막(미도시)을 제1 절연막(220)의 높이 이상으로 형성하고 화학적 기계적 연마방법(Chemical Mechanical Polishing; 이하 CMP)을 이용하여 평탄화시켜 제2 절연막(250)을 형성한다. 제2 절연막(250)으로는 유전율이 약 3 이하인 저유전율 막, 예를 들면 FOX막을 사용한다. 다음, 제1 절연막(220) 상부, 제2 절연막(250) 상부에 포토 레지스트 마스크(미도시)를 형성하고 제1 절연막(220)의 일부를 식각하여 비아홀(260)을 형성한다.     In FIG. 2B, another insulating film (not shown) is formed on the entire surface of the substrate 200 including the exposed portions 230 and 240 of the lower metal layer 210 above the height of the first insulating film 220. The second insulating layer 250 is formed by planarization using CMP. As the second insulating film 250, a low dielectric constant film having a dielectric constant of about 3 or less, for example, a FOX film, is used. Next, a photoresist mask (not shown) is formed on the first insulating film 220 and the second insulating film 250, and a part of the first insulating film 220 is etched to form a via hole 260.

도 2c에서 제1 절연막(220) 상면 및 제2 절연막(250) 상면에 비아홀(260)을 채울 정도로 도전성 물질 예를 들면, 텅스텐층을 형성한 뒤 제2 절연막(250) 상면이 노출될 때까지 CMP를 이용한 평탄화를 진행하여 플러그(270)를 형성한다. 다음, 플러그(270)가 형성된 결과물 상에 상부 금속층(280)을 형성한다. 결과적으로, 하부 금속층(210)과 상부 금속층(280) 사이의 층간 절연막을 비아홀 플러그(270)가 형성되는 영역에는 PE-TEOS 막과 HDP(High Density Plasma) 막의 이중막으로 이루어진 절연막(220)으로 형성하고 나머지 영역에는 저유전율 막(250)으로 구성한다. 상기와 같이 층간 절연막 구조를 이원화함으로써 비아홀 내에 텅스텐과 같은 도전성 물질이 채워져 플러그를 형성할 때, 플러그 내의 보이드 형성을 억제하여 안정적인 비아홀 구조를 얻을 수 있다. 한편, 기생 캐패시턴스의 관점에서 살펴보면, 반도체 소자가 고집적화 됨에 따라 PE-TEOS 막과 HDP(High Density Plasma) 막의 이중막으로 이루어진 절연막(220)이 차지하는 면적은 감소되고 상대적으로 저유전율 막이 차지하는 면적이 증가하므로, 도 1의 구조 변경에 따른 기생 캐패시턴스도 감소하는 효과를 얻을 수 있다.     In FIG. 2C, a conductive material, for example, a tungsten layer is formed on the upper surface of the first insulating film 220 and the upper surface of the second insulating film 250 to form the via hole 260, and then, until the upper surface of the second insulating film 250 is exposed. The planarization using the CMP is performed to form the plug 270. Next, the upper metal layer 280 is formed on the resultant product in which the plug 270 is formed. As a result, the interlayer insulating film between the lower metal layer 210 and the upper metal layer 280 is an insulating film 220 composed of a double film of a PE-TEOS film and a high density plasma film (HDP) film in the region where the via hole plug 270 is formed. The low dielectric constant film 250 is formed in the remaining region. As described above, when the interlayer insulating layer structure is dualized, when a conductive material such as tungsten is filled in the via hole to form a plug, void formation in the plug can be suppressed to obtain a stable via hole structure. On the other hand, in terms of parasitic capacitance, as the semiconductor devices are highly integrated, the area occupied by the insulating film 220 composed of a double film of PE-TEOS film and HDP (High Density Plasma) film is reduced, and the area of the relatively low dielectric film is increased. Therefore, the parasitic capacitance according to the structural change of FIG. 1 may also be reduced.

본 발명의 실시예는 하부 금속층(210)과 상부 금속층(280)을 구비하여 형성되는 금속 배선 형성 방법에 적용하여 설명하였지만, 본 발명은 하부 금속층을 구비하지 않고 저유전율 막을 사용한 층간 절연막내에 홀을 형성하고 금속으로 홀을 채우는 경우에는 모두 적용할 수 있다. 예를 들면, 트랜지스터와 캐패시터의 연결, 비트라인과 트랜지스터의 연결에 적용될 수 있다.        Although the embodiment of the present invention has been described by applying to the metal wiring forming method formed with the lower metal layer 210 and the upper metal layer 280, the present invention does not have a lower metal layer and a hole in an interlayer insulating film using a low dielectric constant film. In the case of forming and filling the hole with metal, all of them can be applied. For example, it can be applied to the connection of the transistor and the capacitor, the connection of the bit line and the transistor.

상술한 바와 같이 본 발명의 저유전율 막을 절연막으로 사용한 반도체 소자 및 그 형성 방법에서 층간 절연막으로 저유전율 막을 사용할 때, 콘택홀 플러그가 형성되는 영역에는 PE-TEOS 막과 HDP(High Density Plasma) 막의 이중막으로 이루어진 절연막을 형성하고 나머지 영역에는 저유전율 막으로 구성하여 층간 절연막 구조를 이원화함으로써 기생 캐패시턴스의 실질적 증가가 없으면서도 콘택홀 내에 도전성 물질이 채워져 플러그를 형성할 때, 플러그 내의 보이드 형성을 억제하여 없이 안정적인 콘택홀 구조를 포함한 층간 절연막을 얻을 수 있다.       As described above, in the semiconductor device using the low dielectric constant film of the present invention as an insulating film and the low dielectric constant film as the interlayer insulating film in the method of forming the same, a double layer of a PE-TEOS film and a high density plasma film (HDP) film is formed in a region where a contact hole plug is formed. By forming an insulating film made of a film and forming a low dielectric constant film in the remaining areas to dualize the interlayer insulating film structure, the formation of the plug is suppressed when the plug is formed by filling a conductive material in the contact hole without substantially increasing the parasitic capacitance. Without this, an interlayer insulating film including a stable contact hole structure can be obtained.

Claims (8)

삭제delete 삭제delete 반도체 기판;Semiconductor substrates; 상기 반도체 기판 상에 형성된 금속층;A metal layer formed on the semiconductor substrate; 상기 반도체 기판과 상기 금속층을 연결하는 콘택홀 플러그;A contact hole plug connecting the semiconductor substrate and the metal layer; 상기 반도체 기판 상에 형성되고 상기 콘택홀 플러그를 둘러싸는 PE-TEOS 막과 HDP 산화막의 이중막으로 이루어진 제1 절연막; 및A first insulating film formed on the semiconductor substrate and comprising a double film of a PE-TEOS film and an HDP oxide film surrounding the contact hole plug; And 상기 반도체 기판 상에 형성되고 상기 제1 절연막을 둘러싸는 유전율이 3 이하인 저유전율 막으로 이루어진 제2 절연막을 포함하는 반도체 소자.And a second insulating film formed on the semiconductor substrate and made of a low dielectric constant film having a dielectric constant of 3 or less surrounding the first insulating film. 제3 항에 있어서, 상기 저유전율 막은 유동성 산화막(FOX)인 반도체 소자.       4. The semiconductor device of claim 3, wherein the low dielectric constant film is a flowable oxide film (FOX). 반도체 기판을 준비하는 단계;        Preparing a semiconductor substrate; 상기 반도체 기판 상에 PE-TEOS 막과 HDP 산화막의 이중막으로 이루어진 제1 절연막을 형성하는 단계;      Forming a first insulating film formed of a double film of a PE-TEOS film and an HDP oxide film on the semiconductor substrate; 상기 제1 절연막이 콘택홀이 형성될 부분을 둘러싸도록 상기 반도체 기판이 노출될 때까지 상기 제1 절연막을 식각하는 단계;      Etching the first insulating film until the semiconductor substrate is exposed such that the first insulating film surrounds a portion where the contact hole is to be formed; 상기 반도체 기판이 노출된 부분을 상기 제1 절연막의 높이까지 채워 유전율이 3이하인 저유전율 막으로 이루어진 제2 절연막을 형성하는 단계;       Filling the exposed portion of the semiconductor substrate to the height of the first insulating film to form a second insulating film made of a low dielectric constant film having a dielectric constant of 3 or less; 남아있는 상기 제1 절연막의 일부를 식각하여 상기 반도체 기판을 노출시키는 상기 콘택홀을 형성하는 단계;       Etching the portion of the remaining first insulating film to form the contact hole exposing the semiconductor substrate; 상기 콘택홀을 도전 물질로 채워 플러그를 형성하는 단계; 및        Filling the contact hole with a conductive material to form a plug; And 잔존하는 상기 제1 절연막 상면, 상기 제2 절연막 상면 및 상기 플러그 상에 금속층을 형성하는 단계를 포함하는 반도체 소자의 형성 방법.  Forming a metal layer on an upper surface of the remaining first insulating film, an upper surface of the second insulating film, and the plug. 제5 항에 있어서, 상기 반도체 기판을 형성하는 단계와 상기 제1 절연막을 형성하는 단계 사이에 상기 반도체 기판 상에 하부 금속층을 형성하는 단계를 더 구비하는 반도체 소자의 형성 방법.       The method of claim 5, further comprising forming a lower metal layer on the semiconductor substrate between forming the semiconductor substrate and forming the first insulating layer. 제5 항에 있어서, 상기 제2 절연막은 유전율이 3이하인 저유전율 막으로 이루어진 반도체 소자의 형성방법.        The method of claim 5, wherein the second insulating film is formed of a low dielectric constant film having a dielectric constant of 3 or less. 제7 항에 있어서, 상기 저유전율 막은 유동성 산화막(FOX)인 반도체 소자의 형성방법.        8. The method of claim 7, wherein the low dielectric constant film is a flowable oxide film (FOX).
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