KR100674546B1 - Semiconductor memory device capable of setting a negative threshold voltage - Google Patents

Abstract

In the memory cell array 1, a word line and a plurality of memory cells MC connected to a bit line are arranged in a matrix. The control circuit 7 controls the potential of the word line and the bit line. When the readout operation is performed from the memory cell connected to the first bit line BLo among the bit lines, the control circuit 7 includes the second bit line BLe disposed adjacent to the first bit line, and the source of the memory cell array. The first voltage is supplied to the line SRC.

Memory Cell Array, Word Line, Bit Line, Source Line, Control Circuit, Constant Voltage Generator Circuit

Description

Semiconductor memory capable of setting negative threshold voltages {SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SETTING A NEGATIVE THRESHOLD VOLTAGE}

1 is a circuit diagram showing a main part of a semiconductor memory device according to the first embodiment.

Fig. 2 is a configuration diagram showing the semiconductor memory device according to the first embodiment.

FIG. 3 is a circuit diagram showing the configuration of the memory cell array 1 and the bit line control circuit 2 shown in FIG.

4A and 4B are cross-sectional views of memory cells and select transistors.

Fig. 5 is a sectional view of an essential part showing a semiconductor memory device according to the first embodiment.

FIG. 6 is a diagram showing voltages supplied to respective units during various operations in the configuration shown in FIG. 5; FIG.

FIG. 7 is a circuit diagram showing an example of the data storage circuit shown in FIG.

8 (a), 8 (b) and 8 (c) are diagrams showing a relationship between data of a memory cell and a threshold voltage of the memory cell.

9 is a diagram showing an example of a writing procedure in the first embodiment.

Fig. 10 is a diagram showing a case where a high breakdown voltage NMOS transistor constituting a row decoder is formed on a P-type substrate.

Fig. 11 is a diagram showing a writing sequence of four values of data.

Fig. 12 is a flowchart showing a writing sequence of four values of data, showing a writing operation of a first page.

Fig. 13 is a flowchart showing a write sequence of four values of data, showing a write operation of a second page.

Fig. 14 is a diagram showing a writing method for self boosting an erase region.

Fig. 15A is a diagram showing the distribution of threshold voltages according to the conventional writing method, and Fig. 15B is a diagram showing the distribution of threshold voltages according to the writing method according to the first embodiment.

FIG. 16 is a diagram showing the configuration of the memory cell array 1 and the data storage circuit 10 according to the fourth embodiment.

17 is a timing chart showing the operation of the positive level read in accordance with the first embodiment.

18 is a timing chart showing the operation of the negative level read in accordance with the first embodiment.

<Explanation of symbols for the main parts of the drawings>

1: memory cell array

2: bit line control circuit

3: column decoder

4: data input / output buffer

5: data input / output terminal

6: word line control circuit

7: control signal and control voltage generating circuit

8: control signal input terminal

10: data storage circuit

71: constant voltage generating circuit

[Patent Document 1] Japanese Patent Application Laid-Open No. 2004-192789

[Patent Document 2] Japanese Patent Laid-Open No. 3-283200

This application is based on the JP Patent application 2004-364902 (December 16, 2004) of this application, and claims the priority, The whole content is taken in here as a reference.

The present invention relates to a semiconductor memory device capable of storing, for example, two or more values of data in one memory cell.

In the NAND flash memory, all or half of the plurality of memory cells arranged in the row (row) direction are connected to corresponding latch circuits through bit lines, respectively. Each latch circuit holds data at the time of writing and reading of the data. All cells arranged in the row direction or half of the cells are collectively written or read out (see Patent Document 1, for example).

In addition, the erase operation is performed in units of blocks, for example. The threshold voltage of the memory cell is made negative by the erase operation, and the threshold voltage is made positive by injecting electrons into the memory cell by the write operation. However, in the NAND type flash memory, since the memory cells are connected in series, in the read operation, the non-selected cell needs to be in the on state. For this reason, a voltage Vread higher than the threshold voltage is applied to the gate of the unselected cell. Therefore, the threshold voltage in the write operation should not exceed Vread. In the write sequence, it is necessary to repeat the program and program verify reads for each bit in order to suppress the threshold voltage distribution so as not to exceed Vread. For this reason, there exists a problem that the program speed becomes slow.

In addition, in order to store a large amount of data, a multi-value memory for storing two or more bits in one cell has been developed. In this multi-value memory, four threshold voltages must be set, for example, in order to store two bits in one cell. For this reason, it is necessary to narrow the distribution of one threshold voltage compared with the memory which stores one bit in one cell. As described above, this control also needs to be repeatedly performed for the program and the program verification, so that there is a problem that the writing speed is lowered.

In addition, when storing three bits or four bits of data in one cell, eight or sixteen threshold voltages must be set. For this reason, the distribution width of one threshold voltage must be made very narrow.

In order to solve this problem, it is conceivable to set the threshold voltage as data also to the negative threshold voltage. In such a configuration, since the set number of the threshold voltages on the positive side can be reduced within the range of Vread, the distribution width of each threshold voltage can be widened, and high-speed writing becomes possible. However, when applying a negative voltage to the gate of the memory cell, it is necessary to supply a negative potential to the word line. For this reason, the high breakdown voltage transistors H. V. Tr. Constituting the row decoder must be formed in the P well structure, and a negative voltage must be applied to the wells. Therefore, there exists a problem that a manufacturing process becomes complicated.

Therefore, at the time of the read and the verify read, the bias voltage is supplied to the source and the well of the cell in accordance with the external power supply or the internal power supply, so that the potential of the source and the well is higher than the potential of the word line. As a result, a technique for reading negative threshold voltages has been proposed in the same manner as in the case where a negative voltage is applied to a word line (see Patent Document 2, for example). However, this technique is applied to the test mode of the memory cell, and this technique is not used in the normal operation mode. In addition, when a bias voltage is applied to the source and the well by the internal power supply circuit, since a large current flows into the internal power supply circuit from a plurality of bit lines (16k to 32k), there is a problem that the internal power supply circuit is not stable. Therefore, there is a demand for a semiconductor memory device capable of setting a negative threshold voltage for a memory cell and enabling stable operation.

According to a first aspect of the present invention, a semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, wherein the memory cells are connected to word lines and bit lines; A control circuit for controlling the potential of a bit line, said control circuit comprising: a second portion disposed adjacent to said first bit line when performing a read operation from a memory cell connected to a first bit line among said bit lines; A first voltage is supplied to a bit line and a source line of the memory cell array.

According to a second aspect of the present invention, a semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, wherein the memory cells are connected to word lines and bit lines, and the word lines and bits. A control circuit for controlling a potential of a line, a source line, and a well, and a constant voltage generating circuit for generating a first voltage and a second voltage, wherein the memory cell includes a first state, a second state to an nth state ( n has n states of two or more natural numbers, and the control circuit is configured to read the states of the first state, the second state to the kth state (k <= n, k is a natural number). The memory cell when the first voltage generated by the constant voltage generation circuit is supplied to a well of the memory cell array and a source line of the memory cell array, and the state of the (k + 1) th to nth states is read. A well of the array and a source line of the memory cell array; 2 Supply the voltage.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

(First embodiment)

FIG. 2 shows the structure of a semiconductor memory device according to the first embodiment, specifically, a NAND flash memory for storing, for example, four values (two bits) of data.

The memory cell array 1 includes a plurality of bit lines, a plurality of word lines, and a common source line. For example, memory cells capable of rewriting data electrically consisting of EEPROM cells are arranged in a matrix. The memory cell array 1 is connected with a bit control circuit 2 and a word line control circuit 6 for controlling the bit lines.

The bit line control circuit 2 reads data of the memory cells in the memory cell array 1 through the bit lines, detects the state of the memory cells in the memory cell array 1 through the bit lines, or detects the bit lines. The write control voltage is applied to the memory cells in the memory cell array 1 to write to the memory cells. The column decoder 3 and the data input / output buffer 4 are connected to the bit line control circuit 2. The data storage circuit in the bit line control circuit 2 is selected by the column decoder 3. Data of the memory cells read into the data storage circuit is output from the data input / output terminal 5 to the outside via the data input / output buffer 4.

The write data input to the data input / output terminal 5 from the outside is input to the data storage circuit selected by the column decoder 3 via the data input / output buffer 4.

The word line control circuit 6 is connected to the memory cell array 1. The word line control circuit 6 selects a word line in the memory cell array 1 and applies a voltage necessary for reading, writing or erasing to the selected word line.

The memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input / output buffer 4, and the word line control circuit 6 are connected to the control signal and the control voltage generation circuit 7. It is controlled by this control signal and control voltage generation circuit 7. The control signal and the control voltage generation circuit 7 are connected to the control signal input terminal 8 and controlled by a control signal input from the outside via the control signal input terminal 8.

The bit line control circuit 2, the column decoder 3, the word line control circuit 6, the control signal and the control voltage generator circuit 7 constitute a write circuit and a read circuit.

3 shows the configuration of the memory cell array 1 and the bit line control circuit 2 shown in FIG. A plurality of NAND cells are arranged in the memory cell array 1. One NAND cell is comprised by the memory cell MC which consists of 32 EEPROM connected in series, and the selection gate S1, S2. The selection gate S2 is connected to the bit line BL0e, and the selection gate S1 is connected to the source line SRC. The control gates of the memory cells MC arranged in each row are commonly connected to the word lines WL0 to WL29, WL30, and WL31. The selection gate S2 is commonly connected to the select line SGD, and the selection gate S1 is commonly connected to the select line SGS.

The bit line control circuit 2 has a plurality of data storage circuits 10. Each data storage circuit 10 includes a pair of bit lines BL0e, BL0o, BL1e, BL1o,... , (BLie, BLio), (BL8ke, BL8ko) are connected.

The memory cell array 1 includes a plurality of blocks, as indicated by broken lines. Each block is composed of a plurality of NAND cells, for example, data is erased in units of blocks. In addition, the erase operation is simultaneously performed on two bit lines connected to the data storage circuit 10.

Further, a plurality of memory cells (memory cells in a range surrounded by broken lines) arranged every other bit line and connected to one word line constitute one sector. Data is written and read for each sector.

In the read operation, the program verify operation, and the program operation, the address signals YA0, YA1, ..., YAi, ... supplied from the outside of the two bit lines BLie, BLio connected to the data storage circuit 10 are provided. , YA8k), one bit line is selected. Further, one word line is selected according to the external address.

4A and 4B show cross-sectional views of memory cells and select transistors. 4A shows a memory cell. An n-type diffusion layer 42 as a source and a drain of the memory cell is formed in the substrate 51 (the P-type well region 55 described later). The floating gate (FG) 44 is formed on the P-type well region 55 via the gate insulating film 43, and the control gate (CG) 46 is disposed on the floating gate 44 via the insulating film 45. Is formed. 4B shows a select gate. An n-type diffusion layer 47 as a source and a drain is formed in the P-type well region 55. The control gate 49 is formed on the P-type well region 55 via the gate insulating film 48.

Fig. 5 shows a sectional view of the semiconductor memory device corresponding to this embodiment. For example, in the P-type semiconductor substrate 51, the N-type well regions 52, 53, and 54 and the P-type well regions 55 and 56 are formed. A P type well region 55 is formed in the N type well region 52, and a low voltage N channel transistor LVNTr constituting the memory cell array 1 is formed in the P type well region 55. In addition, the low voltage P-channel transistor LVPTr and the low voltage N-channel transistor LVNTr constituting the data storage circuit 10 are formed in the N-type well region 53 and the P-type well region 56. In the substrate 51, a high voltage N-channel transistor HVNTr connecting the bit line and the data memory circuit 10 is formed. In the N-type well region 54, for example, a high voltage P-channel transistor HVPTr constituting a word line driving circuit or the like is formed. As shown in Fig. 5, the high voltage transistors HVNTr and HVPTr have, for example, thicker gate insulating films than the low voltage transistors LVNTr and LVPTr.

FIG. 6 shows the voltages supplied to the respective parts shown in FIG. 5 in the positive lead reading the erase voltage, the program, the positive threshold voltage, and the negative read reading the negative threshold voltage.

FIG. 7 is a circuit diagram showing an example of the data storage circuit 10 shown in FIG.

This data storage circuit 10 has a primary data cache PDC, a secondary data cache SDC, a dynamic data cache DDC, and a temporal data cache TDC. The SDC, PDC, and DDC hold input data at the time of writing, hold the read data at the time of reading, temporarily hold data at the time of verification, and are used for operation of internal data when storing multi-value data. The TDC amplifies and temporarily holds the bit line data when data is read, and is used for operation of internal data when storing multi-value data.

The SDC is composed of clocked inverter circuits 61a and 61b and transistors 61c and 61d constituting a latch circuit. The transistor 61c is connected between the input terminal of the clocked inverter circuit 61a and the input terminal of the clocked inverter circuit 61b. The signal EQ2 is supplied to the gate of this transistor 61c. The transistor 61d is connected between the output terminal of the clocked inverter circuit 61b and ground. The signal PRST is supplied to the gate of this transistor 61d. The node N2a of the SDC is connected to the input / output data line IO via the column select transistor 61e, and the node N2b is connected to the input / output data line IOn via the column select transistor 61f. The column select signals CSLi are supplied to the gates of these transistors 61e and 61f. The node N2a of the SDC is connected to the node N1a of the PDC via the transistors 61g and 61h. The signal BLC2 is supplied to the gate of the transistor 61g, and the signal BLC1 is supplied to the gate of the transistor 61h.

The PDC is composed of clocked inverter circuits 61i and 61j and a transistor 61k. The transistor 61k is connected between the input terminal of the clocked inverter circuit 61i and the input terminal of the clocked inverter circuit 61j. The signal EQ1 is supplied to the gate of this transistor 61k. The node N1b of the PDC is connected to the gate of the transistor 611. One end of the current path of the transistor 611 is grounded through the transistor 61m. The signal CHK1 is supplied to the gate of this transistor 61m. The other end of the current path of the transistor 611 is connected to one end of the current path of the transistors 61n and 61o constituting the transfer gate. The signal CHK2n is supplied to the gate of this transistor 61n. The gate of the transistor 61o is connected to the node N3. The signal COMi is supplied to the other end of the current path of the transistors 61n and 61o. This signal COMi is a signal common to all the data storage circuits 10 and is a signal indicating whether or not the verification of all the data storage circuits 10 is completed. That is, as described later, when Verify is completed, the node N1b of the PDC goes low. In this state, when the signals CHK1 and CHK2n are set to high level, when the verification is completed, the signal COMi is set to high level.

In addition, the said TDC is comprised by the MOS capacitor 61p, for example. One end of this capacitor 61p is connected to the connection node N3 of the transistors 61g and 61h, and a signal BOOST described later is supplied to the other end. In addition, the DDC is connected to the connection node N3 through the transistor 61q. The signal REG is supplied to the gate of the transistor 61q.

The DDC is composed of transistors 61r and 61s. The signal VREG is supplied to one end of the current path of the transistor 61r, and the other end thereof is connected to the current path of the transistor 61q. The gate of this transistor 61r is connected to the node N1a of the PDC via the transistor 61s. The signal DTG is supplied to the gate of this transistor 61s.

In addition, one end of the current path of the transistors 61t and 61u is connected to the connection node N3. The signal VPRE is supplied to the other end of the current path of the transistor 61u, and the BLPRE is supplied to the gate. The signal BLCLAMP is supplied to the gate of the transistor 61t. The other end of the current path of the transistor 61t is connected to one end of the bit line BLo via the transistor 61v, and connected to one end of the bit line BLe via the transistor 61w. One end of the bit line BLo is connected to one end of the current path of the transistor 61x. The signal B1ASo is supplied to the gate of this transistor 61x. One end of the bit line BLe is connected to one end of the current path of the transistor 61y. The signal B1ASe is supplied to the gate of this transistor 61y. The signal BLCRL is supplied to the other end of the current path of these transistors 61x and 61y. The transistors 61x and 61y are turned on complementarily to the transistors 61v and 61w in accordance with the signals BlASo and BlASe to supply the potential of the signal BLCRL to the unselected bit lines.

In addition, for example, a MOS capacitor 61z is connected between the node N3 and the ground. The capacitor 61z adjusts the potential of the node N3 so that the potential of the node N3 does not rise excessively by the coupling when boosting the capacitor 61p of the TDC described later by the signal BOOST. Thereafter, the data of the PDC is the potential of the node N1a, the data of the SDC is the potential of the node N2a, the data of the TDC is the potential of the node N3, and the data of the DDC is the potential of the node N4.

Each said signal and voltage are produced | generated by the control signal and control voltage generation circuit 7 shown in FIG. 2, and the following operation | movements are controlled based on the control of this control signal and control voltage generation circuit 7. .

Since this memory is a multivalued memory, it is possible to store two bits of data in one cell. The switching of these two bits is performed by the address (first page, second page).

8A, 8B, and 8C show the relationship between the data of the memory cell and the threshold voltage of the memory cell. When the erase operation is performed, as shown in Figs. 8A and 8C, the data of the memory cell becomes " 0 ". After writing the first page, the data of the memory cell becomes data "0" or data "1". Here, data "0" has a negative threshold voltage and data "1" has a positive threshold voltage.

In addition, as shown in Fig. 8B, after writing the second page, the data of the memory cell becomes data "0", "1", "2", and "3". In the first embodiment, data of the memory cell is defined from the low side to the high side.

9 shows an example of a writing procedure in the first embodiment. Within the block, a write operation is performed for each page in a memory cell close to the source line.

(Read operation)

As shown in Fig. 8A, after writing the first page, the data of the memory cell is " 0 " or " 2 ". For this reason, these data can be read by performing a read operation by setting the potential of the word line to the potential " a " in the middle of the threshold voltage of these data. In addition, after writing the second page, the data of the memory cell is in any one of "0", "1", "2", and "3". For this reason, these data can be read by setting the potentials of the word lines to "b", "c", and "d". Here, for example, the potentials "a" and "b" are negative levels, and the potentials "c" and "d" are positive levels.

(Positive level lead)

First, the reading operation by the positive levels "c" and "d" will be described.

As shown in Figs. 6 and 17, the output voltage of the constant voltage generator circuit 71 shown in Fig. 1 is set to Vss (0V: ground voltage), so that the wells, source lines, and unselected bit lines of the selected cells are selected. Vss (0V) to the select gate of the unselected block, potential "c" or "d" at the time of reading to the select word line, Vread to the unselected word line of the select block, and Vsg (Vdd + to the select gate SGD of the select block. Supply Vth). Vdd is 2.5V, for example, and Vth is the threshold voltage of the N-channel MOS transistor.

Next, Vdd (e.g., 2.5V) is applied to the signal VPRE of the data storage circuit 10 shown in FIG. 7, Vsg (Vdd + Vth) is applied to the signal BLPRE, and (0.6V + Vth) is applied to the signal BLCLAMP. The voltage is supplied once, and the bit line is precharged to, for example, 0.6V. Next, the select line SGS on the source side of the cell is set to Vsg (Vdd + Vth). When the threshold voltage of the cell is higher than "c" or "d", the cell turns off. For this reason, the bit line remains as it is at the H (high) level. In addition, when the threshold voltage of the cell is lower than "c" or "d", the cell turns on. For this reason, the bit lines are discharged through these cells to reach the L (low) level. Here, the signal BLPRE of the data storage circuit 10 shown in FIG. 7 is once set to Vsg (Vdd + Vth) and VPRE = Vdd, and the node of the TDC is precharged to Vdd. Thereafter, the signal BLCLAMP is set to (0.45 V + Vth), for example. The node N3 of the TDC becomes L level when the bit line is lower than 0.45V, and becomes H level when the bit line is higher than 0.45V. Next, after setting signal BLCLAMP = Vss, BLC1 = Vsg (Vdd + Vth) to read the potential of the TDC into the PDC. If the threshold voltage of the cell is lower than the potential " c " or " d " of the word line, the PDC is at L level. If the cell is high, the PDC is at H level, and reading is performed.

(Negative level lead)

Next, the reading operation of negative levels "a" and "b" will be described.

In this case, the negative levels "a" and "b" may be supplied to the selected word line. However, when outputting a negative voltage, as described above, the potential setting of the row decoder is complicated.

That is, as shown in Fig. 10, when the high breakdown voltage NMOS transistor HVNTr constituting the row decoder is formed on the P-type substrate, the drain becomes negative when the transistor control gate CG is set to the negative potential. For this reason, it is necessary to form the high breakdown voltage NMOS transistor HVNTr on the P well. In this case, there exists a problem that a manufacturing process becomes complicated.

Therefore, in the first embodiment, as shown in Fig. 1, the constant voltage generator circuit 71 that generates the voltage Vfix (for example, 1.6 V) is provided, and from the constant voltage generator circuit 71 when the negative level is read. The voltage Vfix (for example, 1.6V) is supplied to the wells, source lines, unselected bit lines, and select gates of the unselected blocks of the selected cells.

That is, as shown in FIG. 1, the transistor 72 is connected between the source line SRC and the constant voltage generator circuit 71, and the transistor (P) in the P type well region 55 in which the memory cell or the selection gate is formed. 73) is connected. One end of the transistor 74 is connected to the source line SRC, and one end of the transistor 75 is connected to the P-type well region 55 in which the memory cell and the selection gate are formed. The other ends of these transistors 74 and 75 are supplied with an erase voltage Vera at the time of erasing. The transistors 72 and 73 are turned off in response to the signal / Sera at the time of erasing data, and are turned on at the time of reading data. In addition, the transistors 74 and 75 are turned on in accordance with the signal Sera at the time of erasing data, and turned off at the time of reading data. The constant voltage generator circuit 71 is provided in the control signal and control voltage generator circuit 7 shown in FIG.

In the above configuration, with reference to FIG. 18, for example, the transistors 61v and 61y are turned on, and the transistors 61w and 71y are turned off to read data at a negative level from a memory cell connected to the bit line BLo. The case will be described. At this time, the transistors 72 and 73 are turned on, and the transistors 74 and 75 are turned off. For this reason, the voltage Vfix (for example, 1.6V) is supplied from the constant voltage generator circuit 71 to the well, the source line SRC, and the unselected bit line of the selected cell. The voltage Vfix (for example, 1.6 V) or Vss is supplied from the constant voltage generator circuit 71 to the selection gate of the unselected block, and the selection gate of the unselected block is turned off.

In addition, the potential Vfix + a (e.g., Vfix + a is 1.1V when a = -0.5V is set) or Vfix + b (e.g., Vfix + b is 0.6 is 0.6) when the selected word line is read. When V) is supplied, a negative potential is supplied to the gate of the cell in appearance. At the same time, Vread + Vfix is supplied to the unselected word line of the selection block, Vsg (Vdd + Vth) + Vfix is supplied to the selection gate SGD of the selection block, and Vfix is supplied to SGS.

Next, Vdd (e.g., 2.5V) is applied to the signal VPRE of the data storage circuit 10 shown in FIG. 7, Vsg (Vdd + Vth) is applied to the signal BLPRE, and (0.6V + Vth) + is applied to the signal BLCLAMP. The voltage of Vfix is supplied and the bit line is precharged, for example, 0.6V + Vfix = 2.2V.

Next, the select line SGS on the source side of the cell is set to Vsg (Vdd + Vth) + Vfix. Since the potential of the well and the source is at Vfix, the cell is turned off when the threshold voltage is higher than "a" (for example, a = -0.5V) or "b" (for example, b = -1V). For this reason, the bit line remains at the H level (for example, 2.2 V). In addition, when the threshold voltage is lower than "a" or "b", the cell turns on. For this reason, the bit line BLo is discharged to become Vfix (for example, 1.6 V) at the same potential as the source line SRC. That is, the potential of the bit line BLo discharges through the cell in the on state, and the charge of the bit line BLo moves to the bit line BLe through the NAND cell, the source line SRC, and the transistors 72 and 61y.

As shown in Fig. 3, the number of bit lines in the memory cell array 1 is, for example, 16k. For this reason, when the charge Q discharged from the bit line flows into the constant voltage generation circuit 71, the operation of the constant voltage generation circuit 71 becomes unstable.

However, in the case of the first embodiment, as shown in Fig. 1, the charge precharged to the bit line is stored in the capacitor C between the selected bit line BLO and the unselected bit line BLe, and the source line SRC. Is connected to the unselected bit line BLe. For this reason, since the charge + Q of the selection bit line BLo cancels out with the charge -Q of the non-selection bit line BLe, it is possible to prevent a large current from flowing into the constant voltage generating circuit 71. Therefore, it is possible to stably maintain the operation of the constant voltage generator circuit 71.

In this state, the signal BLPRE of the data storage circuit 10 shown in FIG. 7 is set to the voltage Vsg (Vdd + Vth), the signal VPRE is set to the voltage Vdd, and the node N3 of the TDC is precharged to Vdd. Thereafter, the signal BOOST is set from the L level to the H level, and TDC = alpha Vdd (for example, alpha = 1.7, alpha Vdd = 4.25V). Here, the signal BLCLAMP is set to, for example, voltage (0.45V + Vth) + Vfix. Then, the node N3 of the TDC becomes L level (Vfix (for example, 1.6V)) when the potential of the bit line is lower than 0.45V + Vfix, and remains at the H level when the potential of the bit line is higher than 0.45V. (? Vdd (for example, 4.25V). Then, after setting signal BLCLAMP = Vtr (for example, 0.1V + Vth), the signal BOOST is set from H level to L level, where TDC is L level. In this case, the voltage is lowered from Vfix (for example, 1.6V), but is not lower than 0.1V because the signal BLCLAMP = Vtr (for example, 0.1V + Vth). For example, from 4.25V)) to Vdd, the potential of the TDC is read into the PDC with the signal BLC1 = Vsg (Vdd + Vth). Thus, the threshold voltage of the cell is either the voltage “a” or the “b”. If lower, the PDC is at L level, if it is high, the PDC is at H level, and reading is performed. In this way, the word line is set to the cell without setting the negative voltage. It is possible to read the negative threshold voltage.

(Program and Program VeriFi)

(program)

Next, a program operation for setting the threshold voltage shown in Fig. 8B will be described. In the program operation, first, an address is specified, and two pages shown in Fig. 3 are selected.

As shown in Fig. 8A, in writing of the first page, the data of the memory cell becomes data " 0 " and data " 2 ". That is, when the write data is "1" (not writing), the data of the memory cell remains in the state of data "0", and when the write data is "0" (writing), the data of the memory cell is Data is "2".

In addition, after writing of the second page, the data of the memory cell becomes data "0", "1", "2", and "3". That is, when the write data of the first page is "1" and the write data of the second page is "1", the data of the memory cell remains "0" and the write data of the second page is "0". In the case of, the data of the memory cell is " 1 ". In addition, when the write data of the first page is "0" and the write data of the second page is "0", the data of the memory cell remains "2" and the write data of the second page is "1". If, the data of the memory cell is " 3 ".

12 shows the program and Verify operations of the first page, and FIG. 13 shows the program and Verify operations of the second page.

(1st page program)

First, the first page is selected by address.

Next, as shown in FIG. 12, data to be written is input from the outside and stored in the SDC of all the data storage circuits 10 (S11). After that, when a write command is input, data of the SDCs in all the data storage circuits 10 are transferred to the PDC (S12). When data "1" (not writing) is input from the outside, the N1a of the PDC becomes H level, and when data "0" (writing) is input, it goes to L level.

(Program operation) (S13)

When a voltage of Vdd + Vth is applied to the signal BLC1 shown in Fig. 7, when the data "1" is stored in the PDC, the potential of the bit line becomes Vdd, and when the data "0" is stored in the PDC, The potential becomes Vss. In addition, writing to a cell of a non-selected page (the bit line is non-selected) connected to the selected word line should not be performed. For this reason, the potential of the bit line connected to these cells is also set to Vdd similarly to the bit line corresponding to the data "1". If the select line SGS of the selected block is supplied with Vdd, Vpgm (20V) is supplied to the selected word line, and Vpass (10V) is supplied to the unselected word line, the cell channel is Vss when the potential of the bit line is Vss. Since the word line becomes Vpgm, writing is performed.

On the other hand, when the potential of the bit line is Vdd, the program is not performed because the channel of the cell is raised to high potential by coupling by raising Vpgm and Vpass instead of Vss.

The program verifier is performed at the "a '" level slightly higher than the "a" level at the time of reading (hereinafter, "'" represents the verifier potential and is set slightly higher than the potential at the time of reading). The program and verification are repeated until the threshold voltage of the memory cell reaches the " a '" level (S14, S15, S13). The Verify operation will be described later.

(2nd page program)

As shown in FIG. 13, first, data to be written is input from the outside, and stored in the SDC of all the data storage circuits 10 (S21).

(Internal Data Lead) (S22)

First, an internal read operation is performed to determine whether the data of the memory cell of the first page is "0" or "2" before writing to the cell. This internal read operation is similar to the negative level read described above, and the read operation is performed by supplying the "a" level to the word line.

(Data Cache Settings) (S23)

Thereafter, the data stored in each data cache is manipulated. That is, data of the SDC is transmitted to the PDC, and data of the PDC is transmitted to the DDC. Next, the data of the DDC is inverted and transmitted to the SDC. Thereafter, the data of the PDC is transmitted to the DDC. Next, the data of the DDC is inverted and transmitted to the PDC. Thereafter, the data of the PDC is transmitted to the DDC. By performing such an operation, when the data of the memory cell is "0 " (data " 1 " on the first page, data " 1 " on the second page), all of the PDC, DDC, and SDC are set to high level.

When the data of the memory cell is " 1 " (data " 1 " on the first page, data " 0 " on the second page), the PDC is set low, the DDC is low, and the SDC is set high.

When the data of the memory cell is " 2 " (data " 0 " on the first page, data " 0 " on the second page), the PDC is set low, the DDC is high level, and the SDC is set low.

When the data of the memory cell is " 3 " (data " 0 " on the first page, data " 1 " on the second page), the PDC, DDC, and SDC are all set to the low level.

In this way, in the state where each data cache is set, the program of the second page is executed similarly to the first page (S24).

Thereafter, program verification is executed using the levels of "b '" "c'" "d '" (S25 to S28 and S24).

Next, the program verifiers of the first and second pages will be described.

Negative Level Program VeriFi Lead

In the above program, data is written from a level at which the threshold voltage is low. For this reason, program verification is performed at the "a '" level on the first page and at the "b'" level on the second page. The program verify operation is almost the same as the read operation.

First, the voltage Vfix (for example, 1.6 V) is supplied from the constant voltage generator circuit 71 to the wells, source lines, unselected bit lines, and select gates of the unselected blocks of the selected cells. The potential Vfix + a 'slightly higher than the potential Vfix + a or Vfix + b at the selected word line (for example, Vfix + a' is 1.2V when a '=-0.4V) or Vfix + b' (example For example, when b '=-0.8V, Vfix + b' is 0.8V), so that a negative potential is supplied to the gate of the cell in appearance. At the same time, Vread + Vfix is supplied to the unselected word line of the selection block, Vsg (Vdd + Vth) + Vfix is supplied to the select line SGD of the selection block, and Vfix is supplied to SGS.

Next, the signal VPRE of the data storage circuit 10 is supplied with the voltage Vdd (for example, 2.5V), Vsg (Vdd + Vth) for the BLPRE, and (0.6V + Vth) + Vfix for the BLCLAMP, for example. , Precharge the bit line to 0.6V + Vfix = 2.2V, for example. Next, the select line SGS on the source side of the cell is set to Vsg (Vdd + Vth) + Vfix. Since the voltages of the wells and sources are Vfix, the threshold voltages of the cells are either VeriFi voltage "a '" (eg a' =-0.4V) or "b '" (eg b' =-0.8V). When higher than), the cell turns off. For this reason, the bit line remains at the H level (for example, 2.2 V), and the cell is turned on when the threshold voltage of the cell is lower than the verification voltage "a '" or "b'". For this reason, the bit line is discharged to have the same potential as the source, that is, Vfix (for example, 1.6 V). During the discharge of the bit line, once VPRE = Vss and BLPRE = Vdd and TDC = L level, copy the DDC to TDC with VREG = Vdd and REG = H levels, and then, once, DTG = Vsg ( Vdd + Vth), the data of the PDC is copied to the DDC, and finally, the data of the TDC is copied to the PDC with BLC1 = H level.

Next, the signal BLPRE of the data storage circuit 10 is set to Vsg (Vdd + Vth), and the node N3 of the TDC is precharged to Vdd. Thereafter, the signal BOOST is set from the L level to the H level, and TDC = alpha Vdd (for example, alpha = 1.7, alpha Vdd = 4.25V). Here, the signal BLCLAMP is, for example, (0.45 V + Vth) + Vfix. The node N3 of the TDC is at an L level (Vfix (e.g., 1.6V)) when the potential of the bit line is lower than 0.45V + Vfix. If the potential of the bit line is higher than 0.45V, it is at the H level (αVdd ( For example, 4.25V). After the signal BLCLAMP = Vtr (for example, 0.1 V + Vth), the signal BOOST is set from the H level to the L level.

Here, the potential of the TDC goes down from Vfix (e.g., 1.6V) when the signal BOOST is at L level. However, since the signal BLCLAMP = Vtr (for example, 0.1V + Vth), the potential of the TDC does not go lower than 0.1V. In addition, when the signal BOOST is at the H level, the potential of the TDC goes from (? Vdd (for example, 4.25V)) to Vdd. Here, when the signal VREG = Vdd and the signal REG = Vsg (Vdd + Vth), when the DDC is at the H level (non-write), the TDC is forced to the H level. However, when the DDC is at the L level (unwritten), the data of the TDC does not change. Next, once the data of the PDC is copied to the DDC with DTG = VSG, the potential of the TDC is read into the PDC with the signal BLC1 = Vsg (Vdd + Vth). Therefore, when the original PDC = L level (write), when the cell's threshold voltage is lower than "a '" or "b'", the PDC goes back to L level (write), and when high, the PDC is H level. It becomes non-write from the next program loop. In the case where the original PDC = H level (non-write), the PDC = H level becomes unwritten from the next program loop.

In addition, in the writing of the second page, the program verification at the "b '" level causes the cells writing at the "c" and "d" levels to be programmed at the "b'" level when the above operation is performed. In pie, it becomes unwritten. However, in the case of writing at the "c '" and "d'" levels, the node N2a of the SDC is set to the L level, and in the case of the writing at the "b '" level, the node N2a of the SDC is set to the H level. For this reason, if the signal BLC2 = Vtr (0.1V + Vth) before the operation of forcibly setting the TDC in the case of non-writing, the TDC is forcibly in the case of writing at the “c '” and “d'” levels. Set to L level, and do not complete writing in program verification at the "b '" level.

Positive Level Program VeriFi Lead

In the writing of the second page, the program and the "b '" level verification are repeated, but after a while, the "c'" level writing is completed. For this reason, the program and the "b '" level and "c'" level verification are repeated. Next, the program is repeated with "b '" level, "c'" level, and "d '" level verification. In addition, since the writing of the "b '" level ends after a while, the program and the "c'" level and the "d '" level verification are repeated. Finally, repeat the program and the "d '" level verification.

First, the reading operation at the positive level "c" and "d" levels will be described.

Vss to the well, the source line, the unselected bit line of the selected cell, the select gate of the unselected block, the potential "c '" or "d'" at the time of reading to the select word line, and the unselected word line of the select block. V read and Vsg (Vdd + Vth) are supplied to the selection gate SGD of the selection block. Next, the signal VPRE of the data storage circuit 10 is set to Vdd (for example, 2.5V), the signal BLPRE is set to Vsg (Vdd + Vth), and the signal BLCLAMP is set to (0.6V + Vth), for example. For example, precharge to 0.6V.

Next, the select line SGS on the source side of the cell is set to Vsg (Vdd + Vth). When the threshold voltage is higher than "c '" or "d'", the cell turns off. For this reason, the bit line remains at the H level. In addition, when the threshold voltage is lower than "c '" or "d'", the bit line is turned to L level because the cell is turned on. During the discharge of the bit line, once VPRE = Vss and BLPRE = Vdd and TDC = L level, the DDC is copied to the TDC with VREG = Vdd and REG = H levels. Next, DTG = Vsg ( Copy the PDC to the DDC, and finally copy the TDC to the PDC with BLC1 = H level. Thereafter, the signal BLPRE is set to Vsg (Vdd + Vth), and the node N3 of the TDC is precharged to Vdd, and then the signal BLCLAMP is set to (0.45V + Vth), for example. The node N3 of the TDC becomes L level when the bit line is lower than 0.45V, and becomes H level when the bit line is higher than 0.45V. After the signal BLCLAMP = Vss, the signal VREG = Vdd and the signal REG = Vsg (Vdd + Vth). When the DDC is at the H level (non-write), the TDC is forced to the H level. However, when the DDC is at the L level (non-write), the value of the TDC does not change. Here, the potential of the TDC is read into the PDC with the signal BLC1 = Vsg (Vdd + Vth). Thus, when the original PDC = L level (write), if the cell's threshold voltage is lower than "c '" or "d'", the PDC goes back to L level (write), and if high, the PDC goes to H level. Then, it will be unwritten from the next program loop. In the case where the original PDC = H level (non-write), the PDC = H level becomes unwritten from the next program loop.

Also, in the writing of the second page, in the program verification at the "c '" level, when the above operation is performed, the writing cell to the "d" level is unwritten in the program verification at the "c'" level. Will be. Therefore, let VREG = Vdd and signal REG = Vsg. Immediately before the operation of forcibly turning the TDC in the case of non-writing into the H level, in the case of writing at the "c" level, the node N1a of the PDC is at the L level, and in the other cases, the node N1a is at the L level. For this reason, the signal BLC1 = Vtr (0.1V + Vth), and in the case of writing at the "d '" level, the TDC is forcibly set to the L level to complete writing from the program verification at the "d'" level. Do not do it.

When the PDC is at the L level, the write operation is performed again, and the program operation and the verify operation are repeated until the data of all the data storage circuits 10 is at the H level.

(Erasing operation)

The erase operation is performed in units of blocks shown by broken lines in FIG. 3. The two bit lines BLie and BLio connected to the data storage circuit 10 are simultaneously executed. First, the transistors 74 and 75 shown in FIG. 1 are turned on, the transistors 72 and 73 are turned off, and the well in which the source line SRC and the memory cell are formed is set to the erase potential Vera = 20 V, and is in the selection block. The potential of the word line is set to 0 V and the other word lines are floating, thereby erasing data of the memory cells in the selection block. After erasing, the cell's threshold voltage becomes data " 0 &quot; (negative threshold voltage) as shown in Fig. 8C.

By the way, in the case of the writing method for erasing the erase area, the threshold voltage of the erase cell needs to be made shallow. First, a writing method for self-boosting this erase area will be described.

This writing method always writes from the source side of the NAND cell, as shown in FIG. The bit line is set to Vss when data is written into the cell, and the bit line is set to Vdd when not writing. Next, for example, when data is written into the selected cell by WL7, WL0 to WL4 are set to Vpass, WL5 is set to Vss, WL6 is set to Vdd, WL7 is set to program voltage Vpgm, and WL8 to WL31 are set to Vpass. In this state, when data is written, writing is performed because the gate of the word line WL7 is Vpgm and the channel is Vss. In addition, in the case of non-writing, the channel is boosted to be Vpass / 2, for example. However, if the number of cells written is large, the channel becomes difficult to boost. By the way, the writing method for self-boosting the erase area is always written from the source side. Therefore, if WL5 = 0 is boosted, the cells of WL8 to WL31 are erased, so the channel is boosted and not written. In this way, the boosted charge must be prevented from moving to the already written cell. However, when the cell selected by the word line WL5 is in an erased state, when the threshold voltage is deep, that is, when the cell is set to a large negative threshold voltage, the cell is not turned off. Therefore, it is necessary to make the threshold voltage of the erase cell shallow, that is, make it the small negative threshold voltage.

Therefore, after the erase operation, all word lines in the block are selected, the program and the program verify read are performed, and the write operation is performed up to the "z" level as shown in Fig. 8C. At this time, in the program and program verifier read operation, all word lines are selected, and the potential of the selected word line at verifiy is set to z + Vfix (for example, 0 V). The process is performed in the same manner as in the VeriFi read.

According to the above embodiment, at least two data of the multi-value data are set by the negative threshold voltage. For this reason, as shown in FIG. 15B, within the range of the read voltage Vread, it is possible to widen the range of the threshold voltage which can be set compared with the conventional case shown in FIG. 15A. Therefore, since the distribution width of one threshold voltage can be set large, the number of programs and verifications can be reduced, and high-speed writing can be performed. In particular, this embodiment is effective when storing 8 or 16 values of data in one memory cell.

In addition, when the negative threshold voltage is read, the voltage Vfix is generated by the constant voltage generator circuit 71, and the voltage Vfix is supplied to the source and the well of the cell so that the potential of the source and the well of the cell is selected. By making it higher than the potential of a line, it is made equivalent to the case where a negative voltage is added to a word line in an external appearance. When the negative threshold voltage is read, the current flowing into the constant voltage generator circuit 71 can be reduced by shorting the source, the well and the unselected bit line. Therefore, it has the effect which can operate the constant voltage generation circuit 71 stably.

Further, according to the embodiment, there is no need to supply a negative voltage to the gate of the cell. For this reason, it is not necessary to form the high breakdown transistor which comprises a row decoder in a P well. Thus, it is possible to prevent an increase in the manufacturing process.

(2nd Example)

In the first embodiment, an operation is performed in which the threshold voltage of the erase cell is -1.6V during the erase sequence. However, as shown in FIG. 11, it is also possible to carry out from the program of a 1st page or the program of a 2nd page.

According to the second embodiment, although the program operation is slightly slowed down, it is possible to speed up the erase operation.

(Third Embodiment)

In the first and second embodiments, the selection of the well, the source line, the unselected bit line, and the unselected block of the selected cell in the positive read and program verify read and the negative read and program verify read. The voltage applied to the gate was changed to Vfix (for example, 1.6V) for negative and Vss for positive. However, the present invention is not limited thereto, and similarly to the negative case, the voltage applied to the well, the source line, the unselected bit line, and the select gate of the unselected block of the selected cell may be Vfix.

According to the third embodiment, in the positive read and the negative read, there is no need to change the read operation. Therefore, positive lead and negative lead can be performed under the same conditions.

Further, in the first and second embodiments, since the read operation of the positive lead and the negative read is different from each other, it is necessary to set a large margin of the threshold voltage. However, in the third embodiment, since the read operation is always the same, it is not necessary to set the margin of the threshold voltage much. Therefore, the distribution width of each threshold voltage of multi-value data can be widened, and high speed writing is attained.

(Example 4)

In the first embodiment, as shown in Fig. 3, one data storage circuit is connected to two bit lines. However, it is not limited to this.

16 shows the configuration of the memory cell array 1 and the data storage circuit 10 according to the fourth embodiment. That is, as shown in Fig. 16, it is also possible to arrange one data storage circuit 10 on one bit line. In this case, for example, the program writes to two bit lines at the same time, at the time of verify read and read, data of one bit line is read, and the other bit line is unselected.

According to the fourth embodiment, since the number of cells to be written at the same time can be doubled as in the first embodiment, it is possible to perform further high-speed writing.

(Example 5)

Like the fourth embodiment, the fifth embodiment also connects one data storage circuit 10 to one bit line. The program writes to the two bit lines at the same time, and reads the data of the two bit lines even at the time of verification read and read. In this case, a current flows into the constant voltage generator circuit 71 (shown in FIG. 1) supplying the source, the well and the intermediate potential. However, since the data of all the bit lines are read at the same time even during the verification read and read, the following is performed. For example, the time until the current of the constant voltage generation circuit 71 is stabilized is secured. Alternatively, first, data is read from a cell with a large current, and after that, except for a cell with a large current, the data is read again from a cell with a small current and the operation is repeated again.

According to the fifth embodiment, the number of cells which are simultaneously written and read can be doubled as in the first embodiment. Therefore, further high speed is possible.

Incidentally, each of the above embodiments has been described for the case of four values, but each embodiment can be applied to a semiconductor memory device for storing data of eight, sixteen, and n values (n is a natural number).

Those skilled in the art can easily create additional advantages and modifications. Accordingly, the invention in its broadest sense is not limited to the description and representative embodiments illustrated and described herein. Accordingly, various modifications are possible without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

According to the present invention, it is possible to provide a semiconductor memory device capable of setting a negative threshold voltage in a memory cell and enabling stable operation.

Claims (22)

In a semiconductor memory device, A memory cell array in which a plurality of memory cells are arranged in a matrix shape, the memory cells being connected to word lines and bit lines; A control circuit for controlling the potential of the word line and the bit line Including, When the readout operation is performed from a memory cell connected to a first bit line among the bit lines, the control circuit includes a second bit line disposed adjacent to the first bit line and a source line of the memory cell array. 1 semiconductor memory for supplying voltage. The method of claim 1, And the control circuit supplies the first voltage to a well in which the memory cell array is formed when reading data from a memory cell connected to the first bit line. The method of claim 1, And the control circuit includes a constant voltage generator circuit for generating the first voltage. The method of claim 3, And at least one first switch connected between said constant voltage generating circuit and a source line of said memory cell array. The method of claim 4, wherein And at least one second switch connected between said constant voltage generating circuit and said well of said memory cell array. The method of claim 1, And the control circuit supplies a predetermined voltage to the word line after supplying a first precharge voltage to a first bit line during the read operation, and reads a potential change of the bit line. The method of claim 1, The first precharge voltage supplied to the first bit line is a voltage higher than the first voltage. The method of claim 1, The charge of the first bit line moves to the second bit line through the memory cell and the source line. The method of claim 4, wherein And at least one third switch connected to the source line and turned on during an erase operation to supply an erase voltage to the source line and the well. The method of claim 9, And at least one fourth switch connected to the well and turned on during an erase operation to supply an erase voltage to the source line and the well. The method of claim 1, And said first voltage is a ground voltage. The method of claim 1, A first transistor having one end connected to the bit line; One end is connected to the other end of the first transistor, further comprising a capacitor to which the first signal is supplied to the other end, When the control circuit reads the potential of the first bit line, the control circuit supplies a third voltage to one end of the capacitor, and then sets the first signal from the low level to the high level, thereby raising the voltage of the one end of the capacitor. By boosting the voltage to a voltage higher than the third voltage and applying a predetermined voltage to the gate of the first transistor, the potential of the first bit line is read, the first transistor is turned off, and the first signal is turned off from the high level. A semiconductor memory device set at a low level. In a semiconductor memory device, A memory cell array in which a plurality of memory cells are arranged in a matrix shape, the memory cells being connected to word lines and bit lines; A control circuit for controlling potentials of the word line, bit line, source line, and well; Constant voltage generation circuit for generating a first voltage and a second voltage Including, The memory cell has n states of a first state and a second state to an nth state (n is a natural number of two or more), and the control circuit includes a first state and a second state to a kth state (k ≦ n , k is a natural number), the first voltage generated by the constant voltage generation circuit is supplied to a source line of the memory cell array, and the state of the (k + 1) to nth states And a second voltage are supplied to a source line of the memory cell array. The method of claim 13, When the control circuit reads out the states of the first state, the second state to the kth state (k ≦ n, k is a natural number), the control circuit generates the first voltage generated by the constant voltage generation circuit in the well of the memory cell array. And a second voltage is supplied to a well of the memory cell array when the first voltage is supplied and the state of the (k + 1) th to nth states is read. The method of claim 13, And the second voltage is lower than the first voltage. The method of claim 13, The control circuit supplies a first precharge voltage to selected bit lines among the bit lines when reading the states of the first state, the second state to the kth state (k ≦ n, k is a natural number). And reading a state of the (k + 1) th to the nth state, and supplying a second precharge voltage to the selected bit line. The method of claim 16, And a difference between the first precharge voltage and the first voltage and a difference between the second precharge voltage and the second voltage are the same. The method of claim 13, The control circuit, when performing data read operation from a memory cell connected to a first bit line among the bit lines, includes the first state, the second state to the kth state (k≤n, k is a natural number). When the state of is read, the first voltage generated by the constant voltage generation circuit is supplied to a second bit line disposed adjacent to the first bit line, and the (k + 1) to nth states are provided. And the second voltage supply the second voltage to the second bit line. The method of claim 13, And a data storage circuit for storing data written to the memory cell and data read from the memory cell. The method of claim 19, The data storage circuit is a semiconductor memory device connected to a pair of bit lines. The method of claim 19, The data storage circuit is a semiconductor memory device connected to one bit line. The method of claim 13, A first transistor having one end connected to the bit line; One end is connected to the other end of the first transistor, further comprising a capacitor to which the first signal is supplied to the other end, When the control circuit reads the potential of the first bit line, the control circuit supplies a third voltage to one end of the capacitor, and then sets the first signal from the low level to the high level, thereby raising the voltage of the one end of the capacitor. By boosting the voltage to a voltage higher than the third voltage and applying a predetermined voltage to the gate of the first transistor, the potential of the first bit line is read, the first transistor is turned off, and the first signal is turned off from the high level. A semiconductor memory device set at a low level.

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