JP4843362B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device capable of storing binary data or more in one memory cell, for example.

  For example, in a NAND flash memory, a plurality of memory cells arranged in the row direction are each connected to a corresponding latch circuit via a bit line. Each latch circuit holds data when data is written and read. Data is written into or read from a plurality of cells arranged in the row direction at once (see, for example, Patent Document 1).

  In the erase operation, the threshold voltage of the memory cell is set to a negative voltage, and the threshold voltage is set to a positive voltage by injecting electrons into the floating gate of the memory cell by the write operation. However, in the NAND flash memory, since memory cells are connected in series, it is necessary to turn on non-selected cells other than the selected cell when reading the data of the selected cell to the bit line during the read operation. . For this reason, a voltage (Vread) higher than the maximum threshold voltage set in the memory cell is applied to the control gate of the non-selected cell.

  On the other hand, in the write operation, the threshold voltage set in the memory cell cannot exceed Vread in consideration of the read operation. For this reason, in the write sequence, it is necessary to repeatedly perform program and program verify read for each bit, and control so that the threshold voltage of the memory cell does not exceed Vread.

  In order to store a large capacity, a multi-value memory that stores data of 2 bits or more in one memory cell has been developed. For example, in order to store 2 bits in one memory cell, four threshold distributions must be set. For this reason, the multilevel memory has a problem that the threshold distribution per cell needs to be set narrower than a memory that stores one bit in one cell, and the writing speed becomes slow.

  Therefore, it is considered that high-speed writing can be performed by setting a threshold voltage on the negative voltage side and widening the width of the threshold distribution per one. As a method of setting the threshold voltage on the negative voltage side, a bias voltage is applied to the source and well of the cell at the time of reading and verify reading, and these potentials are made higher than the potential of the word line. It has been proposed to read a negative threshold voltage by making it equivalent to the case where a negative voltage is applied to. In this proposal, for example, the source and well and the non-selected bit line are short-circuited so that a large current does not flow into a power supply circuit that generates a bias voltage from a large number of bit lines from 16 k to 32 k. In the read operation, first, a potential is applied to the selected bit line of the two bit lines. At this time, the charge + Q is stored in the selected bit line, but the charge -Q is also stored in the non-selected bit line. Here, when the cell is turned on, the charge stored in the selected bit line flows into the source, but since the source and well and the non-selected bit line are short-circuited, the charge of the selected bit line is And neutralizes with the charge -Q stored in the non-selected bit line and disappears. For this reason, source noise can be suppressed and high-speed reading can be performed. In addition, since the current flowing into the power supply circuit that supplies the bias voltage to the source and well and the non-selected bit line is small, the power supply circuit operates stably and the threshold voltage on the negative voltage side can be read reliably.

However, in this case, since it is necessary to flow the charge −Q stored in the non-selected bit line to the source line, only half of the plurality of cells arranged in the row direction can be read simultaneously. When only half of the plurality of cells arranged in the row direction can be selected, half of the cells are written. For this reason, non-selected cells receive program disturb. In order to increase the writing speed, it is desirable to simultaneously write all the plurality of cells arranged in the row direction. By connecting the data storage circuits to all the bit lines, all the cells arranged in the row direction can be written simultaneously.

However, as described above, since it is necessary to eliminate the charge of the other bit line using one adjacent bit line as described above, only half of the cells arranged in the row direction are read. Cannot be performed, and all cells cannot be read simultaneously. This data reading is not limited to normal reading, but is the same in verify reading for verifying write data. In particular, in the case of a multi-level memory that stores 4-level, 8-level, and 16-level data, the number of times of verify read increases because the write data is verified. For this reason, the time required for the write verification is longer than the write time. As described above, when a bias voltage is applied to the source line at the time of reading data, there is a problem that all the cells in the row direction cannot be read simultaneously at a stable and high speed while suppressing noise.
JP 2004-192789 A

  An object of the present invention is to provide a semiconductor memory device capable of simultaneously reading all cells in the row direction stably and at high speed.

According to an aspect of the semiconductor memory device of the present invention, a memory cell array in which a plurality of word lines, a plurality of bit lines, a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines are arranged, A plurality of source lines arranged along each of the plurality of bit lines and connected to the respective sources of the plurality of memory cells, wherein the plurality of bit lines are odd-numbered bit lines. A second bit line that is an even-numbered bit line, the plurality of source lines include first and second source lines, and the first source line is connected to the first bit line. And the second source line is arranged along the second bit line, and the first source line, the first bit line, the second source line, and the second bit are arranged along the second bit line. Lines are formed in different layers And wherein the Rukoto.

  According to the present invention, it is possible to provide a semiconductor memory device capable of simultaneously reading all cells in the row direction stably and at high speed.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 2 shows a configuration of the semiconductor memory device according to the first embodiment, specifically, a NAND flash memory that stores, for example, 4-level (2-bit) data.

The memory cell array 1 includes a plurality of bit lines, a plurality of word lines, and a common source line, and memory cells that are electrically rewritable, such as EEPROM cells, are arranged in a matrix. A bit line control circuit 2 and a word line control circuit 6 for controlling bit lines are connected to the memory cell array 1.

  The bit line control circuit 2 reads the data of the memory cells in the memory cell array 1 via the bit lines, detects the state of the memory cells in the memory cell array 1 via the bit lines, and stores the memory via the bit lines. A write control voltage is applied to the memory cells in the cell array 1 to write to the memory cells. A column decoder 3 and a data input / output buffer 4 are connected to the bit line control circuit 2. The data storage circuit in the bit line control circuit 2 is selected by the column decoder 3. Data of the memory cell read to the data storage circuit is output to the outside from the data input / output terminal 5 via the data input / output buffer 4.

  Further, the data input / output terminal 5 receives, for example, various commands CMD, an address ADD, and write data DT supplied from an external host. The write data DT input to the data input / output terminal 5 is input to the data storage circuit selected by the column decoder 3 via the data input / output buffer 4.

  The word line control circuit 6 is connected to the memory cell array 1. The word line control circuit 6 selects a word line in the memory cell array 1 and applies a voltage necessary for reading, writing or erasing to the selected word line.

  The memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input / output buffer 4, and the word line control circuit 6 are connected to a control signal and control voltage generation circuit 7, and the control signal and control voltage generation circuit 7 Be controlled. The control signal and control voltage generation circuit 7 is connected to a control signal input terminal 8 and is supplied with control signals ALE (address latch enable) and CLE (command latch enable) input from the outside via the control signal input terminal 8. ), WE (write enable), and RE (read enable). The control signal and control voltage generation circuit 7 generates a control signal and a control voltage necessary for writing, reading and erasing data according to these control signals. Further, the control signal and control voltage generation circuit 7 includes a constant voltage generation circuit 7-1 that generates a constant voltage Vfix (for example, 1.6 V). When the negative threshold voltage is read, the constant voltage generation circuit 7-1 supplies a constant voltage Vfix to the cell well, the main source line, the sub-source line, and the selection gate of the non-selected block described later. That is, by applying a constant bias voltage to the well, source line, etc. to make it higher than the potential of the word line, the negative threshold voltage set in the memory cell is set to a state in which a negative voltage is apparently applied to the word line. Readable.

  The bit line control circuit 2, column decoder 3, word line control circuit 6, control signal and control voltage generation circuit 7 constitute a write circuit and a read circuit.

FIG. 1 shows the configuration of the memory cell array 1 and the bit line control circuit 2 shown in FIG. A plurality of NAND cells are arranged in the memory cell array 1. One NAND cell includes a memory cell MC made up of, for example, 32 EEPROMs connected in series, and select gates S1 and S2. Selection gate S2 is connected to the bit line BL0e, selection gate S1 is connected to the sub source line SRC0 e.

In the first embodiment, sub-source lines SRC0e, SRC0o, SRC1e, SRC1o ... SRCie, SRCio ... SRC8ke, SRC8ko are arranged along each bit line BL0e, BL0o, BL1e, BL1o ... BLie, BLio ... BL8ke, BL8ko. ing. One end of each sub-source line is connected to the main source line SRC arranged along the word line, and the other end is connected to the source of each NAND cell via the selection gate S1. These sub-source lines SRC0e, SRC0o, SRC1e, SRC1o... SRCie, SRCio... SRC8ke, SRC8ko have a function of neutralizing and extinguishing charges on the corresponding bit lines when reading data. The even-numbered bit lines BL0e to BL8ke and the even-numbered sub-source lines SRC0e to SRC8ke, the odd-numbered bit lines BL0o to BL8ko, and the odd-numbered sub-source lines SRC0 o to SRC8k o have sub-source lines and bit lines, They are formed alternately.

  The control gates of the memory cells MC arranged in each row are commonly connected to the word lines WL0 to WL29, WL30, WL31. The selection gate S2 is commonly connected to the select line SGD, and the selection gate S1 is commonly connected to the select line SGS.

  The bit line control circuit 2 has the same number of data storage circuits 10 as the number of bit lines. Each data storage circuit 10 is connected to bit lines BL0e, BL0o, BL1e, BL1o... BLie, BLio... BL8ke, BL8ko, respectively. In FIG. 1, all the data storage circuits are arranged on one end side of the bit line. However, when the layout is difficult, for example, the data storage circuit connected to the even-numbered bit line BLe is arranged on one end side of the bit line, and the data storage circuit connected to the odd-numbered bit line BLo is connected to the other end of the bit line. It is also possible to arrange on the side.

  The memory cell array 1 includes a plurality of blocks as indicated by broken lines. Each block includes a plurality of NAND cells, and data is erased in units of blocks, for example. The erase operation is simultaneously performed on the bit lines connected to the data storage circuit 10.

  Further, a plurality of memory cells connected to one word line (memory cells in a range surrounded by a broken line) constitute one sector. Data is written and read for each sector. In the case of this embodiment, data is written to and read from all memory cells connected to one word line.

  During the read operation, program verify operation, and program operation, the bit lines BL0e, BL0o, BL1e, BL1o... BLie, BLio. , YAi + 1... YA8k, YA8k + 1 are selected. Furthermore, one word line is selected according to the external address.

  FIGS. 3A, 3B, and 4 show cross-sectional views of the memory cell and the select transistor.

  3A and 3B are cross-sectional views of the memory cell and the select transistor. FIG. 3A shows a memory cell. In the substrate 51 (P-type well region 55 described later), an n-type diffusion layer 42 is formed as the source and drain of the memory cell. A floating gate (FG) 44 is formed on the P-type well region 55 via a gate insulating film 43, and a control gate (CG) 46 is formed on the floating gate 44 via an insulating film 45. Yes. FIG. 3B shows a selection gate. In the P-type well region 55, an n-type diffusion layer 47 as a source and a drain is formed. A control gate 49 is formed on the P-type well region 55 via a gate insulating film 48.

  FIG. 4 is a cross-sectional view of the semiconductor memory device corresponding to the first embodiment. For example, N-type well regions 52, 53, 54 and P-type well regions 55, 56 are formed in the P-type semiconductor substrate 51. A P-type well region 55 is formed in the N-type well region 52, and a low-voltage N-channel transistor LVNTr constituting the memory cell array 1 is formed in the P-type well region 55. Further, a low-voltage P-channel transistor LVPTr and a low-voltage N-channel transistor LVNTr constituting the data storage circuit 10 are formed in the N-type well region 53 and the P-type well region 56. In the substrate 51, a high-voltage N-channel transistor HVNTr that connects the bit line and the data storage circuit 10 is formed. In the N-type well region 54, for example, a high voltage P-channel transistor HVPTr constituting a word line driving circuit or the like is formed. As shown in FIG. 4, the high voltage transistors HVNTr and HVPTr have, for example, a thicker gate insulating film than the low voltage transistors LVNTr and LVPTr. The peripheral circuits 2 to 8 in FIG. 2 are also composed of LVNTr, LVPTr, HVNTr, and HVPTr.

  FIG. 5 shows voltages supplied to the respective units shown in FIG. 4 in erasing, programming, and reading. At the time of data reading, a constant voltage Vfix is supplied to the N well 52 and the P well 55 in which memory cells are formed. If no threshold level is provided on the negative side other than the erase level, Vfix = 0V.

  FIG. 6 is a circuit diagram showing an example of the data storage circuit 10 shown in FIG.

  The data storage circuit 10 includes a primary data cache (PDC), a secondary data cache (SDC), a dynamic data cache (DDC), and a temporary data cache (TDC). The SDC, PDC, and DDC hold input data at the time of writing, hold read data at the time of reading, temporarily hold data at the time of verification, and are used for internal data operations when storing multi-value data. The TDC amplifies and temporarily holds bit line data when reading data, and is used to manipulate internal data when storing multilevel data.

  The SDC includes clocked inverter circuits 61a and 61b and transistors 61c and 61d that constitute a latch circuit. The transistor 61c is connected between the input terminal of the clocked inverter circuit 61a and the input terminal of the clocked inverter circuit 61b. A signal EQ2 is supplied to the gate of the transistor 61c. The transistor 61d is connected between the output terminal of the clocked inverter circuit 61b and the ground. A signal PRST is supplied to the gate of the transistor 61d. The node N2a of the SDC is connected to the input / output data line IO via the column selection transistor 61e, and the node N2b is connected to the input / output data line IOn via the column selection transistor 61f. A column selection signal CSLi is supplied to the gates of the transistors 61e and 61f. The node N2a of the SDC is connected to the node N1a of the PDC via the transistors 61g and 61h. A signal BLC2 is supplied to the gate of the transistor 61g, and a signal BLC1 is supplied to the gate of the transistor 61h.

  The PDC includes clocked inverter circuits 61i and 61j and a transistor 61k. The transistor 61k is connected between the input terminal of the clocked inverter circuit 61i and the input terminal of the clocked inverter circuit 61j. A signal EQ1 is supplied to the gate of the transistor 61k. The node N1b of the PDC is connected to the gate of the transistor 61l. One end of the current path of the transistor 61l is grounded through the transistor 61m. A signal CHK1 is supplied to the gate of the transistor 61m. The other end of the current path of the transistor 61l is connected to one end of the current path of the transistors 61n and 61o constituting the transfer gate. A signal CHK2n is supplied to the gate of the transistor 61n. The gate of the transistor 61o is connected to the node N2a. The other ends of the current paths of the transistors 61n and 61o are connected to the signal line COMi. This signal line COMi is commonly connected to all the data storage circuits 10, and it can be determined whether or not the verification of all the data storage circuits 10 has been completed based on the level of this signal line COMi. That is, as will be described later, when the verification is completed, the node N1b of the PDC becomes low level. In this state, when the signals CHK1 and CHK2n are set to the high level, the signal line COMi is set to the high level when the verification is completed.

  Further, the TDC is constituted by, for example, a MOS capacitor 61p. One end of the capacitor 61p is connected to the connection node N3 of the transistors 61g and 61h, and a signal BOOST described later is supplied to the other end. A DDC is connected to the connection node N3 via a transistor 61q. A signal REG is supplied to the gate of the transistor 61q.

  The DDC is composed of transistors 61r and 61s. The signal VREG is supplied to one end of the current path of the transistor 61r, and the other end is connected to the current path of the transistor 61q. The gate of the transistor 61r is connected to the node N1a of the PDC through the transistor 61s. A signal DTG is supplied to the gate of the transistor 61s.

  Further, one end of a current path of the transistors 61t and 61u is connected to the connection node N3. The signal VPRE is supplied to the other end of the current path of the transistor 61u, and BLPRE is supplied to the gate. A signal BLCLAMP is supplied to the gate of the transistor 61t. The other end of the current path of the transistor 61t is connected to one end of the bit line BLe or BLo via the transistor 61v.

  The above signals and voltages are generated by the control signal and control voltage generation circuit 7 shown in FIG. 2, and the following operations are controlled based on the control of the control signal and control voltage generation circuit 7.

  This memory is a multi-level memory and can store, for example, 2-bit data in one cell. The 2-bit switching is performed by an address (first page, second page).

  FIGS. 7A, 7B, and 7C show the relationship between the memory cell data and the threshold voltage of the memory cell. When the erase operation is performed, the data in the memory cell becomes “0” as shown in FIGS. After writing the first page, the data in the memory cell becomes data “0” or data “1”. Here, data “0” has a negative threshold voltage, and data “1” has a positive threshold voltage.

  Further, as shown in FIG. 7B, after the second page is written, the data in the memory cell becomes data “0”, “2”, “3”, “4”. In the first embodiment, the memory cell data is defined from the lower threshold voltage to the higher threshold voltage.

  FIG. 8 shows an example of the write order in the first embodiment. In the block, a write operation is performed for each page from a memory cell close to the source line. Memory cell 1 and memory cell 2 are written simultaneously, memory cell 3 and memory cell 4 are written simultaneously, memory cell 5 and memory cell 6 are written simultaneously, and memory cell 7 and memory cell 8 are written simultaneously. The writing order is as follows.

(1) First page of memory cells 1 and 2 (2) First page of memory cells 3 and 4 (3) Second page of memory cells 1 and 2 (4) First page of memory cells 4 and 5 (5) ) Second page of memory cells 3 and 4 (6) First page of memory cells 7 and 8 (7) Second page of memory cells 5 and 6 (8) Other memory cells not shown (9) Memory cell 7 , 8 second page (read operation)
As shown in FIG. 7A, after the first page write, the data in the memory cell is “0” or “ 1 ”. Therefore, the data can be read by performing the read operation by setting the potential difference between the word line and the source line to the potential “a” intermediate between the threshold voltages of these data. Further, as shown in FIG. 7B, after the second page write, the memory cell data is in any one of “0”, “2”, “3”, and “4”. Therefore, the data can be read by setting the potential difference between the word line and the source line to “b”, “c”, “d”.

  The read operation will be described with reference to FIG. In the read operation, the voltage Vfix (eg, 1.6 V) is supplied from the constant voltage generation circuit 7-1 to the well of the selected cell, the main source line SRC, the sub source line SRC0e... SRC8ko, and the selection gate of the non-selected block. Supplied. In the case where the threshold distribution is not set on the negative voltage side, Vfix is set to 0V.

  Further, the potential Vfix + “a” or “b”, “c”, “d” at the time of reading is supplied to the selected word line. For example, if “a” = − 0.5V, Vfix + “a” is 1.1V. At the same time, Vread + Vfix is applied to the non-selected word line of the selected block, Vsg + Vfix is applied to the select line SGD of the selected block (Vsg = Vdd + Vth, Vdd is, for example, 2.5 V, Vth is the threshold voltage of the N-channel MOS transistor), and Vfix is applied to the select line SGS. Supply.

  Further, the signal VPRE of the data storage circuit 10 shown in FIG. 6 is set to Vdd, the signal BLPRE is set to Vsg, the signal BLCLAMP is set to 0.6V + Vth + Vfix, for example, and the bit line is set to 0.6V + Vfix = 2.2V, for example. Precharge.

  Next, the select line SGS on the source side of the cell is set to Vsg + Vfix. Since the well and main source lines SRC, sub-source lines SRC0e... SRC8ko are at the voltage Vfix, the threshold voltage of the cell is “a” = − 0.5 V, or higher than “b”, “c”, “d”. At this time, since the cell is in an off state, the potential of the bit line remains at a high level, for example, 2.2V. When the threshold voltage of the cell is lower than “a”, “b”, “c”, or “d”, the cell is turned on, so that the charge of the bit line is discharged, and the main source line, sub-source line, The same potential, that is, Vfix (for example, 1.6 V). Here, as shown in FIG. 1, there are 16k bit lines, for example, and when the charge Q discharged from each bit line flows into the constant voltage generation circuit 7-1, the constant voltage generation circuit 7-1 It becomes unstable.

  However, as shown in FIG. 10, for example, the charge + Q precharged to the bit line BL0e flows to the sub-source line SRC0e, and is neutralized with the charge −Q of the sub-source line SRC0e and disappears. For this reason, it is possible to prevent a large current from flowing into the constant voltage generation circuit 7-1.

  After that, the signal BLPRE of the data storage circuit 10 shown in FIG. 6 is once set to the voltage Vsg, and the node N3 of the TDC is precharged to Vdd. Then, the signal BOOST is changed from the low level to the high level. The potential is set to αVdd (for example, α = 1.7, αVdd = for example, 4.25V).

  Next, the signal BLCLAMP is set to, for example, voltage (0.45V + Vth) + Vfix. The node N3 of the TDC is at a low level when the potential of the bit line is lower than 0.45V + Vfix (Vfix = for example, 1.6V), and remains at a high level when the potential of the bit line is higher than 0.45V (αVdd = for example, 4.25V).

  Next, after setting the signal BLCLAMP to a voltage Vtr (for example, 0.1 V + Vth), the signal BOOST is changed from a high level to a low level. Here, when the node N3 of the TDC is at a high level, it drops from Vfix (for example, 1.6V), but since the signal BLCLAMP is at the voltage Vtr (for example, 0.1V + Vth), it does not drop below 0.1V. The node N3 of the TDC becomes Vdd from the high level (αVdd = eg 4.25V).

  Here, the signal BLC1 is set to Vsg, and the potential of the TDC is read into the PDC. Therefore, when the threshold voltage of the cell is lower than the levels of “a” or “b”, “c”, and “d”, the PDC is at a low level, and when it is higher, the PDC is at a high level and reading is performed. In this way, a negative threshold voltage can be read without setting the word line to a negative voltage.

(Program and program verify)
(program)
A flowchart of the program operation is shown in FIG.

  In the program operation, first, an address is designated, and two pages shown in FIG. 1 are selected. The memory can be programmed only in the order of the first page and the second page of the two pages. Therefore, the first page is first selected by address.

  Next, write data is input from the outside and stored in SDCs (shown in FIG. 6) in all data storage circuits 10 (S11). When a write command is input, the SDC data in all the data storage circuits 10 are transferred to the PDC (S12). When data "1" (not written) is input from the outside, the node N1a of the PDC of the data storage circuit 10 becomes high level, and when data "0" (write is performed) is input, it becomes low level. . Thereafter, the data of the PDC is the potential of the node N1a, and the data of the SDC is the potential of the node N2a.

(Program operation) (S13)
When signal BLC1 shown in FIG. 6 is set to Vdd + Vth and data “1” (not written) is stored in PDC, the bit line becomes Vdd, and data “0” (write is performed). The bit line becomes Vss. Here, Vdd and select line SG S of a selected block, Vpgm (20V) to the selected word line and the unselected word lines to apply a Vpass (10V), when the bit line is at Vss, the cell Since the channel is Vss and the word line is Vpgm, writing is performed. On the other hand, when the bit line is at Vdd, the cell channel is not Vss, but by raising Vpgm or Vpass, the potential rises due to coupling, so that programming is not performed. By writing the first page, the data of the memory cell, as shown in FIG. 7 (a), becomes the data "0" and data "1".

(Program verify read) (S14)
The memory cell is program-verified by the level “a” in the first page. The program verify operation is almost the same as the read operation.

  First, the voltage Vfix (for example, 1.6 V) is supplied from the constant voltage generation circuit 7-1 to the well of the selected cell, the main source line SRC, the sub source lines SRC0e to SRC8ko, and the select line of the unselected block. . A potential Vfix + a ′ slightly higher than the potential Vfix + a at the time of reading is supplied to the selected word line. For example, if “a ′” = − 0.4V, Vfix + a ′ is 1.2V. Hereinafter, “′” indicates a verify potential, which is slightly higher than the read potential.

  By applying the potential Vfix + a ′ at the time of verify read to the selected word line, a negative potential is apparently applied to the gate of the cell. At the same time, Vread + Vfix is supplied to the unselected word line of the selected block, Vsg + Vfix is supplied to the select line SGD of the selected block, and Vfix is supplied to the select line SGS. Vfix is supplied to the main source line SRC and the sub source lines SRC0e to SRC8ko, and Vfix is also supplied to the wells of the cells. Next, the signal VPRE of the data storage circuit 10 shown in FIG. 6 is set to Vdd (for example, 2.5V), the signal BLPRE is set to Vsg, the signal BLCLAMP is set to, for example, (0.6V + Vth) + Vfix, and the bit line is set to, for example, 0.6V + Vfix = Precharge to 2.2V. Next, the select line SGS on the source side of the cell is set to Vsg + Vfix. Since the well and main source line SRC and sub-source lines SRC0e to SRC8ko are at Vfix, the cell is turned off when the threshold voltage is higher than a '(for example, a' =-0.4V). For this reason, the bit line remains at a high level (eg, 2.2 V). When the threshold voltage of the cell is lower than a ', the cell is turned on. For this reason, the bit line is discharged and becomes the same potential as the main source line SRC and the sub source lines SRC0e to SRC8ko, that is, Vfix (for example, 1.6V). During this bit line discharge time, after setting TDC to Vss with signal VPRE = Vss and signal BLPRE = Vsg, TDC is set to high level when signal VREG = Vdd and signal REG = Vdd and DDC is at high level. To do. Thereafter, the signal DTG is set to Vsg, and the data of the PDC is copied to the DDC. Next, the potential of the TDC is transferred to the PDC with the signal BLC1 = Vsg. Through these operations, DDC data and PDC data are exchanged.

  Thereafter, the signal BLPRE of the data storage circuit 10 shown in FIG. 6 is once set to Vsg = (Vdd + Vth), and the node N3 of the TDC is precharged to Vdd. Next, the signal BOOST is set from the low level to the high level, and TDC = αVdd (for example, α = 1.7, αVdd = 4.25V) is set. Here, the signal BLCLAMP is set to, for example, (0.45 V + Vth) + Vfix. The node N3 of the TDC is at a low level (Vfix (eg, 1.6V)) when the bit line is lower than 0.45V + Vfix, and is at a high level (αVdd (eg, 4.25V)) when the bit line is higher than 0.45V. Will remain. Thereafter, the signal BLCLAMP is set to Vtr (for example, 0.1 V + Vth), and then the signal BOOST is set from the high level to the low level. Here, the node N3 of the TDC falls from Vfix (eg, 1.6V) when it is at a low level, but does not fall below 0.1V because the signal BLCLAMP is set to Vtr (eg, 0.1V + Vth). Further, the node N3 of the TDC becomes Vdd from the high level (αVdd (eg, 4.25V)). Here, the signal BLC1 is set to Vsg, and the potential of the TDC is read into the PDC. Next, the signal VREG = Vdd and the signal REG = Vsg are set, and when the DDC is at a high level (non-write), the TDC is forcibly set to a high level. However, when DDC is at a low level (non-write), the value of TDC does not change. Therefore, when PDC = low level (write) originally and the threshold voltage of the cell is lower than the level “a ′”, the PDC becomes low level (write) again, and when it is higher, the PDC becomes high level. Not written in the program. When PDC = high level (non-write) originally, PDC = high level, and non-write occurs in the next program loop. Such an operation is repeated until the PDCs of all the data storage circuits 10 become high level (“1”) (S15 to S13).

  On the other hand, FIG. 12 shows the second page write operation. In writing the second page, first, data to be written is input from the outside and stored in the SDCs of all the data storage circuits 10 (S21).

(Internal data read) (S22)
First, an internal read operation is performed to determine whether the data in the memory cell of the first page is “0” or “2” before writing to the cell. This internal read operation is the same as the negative level read described above, and the read operation is performed by supplying the level “a” to the word line.

(Data cache setting) (S23)
Thereafter, the data stored in each data cache is manipulated. That is, SDC data is transferred to the PDC, and PDC data is transferred to the DDC. Next, the DDC data is inverted and transferred to the SDC. Thereafter, the PDC data is transferred to the DDC. Next, the data of the DDC is inverted and transferred to the PDC. Thereafter, the PDC data is transferred to the DDC. By performing such an operation, when the data in the memory cell is set to “0” (data “1” on the first page, data “1” on the second page), the PDC, DDC, and SDC are all set to the high level. Is set.

  When the data in the memory cell is set to “1” (data “1” on the first page and data “0” on the second page), the PDC is set to the low level, the DDC is set to the low level, and the SDC is set to the high level.

  When the data in the memory cell is set to “2” (data “0” in the first page and data “0” in the second page), the PDC is set to the low level, the DDC is set to the high level, and the SDC is set to the low level.

  When the data in the memory cell is set to “3” (data “0” in the first page and data “1” in the second page), the PDC, DDC, and SDC are all set to a low level.

  Thus, in the state where each data cache is set, the program for the second page is executed in the same manner as the first page (S24).

  Thereafter, the program verify is executed in the same manner as the level “a ′” using the levels “b ′”, “c ′”, and “d ′” (S25-S28, S24).

  If the above operation is performed in the program verify of the level “b ′”, the write cells to the levels “c” and “d” are not written in the program verify of the level “b ′”. Therefore, for example, in the case of writing of levels “c ′” and “d ′”, the node N2a of the SDC is set to a low level. In the case of writing at level “b ′”, the node N2a of the SDC is at a high level, so that the signal VPRE = Vdd and the signal BLPRE = Vsg are normally set to forcibly set the TDC to a high level. However, in this case, the signal BLPRE remains at Vss, the signal BLC2 = Vsg, the level “c ′” and “d ′” are written, the TDC is set to the low level, and the level “b ′” is written only. TDC is set to high level. As a result, in the case of writing at levels “c ′” and “d ′”, the writing is not completed in the program verify.

  In the program verify of level “c ′” in the second page write, if the above operation is performed, the write cell to level “d” is completely written in the program verify of level “c ′”. End up. For this reason, after setting the signal BOOST from the high level to the low level, the signal VREG = Vdd and the signal REG = Vsg are set, and when the DDC is at the high level, the signal is set before the operation for forcibly setting the TDC to the high level. BLC1 = Vtr (= 0.1V + Vth) is set. Here, during the discharge of the bit line, the DDC data and the PDC data are exchanged. Therefore, the node N1a of the PDC is at a high level when writing at level “c”, and at a low level when writing at other levels. Therefore, the TDC is forcibly set to a low level in cases other than writing of level “c”. As a result, in the case of writing “d ′”, the writing is not completed in the program verify.

  When the PDC is at the low level, the write operation is performed again, and this program operation and the verify operation are repeated until the data in the PDC of all the data storage circuits 10 becomes the high level (S25-S28, S24).

(Erase operation)
The erase operation is executed in units of blocks indicated by broken lines in FIG. After erasing, the threshold voltage distribution of the cell becomes data “0” as shown in FIG.

  FIG. 13 shows an EASB (Erased Area Self Boost) write method for self-boosting the erase area. In the case of the EASB writing method, it is necessary to make the threshold voltage distribution of the erase cell shallow. Writing is performed from the source side of the NAND cell. When writing data to the cell, the bit line is set to Vss, and when not writing, the bit line is set to Vdd. Next, for example, when data is written to the selected cell by WL7, WL0 to WL4 are set to Vpass, WL5 is set to Vss, WL6 is set to Vdd, WL7 is set to the program voltage Vpgm, and WL8 to WL31 are set to Vpass. In this state, when data is written, writing is performed because the gate of the word line WL7 is Vpgm and the channel is Vss. In the case of non-write, the channel is boosted to, for example, Vpass / 2. However, if the number of cells to be written is large, the channel is less likely to be boosted. However, the EASB writing method always writes from the source line side. Therefore, when boosting is performed with the word line WL5 = 0, the cells connected to the word lines WL8 to WL31 are erased, so that the channel is boosted and cannot be written. Thus, it is necessary to prevent the boosted charge from moving to the already written cell. However, if the cell selected by the word line WL5 is in the erased state and the threshold voltage is deep, that is, if the cell has a large negative threshold voltage, the cell will not turn off. Therefore, it is necessary to make the threshold voltage of the erase cell shallow, that is, to set a small negative threshold voltage.

  For this reason, after the erase operation, all word lines in the block are selected, program and program verify read are performed, and the write operation is performed up to the “z” level as shown in FIG. 7C. The program and program verify read operations at this time are performed in the same manner as the normal program and program verify read except that all word lines are selected and the potential of the selected word line at the time of verify is z + Vfix (for example, 0V). .

  According to the first embodiment, the sub-source lines SRC0e to SRC8ko connected to the main source line SRC are arranged along the bit lines BL0e to BL8ko, respectively, and the data is read via the selection gate S1. Each sub-source line SRC0e to SRC8ko is connected to the source of each NAND cell. For this reason, when the cell is turned on, the charge precharged on each bit line can be neutralized with the charges on each sub-source line and main source line and disappear. Therefore, data can be read simultaneously from all the cells connected to the word line.

  Further, at the time of data writing, the verify read can be simultaneously performed on all the memory cells connected to the word line. For this reason, it is possible to increase the writing speed.

  Further, when a negative threshold voltage is set for the memory cell, when a bias voltage is supplied to the source of the memory cell by the constant voltage generation circuit 7-1, the charge of each bit line is changed to each sub-source line, and Since the charge of the main source line is neutralized and eliminated, the current flowing into the constant voltage generation circuit 7-1 can be suppressed. Therefore, the constant voltage generation circuit 7-1 can be operated stably, and noise generation can be suppressed.

(Second Embodiment)
In the first embodiment, sub-source lines SRC0e to SRC8ko are arranged along the bit lines BL0e to BL8ko, respectively. When the sub-source line is arranged adjacent to each bit line, the space between the bit line and the sub-source line becomes narrow, which makes manufacturing difficult. Therefore, in the second embodiment, adjacent bit lines and adjacent sub-source lines are arranged in different layers.

  FIGS. 14A and 14B show the second embodiment and schematically show the arrangement of bit lines and source lines. 14A and 14B, a diffusion layer, a floating gate, an interlayer insulating film, and the like constituting the memory cell are omitted.

  14A and 14B, a floating gate FG, word lines (control gates CG) WL0 to WL31, and select lines SGD and SGS are formed above the active region AA where the diffusion layer is formed. Above these, an odd-numbered bit line BLo among the plurality of bit lines and an odd-numbered sub-source line SRCo among the plurality of sub-source lines are arranged. These odd-numbered bit lines BLo and sub-source lines SRCo are formed by the first layer metal wiring M1. Above the odd-numbered bit lines BLo and the sub-source lines SRCo, even-numbered bit lines BLe and sub-source lines SRCe are formed by the second-layer metal wiring M2. Above the even-numbered bit lines BLe and the sub-source lines SRCe, wirings for supplying potentials to the select lines SGS, SGD and the well Well are arranged by the third layer metal wiring M3.

  The sources of the selection gates S1 of the NAND cells are connected to each other at the connection portion CP in the active area AA to form a main source line SRC. For example, contacts CB are formed every other connecting portion CP, and the odd-numbered sub-source lines SRCo formed above are connected to the source diffusion layers via the contacts CB. Further, a via V1 is formed on the odd-numbered sub-source line SRCo, and the odd-numbered sub-source line SRCo and the even-numbered sub-source line SRCe are connected via the via V1. 14A and 14B, even-numbered bit lines BLe are formed above odd-numbered sub-source lines SRCo, and even-numbered sub-source lines SRCe are formed above odd-numbered bit lines BLo. Has been. Thus, the odd-numbered bit lines BLo and even-numbered bit lines BLe, and the odd-numbered sub-source lines SRCo and even-numbered sub-source lines SRCe are displaced from each other. Therefore, the odd-numbered bit lines BLo and the even-numbered bit lines BLe, the odd-numbered sub-source lines SRCo, and the even-numbered sub-source lines SRCe are inclined patterns corresponding to the positions of the contacts CB and V1. Contains OP.

  According to the second embodiment, odd-numbered bit lines BLo and sub-source lines SRCo, and even-numbered bit lines BLe and sub-source lines SRCe are arranged in different wiring layers. For this reason, in the configuration in which the data storage circuit 10 is connected to all the bit lines, the bit lines and the sub-source lines can be formed with sufficient intervals.

(Third embodiment)
In the second embodiment, adjacent active areas AA are connected by the connecting portion CP. On the other hand, in the third embodiment, the active region AA is connected without forming the connection portion CP.

  15 (a), 15 (b), and FIG. 16, the same parts as those in FIGS. 14 (a) and 14 (b) are denoted by the same reference numerals, and only different parts will be described. 15A, 15B, and 16, the source of the select gate S1 of each NAND cell is connected to the adjacent active region AA by a conductive film CF formed of, for example, polysilicon. The contact CB is formed on substantially the center of the conductive film CF. An odd-numbered sub-source line SRCo is connected to this contact CB.

  According to the third embodiment, the source diffusion layers of adjacent select gates S1 are connected by the conductive film CF. For this reason, the manufacturing can be facilitated when it is difficult to connect the diffusion layers as the active regions AA as in the second embodiment.

(Fourth embodiment)
17 (a) and 17 (b) show the fourth embodiment, and the same reference numerals are given to the same portions as those in FIGS. 15 (a), 15 (b) and FIG.

  In the second and third embodiments, the odd-numbered bit lines BLo and the even-numbered bit lines BLe, the odd-numbered sub-source lines SRCo, and the even-numbered sub-source lines SRCe include an oblique pattern OP. . On the other hand, in the fourth embodiment, the odd-numbered bit lines BLo and the even-numbered bit lines BLe, the odd-numbered sub-source lines SRCo, and the even-numbered sub-source lines SRCe are formed by only a linear pattern. ing.

  That is, as shown in FIGS. 17A and 17B, the source of the select gate S1 of each NAND cell is connected to the adjacent active region AA by the first conductive film CF1 formed of, for example, polysilicon. Yes. On the first conductive film CF1, a contact CB is formed corresponding to one active region AA connected by the first conductive film CF1. An odd-numbered sub-source line SRCo is connected to this contact CB. Therefore, the odd-numbered sub-source line SRCo is formed only by a linear pattern, and the odd-numbered bit line BLo is also formed only by a linear pattern.

  Furthermore, a via V1 is formed on the odd-numbered sub-source line SRCo, and a second conductive film CF2 is formed on the via V1 by a second metal wiring layer. In the second and third embodiments, the second metal wiring layer M2 constitutes even-numbered bit lines and sub-source lines. In the fourth embodiment, the second metal wiring layer M2 , Select lines SGD, SGS, Well are formed. A via V2 is formed on the second conductive film CF2 at a position corresponding to the even-numbered sub-source line SRCe, and the odd-numbered sub-source line SRCo is formed via the via V2, the second conductive film CF2, and the via V1. Are connected to the even-numbered sub-source line SRCe. That is, the even-numbered sub-source line SRCe and the even-numbered bit line BLe are configured by the third metal wiring layer M3.

According to the fourth embodiment, the active region AA, the odd-numbered sub-source line SRCo, and the even-numbered sub-source are formed using the first and second conductive films CF1, CF2, contacts CB, vias V1, V2. Line SRCe is connected. Therefore, the odd-numbered sub-source lines SRCo and the odd-numbered bit lines BLo, and the even-numbered sub-source lines SRCe and the even-numbered bit lines BLe can be formed with a pattern of only a straight line. It is possible to easily form a fine pattern without using a technique.

The conductive film CF, the first conductive film CF1, and the second conductive film CF2 are partially formed corresponding to the adjacent active layer AA. However, the present invention is not limited to this. For example, FIG. It is also possible to form them integrally as indicated by broken lines 16 and 17 .

  14 and 15, select lines SGD, SGS, and Well are formed in the third metal wiring layer M3. In FIG. 17, select lines SGD, SGS, and Well are formed in the second metal wiring layer M2. is doing. However, as indicated by broken lines in the third metal wiring layer M3 in FIGS. 14 and 15 and the second metal wiring layer M2 in FIG. 17, the source line SRC is formed in addition to the select lines SGD, SGS, and Well, It is also possible to connect the source line SRC and the sub-source lines SRCe and SRCo by vias (not shown).

  Further, the first to fourth embodiments have been described by taking the semiconductor memory device storing four values as an example. However, the present invention is not limited to this, and the present invention can be applied to a semiconductor memory device that stores 8-value, 16-value, and n-value (n is a natural number).

  Of course, various modifications can be made without departing from the scope of the present invention.

The circuit diagram which shows 1st Embodiment and shows a memory cell array. 1 is a schematic configuration diagram of a semiconductor memory device according to a first embodiment. 3A and 3B are cross-sectional views showing a memory cell and a select transistor. Sectional drawing which shows NAND type flash memory. The figure which shows the example of the voltage supplied to each area | region shown in FIG. FIG. 2 is a circuit diagram showing an example of a data storage circuit shown in FIG. 1. FIGS. 7A, 7B, and 7C are diagrams showing threshold voltage distributions of a memory cell associated with writing and erasing operations. The figure which shows the write order of a NAND cell. FIG. 2 is a waveform diagram showing a read operation of the circuit shown in FIG. FIG. 5 is a diagram schematically showing a read operation according to the first embodiment. 10 is a flowchart showing a first page write operation. The flowchart which shows the write-in operation | movement of a 2nd page. The figure which shows the EASB (Erased Area Self Boost) write-in method. 14A and 14B show the second embodiment. FIG. 14A is an exploded perspective view schematically showing the arrangement of bit lines and source lines, and FIG. FIG. 15 is a cross-sectional view taken along line 14b-14b of FIG. FIGS. 15A and 15B show a third embodiment. FIG. 15A is an exploded perspective view schematically showing the arrangement of bit lines and source lines, and FIG. FIG. 15 is a cross-sectional view taken along the line 15b-15b in FIG. FIG. 16 is a cross-sectional view taken along line 16-16 in FIG. FIGS. 17A and 17B show a fourth embodiment. FIG. 17A is an exploded perspective view schematically showing the arrangement of bit lines and source lines, and FIG. FIG. 18 is a cross-sectional view taken along line 17b-17b of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, WL0-WL31 ... Word line, BL0e-BL8ko ... Bit line, SRC0e-SRC8ko ... Sub source line, SRC ... Main source line, S1, S2 ... Selection gate, 7-1 ... Constant voltage generation circuit, M1 , M2, M3... First to third metal wiring layers.

Claims (5)

A memory cell array in which a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines are arranged;
A plurality of source lines disposed along each of the plurality of bit lines and connected to the respective sources of the plurality of memory cells ;
The plurality of bit lines include a first bit line that is an odd-numbered bit line and a second bit line that is an even-numbered bit line, and the plurality of source lines include first and second source lines. The first source line is disposed along the first bit line; the second source line is disposed along the second bit line; and the first source line and the first source line The bit line, the second source line, and the second bit line are formed in different layers . 2. The semiconductor memory device according to claim 1, wherein the first source line and the second source line are connected. 2. The semiconductor memory device according to claim 1, further comprising a voltage generation circuit for supplying a constant voltage to the first and second source lines when reading data. A plurality of first selection gates connecting the sources of the plurality of memory cells and the first and second source lines, and a drain of the plurality of memory cells and the first and second bit lines are connected. A plurality of second selection gates that are turned on after the first and second bit lines are charged, and the first and second selection gates are turned on. 2. The semiconductor memory device according to claim 1, wherein the charge of the bit line is discharged to the first and second source lines. Formed between a first layer in which the first bit line and the first source line are disposed, and a second layer in which the second bit line and the second source line are disposed. 2. The semiconductor memory device according to claim 1, further comprising a wiring layer that connects the first source line and the second source line.

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