KR100673648B1 - Method for Reducing Contact Resistance between Tungsten Plug and Copper Interconnect - Google Patents

Method for Reducing Contact Resistance between Tungsten Plug and Copper Interconnect Download PDF

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KR100673648B1
KR100673648B1 KR1020040117084A KR20040117084A KR100673648B1 KR 100673648 B1 KR100673648 B1 KR 100673648B1 KR 1020040117084 A KR1020040117084 A KR 1020040117084A KR 20040117084 A KR20040117084 A KR 20040117084A KR 100673648 B1 KR100673648 B1 KR 100673648B1
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tungsten plug
tungsten
plug
copper
contact resistance
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KR20060079318A (en
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김동준
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers

Abstract

본 발명은 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법에 관한 것으로서, 보다 상세하게는 반도체 기판상에 콘택홀을 형성하는 단계; 상기 콘택홀 내부에 인위적인 키 홀(key hole)을 갖는 텅스텐 플러그를 형성한 뒤 일정크기의 키 홀이 표면에 노출될 수 있도록 CMP 하는 단계; 상기 텅스텐 플러그에 상부 금속배선을 형성하기 위하여 절연막을 증착하는 단계; 상기 텅스텐 플러그 상부의 절연막을 식각하여 형성된 패턴 내에서 텅스텐 플러그를 일정두께로 노출시켜 M 자형 텅스텐 플러그를 형성한 후 고온에서 열처리하는 단계; 상기 M자형 텅스텐 플러그의 노출된 부분을 Ar 스퍼터(Sputter) 식각하는 단계; 및 상기 M자형 텅스텐 플러그상에 배리어(barrier) 및 시드(seed)를 증착한 후 구리 금속배선을 형성하는 단계를 포함하는 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법에 관한 것이다. 본 발명의 방법을 이용하면 텅스텐 플러그와 구리 박막과의 접촉면적을 크게 하여 동일한 디자인룰(design rule)에서도 종래의 방법보다 저항이 낮은 콘택을 형성할 수 있으며, 아울러 텅스텐 플러그 키홀의 단차피복성을 완화시킬 수 있는 장점이 있다.The present invention relates to a method for reducing contact resistance between a tungsten plug and a copper wiring, and more particularly, to form a contact hole on a semiconductor substrate; Forming a tungsten plug having an artificial key hole in the contact hole and then CMPing a predetermined size of the key hole to be exposed to the surface; Depositing an insulating film to form an upper metal wiring on the tungsten plug; Exposing the tungsten plug to a predetermined thickness in a pattern formed by etching the insulating film on the tungsten plug to form an M-shaped tungsten plug, and then heat-treating at a high temperature; Etching an exposed portion of the M-shaped tungsten plug with an Ar sputter; And forming a copper metal wiring after depositing a barrier and a seed on the M-shaped tungsten plug, and a method of reducing contact resistance between the tungsten plug and the copper wiring. By using the method of the present invention, the contact area between the tungsten plug and the copper thin film can be increased to form a contact having a lower resistance than the conventional method even under the same design rule. There is an advantage that can be mitigated.

접촉저항, 텅스텐 플러그, 금속배선Contact resistance, tungsten plug, metal wiring

Description

텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법{Method for Reducing Contact Resistance between Tungsten Plug and Copper Interconnect}Method for Reducing Contact Resistance between Tungsten Plug and Copper Interconnect}

도 1a 내지 도 1g는 본 발명에 따른 접촉 저항 감소 방법의 공정 과정을 보여주는 모식도이다.1A to 1G are schematic views showing a process of the method for reducing contact resistance according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11 ; 소스(source), 12 ; 드레인(drain),11; Source, 12; Drain,

13 ; 게이트(gate), 14 ; 하부 절연막,13; Gate, 14; Bottom insulating film,

15 ; 텅스텐 플러그, 16 ; 제2 절연막,15; Tungsten plug, 16; Second insulating film,

17 ; 제3 절연막, 18 ; 배리어(barrier),17; Third insulating film 18; Barriers,

19 ; 구리 금속 배선19; Copper metal wiring

본 발명은 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법에 관한 것으로서, 보다 상세하게는 텅스텐 플러그와 구리 금속배선간의 접촉저항을 감소시키기 위하여 텅스텐 플러그 내에 임의로 키홀(key hole)을 형성시킴으로써 M자형 텅스텐 플러그를 형성하는 단계를 포함하는 텅스텐 플러그와 구리배선간의 접촉 저항을 감소시키는 방법에 관한 것이다.The present invention relates to a method for reducing contact resistance between a tungsten plug and a copper wiring, and more particularly, to form an M-shaped hole by forming a key hole in the tungsten plug to reduce the contact resistance between the tungsten plug and the copper metal wiring. A method of reducing contact resistance between a tungsten plug and a copper wiring comprising forming a tungsten plug.

최근 지속적으로 반도체 소자가 집적화되고 관련 기술이 발전함에 따라 속도나 저항 혹은 금속간의 기생 캐패시터 등이 문제점으로 대두되면서 종래의 알루미늄 대신 구리를 이용한 배선 공정이 차세대 소자의 배선 공정으로 각광을 받고 있다. 반도체 소자가 경박단소화됨에 따라 소자를 실리콘 기판상에 구현하는 금속배선기술에 대한 디자인룰(design rule)도 감소하게 되었으며, 이에 따라 텅스텐 플러그와 구리배선간의 콘택 면적이 점차 감소하게 되었다. 이러한 금속간의 콘택 면적의 감소는 접촉저항의 증가를 초래하기 때문에 초고속 소자의 구현을 위해서는 저저항의 접촉저항을 갖는 새로운 구조의 콘택 형성 기술이 필수 불가결하다. 그러나, 현재 이러한 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키기 위한 효과적인 방법의 개발이 미진한 실정이다.Recently, as semiconductor devices are continuously integrated and related technologies have been developed, problems such as speed, resistance, or parasitic capacitors between metals have emerged as problems, and conventional wiring processes using copper instead of aluminum have been spotlighted as wiring processes of next generation devices. As semiconductor devices become thinner and shorter, design rules for the metallization technology for implementing the devices on silicon substrates are also reduced. As a result, the contact area between the tungsten plug and the copper wiring is gradually reduced. Since the reduction of the contact area between the metals leads to an increase in contact resistance, a new structure of contact formation technology having a low resistance contact resistance is indispensable for the implementation of ultra-high speed devices. However, the development of an effective method for reducing the contact resistance between the tungsten plug and the copper wiring is currently insufficient.

본 발명은 상기와 같은 종래 텅스텐 플러그와 구리배선간의 접촉저항 증가 문제를 해결하기 위하여 안출된 것으로서, 텅스텐 플러그 공정시 텅스텐 플러그 증착두께를 플러그 갭 필(gap fill)이 가능한 목표치보다 낮추고 키 홀을 만들어 CMP 공정 및 패터닝 공정을 이용하여 M자 형태의 텅스텐 플러그를 형성한 후, 이를 구리 금속 배선 공정의 배리어/시드 공정과 전기도금을 통하여 콘택 영역에서 Cu와 텅스텐 플러그 사이의 접촉면적을 증가시킴으로써 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법을 제공하는 것을 목적으로 한다.The present invention has been made to solve the problem of increasing the contact resistance between the conventional tungsten plug and the copper wiring, the tungsten plug deposition thickness during the tungsten plug process is lower than the target that can be plug gap fill (key gap) to make a key hole After forming M-type tungsten plugs using the CMP process and the patterning process, the tungsten plug is increased by increasing the contact area between Cu and tungsten plugs in the contact region through the barrier / seed process of copper metal wiring process and electroplating. It is an object of the present invention to provide a method for reducing contact resistance between a copper wiring and a copper wiring.

상기 목적을 달성하기 위하여, 본 발명은 반도체 기판상에 콘택홀을 형성하는 단계; 상기 콘택홀 내부에 인위적인 키 홀을 갖는 텅스텐 플러그를 형성한 뒤 일정크기의 키 홀이 표면에 노출될 수 있도록 CMP 하는 단계; 상기 텅스텐 플러그에 상부 금속배선을 형성하기 위하여 절연막을 증착하는 단계; 상기 텅스텐 플러그 상부의 절연막을 식각하여 형성된 패턴 내에서 텅스텐 플러그를 일정두께로 노출시켜 노출된 부분이 M 모양이 될 수 있도록 플러그를 형성한 후 고온에서 열처리하는 단계; 상기 M자형 텅스텐 플러그의 노출된 부분을 Ar 스퍼터(Sputter) 식각하는 단계; 및 상기 M자형 텅스텐 플러그상에 배리어 및 시드를 증착한 후 구리 금속 배선을 형성하는 단계를 포함하는 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming a contact hole on a semiconductor substrate; Forming a tungsten plug having an artificial key hole in the contact hole and then performing CMP to expose a predetermined size of the key hole to the surface; Depositing an insulating film to form an upper metal wiring on the tungsten plug; Exposing the tungsten plug to a predetermined thickness in a pattern formed by etching the insulating film on the tungsten plug to form a plug such that the exposed portion may have an M shape, and then performing heat treatment at a high temperature; Etching an exposed portion of the M-shaped tungsten plug with an Ar sputter; And forming a copper metal wiring after depositing a barrier and a seed on the M-shaped tungsten plug, thereby providing a method of reducing contact resistance between the tungsten plug and the copper wiring.

이하, 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail.

본 발명의 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법은The method of reducing the contact resistance between the tungsten plug and the copper wiring of the present invention

1) 반도체 기판상에 콘택홀을 형성하는 단계;1) forming a contact hole on the semiconductor substrate;

2) 상기 콘택홀 내부에 인위적인 키 홀을 갖는 텅스텐 플러그를 형성한 뒤 일정크기의 키 홀이 표면에 노출될 수 있도록 CMP 하는 단계;2) forming a tungsten plug having an artificial key hole in the contact hole, and then CMPing a predetermined size of the key hole to be exposed to the surface;

3) 상기 텅스텐 플러그에 상부 금속배선을 형성하기 위하여 절연막을 증착하는 단계;3) depositing an insulating film to form an upper metal wiring on the tungsten plug;

4) 상기 텅스텐 플러그 상부의 절연막을 식각하여 형성된 패턴 내에서 텅스텐 플러그를 일정두께로 노출시켜 노출된 플러그 부분이 M자 모양이 될 수 있도록 오버에치(over etch)하여 플러그를 형성한 후 고온에서 열처리하는 단계;4) After exposing the tungsten plug to a predetermined thickness in the pattern formed by etching the insulating film on the upper surface of the tungsten plug, the exposed plug portion is overetched to form an M shape, and the plug is formed at a high temperature. Heat treatment;

5) 상기 M자형 텅스텐 플러그의 노출된 부분을 Ar 스퍼터(Sputter) 식각하는 단계; 및5) Ar sputter etching the exposed portion of the M-shaped tungsten plug; And

6) 상기 M자형 텅스텐 플러그상에 배리어 및 시드를 증착한 후 구리 금속 배선을 형성하는 단계를 포함한다.6) forming a copper metal wiring after depositing a barrier and seed on the M-shaped tungsten plug.

우선, 도 1a을 참조하면, 게이트(13)와 소스(11) 및 드레인(12)이 형성된 반도체 기판 상에 하부 절연막(14)을 증착한 다음, 선택적 식각 공정을 진행하여 플러그 형성용 콘택홀을 형성한다.
도 1b를 참조하면, 상기 콘택홀이 형성된 결과물 상에 상기 콘택홀이 완전히 매립되도록 충분한 두께의 텅스텐을 증착하여 인위적인 키 홀을 갖는 텅스텐 플러그(15)를 형성한 뒤 일정크기의 키 홀이 표면에 노출될 수 있도록 CMP 한다.
도 1c 및 도 1d를 참조하면, 상기 텅스텐 플러그(15)에 상부 금속배선을 형성할 수 있도록 절연막 즉, 제2 및 제3 절연막(16, 17)을 증착한 후 포토 및 식각공정을 진행하여 패턴을 형성한다. 이때, 패턴 내에 M자 모양의 텅스텐 플러그(15)가 노출될 수 있도록 오버에치 공정을 진행한다. 상기에서, M자형 텅스텐 플러그(15)를 형성하기 위하여 키홀이 홀 크기의 30 내지 80%, 바람직하게는 40 내지 60% 정도를 차지할 수 있도록 텅스텐을 증착시키고, 오버에치의 경우에는 패턴 내에 텅스텐 플러그가 1,000Å 이상 돌출될 수 있도록 하부 절연막(14)을 500 내지 2,000Å 정도 식각하는 것이 바람직하다. 이때, 식각후 노출된 M자형 텅스텐 플러그(15)는 식각 및 세척과정에서 형성된 부산물들이 키홀에 축적되지 않도록 하여야 하며, 배리어/시드 증착전에 부산물에 의해 벌어짐(delamination)이 발생하지 않도록 고온에서 열처리를 수행한다. 상기 열처리는 질소, 아르곤, 수소 또는 헬륨 분위기에서 200 내지 500℃ 온도로 수행하여 M자형 텅스텐 플러그(15) 내에 잔류하는 화합물들을 제거하는 것이 바람직하다.First, referring to FIG. 1A, a lower insulating film 14 is deposited on a semiconductor substrate on which a gate 13, a source 11, and a drain 12 are formed, and then a selective etching process is performed to form a contact hole for forming a plug. Form.
Referring to FIG. 1B, a tungsten plug 15 having a sufficient thickness is deposited by depositing tungsten having a sufficient thickness so that the contact hole is completely filled on the resultant product in which the contact hole is formed. CMP to expose.
Referring to FIGS. 1C and 1D, an insulating film, that is, second and third insulating films 16 and 17 are deposited to form an upper metal wiring on the tungsten plug 15, and then a photo and etching process is performed. To form. At this time, the over-etch process is performed so that the M-shaped tungsten plug 15 is exposed in the pattern. In the above, in order to form the M-shaped tungsten plug 15, tungsten is deposited so that the keyhole may occupy 30 to 80%, preferably 40 to 60% of the hole size, and in the case of overetching, the tungsten plug It is preferable to etch the lower insulating film 14 to about 500 to 2,000 있도록 to protrude more than 1,000 Å. At this time, the M-shaped tungsten plug 15 exposed after etching should prevent the by-products formed during the etching and washing process from accumulating in the keyhole, and the heat treatment is performed at a high temperature so that delamination does not occur by the by-products before barrier / seed deposition. Perform. The heat treatment is preferably carried out in a nitrogen, argon, hydrogen or helium atmosphere at a temperature of 200 to 500 ° C. to remove compounds remaining in the M-shaped tungsten plug 15.

도 1e를 참조하면, 노출된 텅스텐 플러그(15) 위에 금속 배선을 형성하기 위해 콘택 전세척(precleaning)을 실시한다. 이때, 키홀에 배리어와 시드가 잘 증착될 수 있도록 Ar 스퍼터 식각 방법으로 M자형 텅스텐 플러그(15)의 프로필(profile)을 변화시킴으로써 단차피복성(step coverage)을 완화시킨다. 상기 Ar 스퍼터 식각은 50 내지 600V의 높은 바이아스(bias)에서 수행되는 것이 바람직하다.Referring to FIG. 1E, contact precleaning is performed to form metallization over the exposed tungsten plug 15. At this time, the step coverage is alleviated by changing the profile of the M-shaped tungsten plug 15 by the Ar sputter etching method so that the barrier and seeds can be well deposited in the keyhole. The Ar sputter etching is preferably performed at high vias of 50 to 600V.

도 1f를 참조하면, 스퍼터 식각으로 전세척된 텅스텐 플러그(15) 위에 배리어(18)가 증착된다. 상기 배리어(18)는 ALD (atomic layer deposition) 방법으로 50Å 미만의 균일한 두께로 형성하여 후속공정에서 증착되는 구리 시드 박막의 부착 촉진제(adhesion promotor)로 작용할 수 있도록 한다. 상기 배리어(18)는 티타늄(Ti) 계열, 탄탈륨(Ta) 계열 및 텅스텐(W) 계열의 금속으로 구성된 군으로부터 선택될 수 있다.Referring to FIG. 1F, a barrier 18 is deposited over the tungsten plug 15 precleaned by sputter etching. The barrier 18 is formed to have a uniform thickness of less than 50 mm by ALD (atomic layer deposition) method to act as an adhesion promoter of the copper seed thin film deposited in a subsequent process. The barrier 18 may be selected from the group consisting of titanium (Ti) -based, tantalum (Ta) -based and tungsten (W) -based metals.

도 1g를 참조하면, 구리 시드(도시하지 않음)를 배리어(18) 위에 증착한 후 구리 금속 배선(19)을 형성한다. 이때, 구리 시드는 텅스텐 플러그(15)에 존재하는 M자형 키홀의 크기에 따라 증착방법이 결정되는데, 단차가 열악한 패턴에 대해서는 PVD (physical vapor deposition) 또는 CVD (chemical vapor deposition) 방법으로 시드를 증착함으로써 보이드(void) 형성을 억제할 수 있도록 하며, 300 내지 1,200Å의 두께로 증착되는 것이 바람직하다.Referring to FIG. 1G, a copper seed (not shown) is deposited over the barrier 18 to form a copper metal interconnect 19. At this time, the copper seed is determined according to the size of the M-shaped keyhole present in the tungsten plug 15. For the poor pattern of steps, the seed is deposited by PVD (physical vapor deposition) or CVD (chemical vapor deposition) method. It is possible to suppress the formation of void (void), it is preferable to be deposited to a thickness of 300 to 1,200Å.

상기에서 살펴본 바와 같이, 본 발명의 방법을 이용하면 텅스텐 플러그와 구리 박막과의 접촉면적을 크게 하여 동일한 디자인룰에서도 종래의 방법보다 저항이 낮은 콘택을 형성할 수 있으며, 아울러 텅스텐 플러그 키홀의 단차피복성을 완화시킬 수 있는 장점이 있다.As described above, by using the method of the present invention, the contact area between the tungsten plug and the copper thin film can be increased to form a contact having a lower resistance than the conventional method even in the same design rule, and the step coating of the tungsten plug keyhole There is an advantage to mitigate sex.

Claims (8)

1) 반도체 기판상에 콘택홀을 형성하는 단계;1) forming a contact hole on the semiconductor substrate; 2) 상기 콘택홀 내부에 인위적인 키 홀(key hole)을 갖는 텅스텐 플러그를 형성한 뒤 일정크기의 키 홀이 표면에 노출될 수 있도록 CMP 하는 단계;2) forming a tungsten plug having an artificial key hole in the contact hole and then CMPing the key hole having a predetermined size to be exposed to the surface; 3) 상기 텅스텐 플러그에 상부 금속배선을 형성하기 위하여 절연막을 증착하는 단계;3) depositing an insulating film to form an upper metal wiring on the tungsten plug; 4) 상기 텅스텐 플러그 상부의 절연막을 식각하여 형성된 패턴 내에서 텅스텐 플러그를 일정두께로 노출시켜 노출된 플러그 부분이 M 자 모양이 될 수 있도록 오버에치(over etch)하여 플러그를 형성한 후 질소, 아르곤, 수소 또는 헬륨 분위기에서 200 내지 500℃ 고온에서 열처리하는 단계;4) After the tungsten plug is formed by etching the insulating film on the upper surface of the tungsten plug, the tungsten plug is exposed to a predetermined thickness, so that the exposed plug portion is overetched to form an M shape, followed by nitrogen, Heat treatment at 200 to 500 ° C. high temperature in argon, hydrogen or helium atmosphere; 5) 상기 M자형 텅스텐 플러그의 노출된 부분을 Ar 스퍼터(Sputter) 식각하는 단계; 및5) Ar sputter etching the exposed portion of the M-shaped tungsten plug; And 6) 상기 M자형 텅스텐 플러그상에 배리어(barrier) 및 시드(seed)를 증착한 후 구리 금속 배선을 형성하는 단계를 포함하는 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법.6) forming a copper metal wiring after depositing a barrier and a seed on the M-shaped tungsten plug, wherein the contact resistance between the tungsten plug and the copper wiring is reduced. 제 1항에 있어서,The method of claim 1, 상기 M자형 텅스텐 플러그를 형성하기 위하여 키홀이 홀 크기의 30 내지 80%를 차지하도록 텅스텐을 증착시키는 것을 특징으로 하는 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법.And depositing tungsten such that the key hole occupies 30 to 80% of the hole size to form the M-shaped tungsten plug. 제 2항에 있어서,The method of claim 2, 상기 키홀은 홀 크기의 40 내지 60%를 차지하도록 텅스텐을 증착시키는 것을 특징으로 하는 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법.And the keyhole deposits tungsten so as to occupy 40 to 60% of the hole size. 제 1항에 있어서,The method of claim 1, 상기 절연막을 500 내지 2,000Å 식각하는 것을 특징으로 하는 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법.And 500 to 2,000 kW of the insulating film to reduce contact resistance between the tungsten plug and the copper wiring. 삭제delete 제 1항에 있어서,The method of claim 1, 상기 Ar 스퍼터 식각은 50 내지 600V의 높은 바이아스(bias)에서 수행되는 것을 특징으로 하는 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법.And wherein the Ar sputter etching is performed at a high bias of 50 to 600V. 제 1항에 있어서,The method of claim 1, 상기 배리어는 티타늄(Ti) 계열, 탄탈륨(Ta) 계열 및 텅스텐(W) 계열의 금속 으로 구성된 군으로부터 선택되는 것을 특징으로 하는 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법.And the barrier is selected from the group consisting of titanium (Ti), tantalum (Ta) and tungsten (W) based metals. 제 1항에 있어서,The method of claim 1, 상기 시드는 300 내지 1,200Å의 두께로 증착되는 것을 특징으로 하는 텅스텐 플러그와 구리배선간의 접촉저항을 감소시키는 방법.And the seed is deposited to a thickness of 300 to 1,200 Å.
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