KR100673547B1 - Method for fabricating semiconductor devices by using pattern with three-dimensional - Google Patents

Abstract

A method of manufacturing a semiconductor device is provided to simplify manufacturing processes and to improve the productivity by performing sequentially a selective etching process or an etch back process using a three dimensional pattern structure. A semiconductor material, a doping material and an electrode material are sequentially formed on a substrate(102) with a gate electrode(104a) and a gate insulating layer(106). A three dimensional polymer pattern structure(114) is formed on the resultant structure. The three dimensional polymer pattern structure includes a source electrode defining pattern, a drain electrode defining pattern and a via hole defining pattern. The electrode material is partially exposed to the outside by performing an etch back process on the three dimensional polymer pattern structure. A semiconductor layer(108a), a doping layer(110a), and source/drain electrodes(112a) are formed by performing a selective etching process on the resultant structure. The via hole defining pattern alone remains on the resultant structure by performing an etch back process on the three dimensional polymer pattern structure.

Description

Method of manufacturing semiconductor device using pattern of three-dimensional structure {METHOD FOR FABRICATING SEMICONDUCTOR DEVICES BY USING PATTERN WITH THREE-DIMENSIONAL}

1 is a cross-sectional view of a structure in which a three-dimensional structured polymer pattern is formed on a substrate on which a plurality of materials are stacked for manufacturing a semiconductor device according to an embodiment of the present invention;

2a to 2k is a process flow diagram showing the main process for manufacturing a semiconductor device using a three-dimensional structure polymer pattern according to a preferred embodiment of the present invention,

3 is a cross-sectional view of a structure in which a three-dimensional structured polymer pattern is formed on a substrate on which a plurality of materials are stacked for manufacturing a semiconductor device according to another exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

102 substrate 104 gate electrode

106 gate insulating film 108 semiconductor film

110: doping film 112: source / drain electrode

114: three-dimensional structural polymer pattern 114a: pattern for defining the source electrode

114b: Pattern for defining a drain electrode 114c: Pattern for defining a via hole

114d: Pattern for defining a metal slit 116: protective film

117: via hole 118: ITO electrode

The present invention relates to a technique for manufacturing a semiconductor device, and more particularly, using a pattern of a three-dimensional structure suitable for manufacturing a thin film transistor (TFT) of a liquid crystal display (LCD) using a polymer pattern having a three-dimensional structure A method for manufacturing a semiconductor device.

As is well known, a liquid crystal display (LCD) using a thin film transistor has a lower substrate on which an array of transistors are formed for individual driving of each pixel (pixel), and red (R) and green (G) colors that can implement color. And a top glass substrate on which an array of color filter materials of blue (B) is formed, and a liquid crystal material whose arrangement direction changes with the application of an electric field is filled between the two organic substrates. The present invention relates to a method of manufacturing a thin film transistor array for individually driving each pixel in a TFT-LCD manufacturing process of such a structure.

On the other hand, in a typical method of manufacturing a thin film transistor array of a liquid crystal display device, a photolithography technique for forming a fine pattern using light is mainly used. In the manufacture of a thin film transistor array through the photolithography technique, a photomask is used. The alignment / exposure and etching process using (or reticle) is performed repeatedly.

More specifically, the conventional method using a photomask is formed by forming a photosensitive polymer thin film on the substrate by a method such as roll coding or spin coating, and then aligning and exposing the photomask on which the desired pattern is formed on the previous pattern or substrate. An anisotropic etching process or a chemical process using a plasma such as reactive ion etching (RIE) using the etching mask as an etching barrier layer by forming an etching mask on the substrate by removing the photosensitive polymer material of the exposed portion through the developing process. Wet etching using a solution removes the exposed portions of the thin film and then forms a single thin film pattern by removing the etch mask. This series of steps is performed as many times as necessary to form the device (eg, 4-5 times). Exposure process) by repeatedly applying a thin film transistor array having a desired structure and properties. The small.

Therefore, the conventional method has a problem that the manufacturing process is very complicated because it requires a number of mask and alignment processes using a large number of photomasks, such a problem is the increase in manufacturing cost and the decrease in production yield (reproducibility / uniformity) Gender security issues).

The present invention is to solve the above problems of the prior art, by forming a TFT for LCD through the selective front etching process using the pattern of the three-dimensional structure, the three-dimensional structure pattern that can realize the simplification of the manufacturing process It is an object of the present invention to provide a method for manufacturing a semiconductor device.

In order to achieve the above object, the present invention is a method for manufacturing a semiconductor device for a liquid crystal display device having a gate electrode and a source / drain electrode, the semiconductor material, the doping material and the electrode material on a substrate on which the gate electrode and the gate insulating film is formed Forming a 3D structure polymer pattern including a process of sequentially forming a pattern, a pattern for defining a source electrode, a pattern for defining a drain electrode, and a pattern for defining a via hole, and etching the front surface of the 3D structural polymer pattern to form a top portion of the electrode material Selectively etching part of the electrode material, the dopant material and the semiconductor material until the part of the surface of the gate insulating film is exposed through a process of exposing the surface of the gate insulating film through a front surface etching using the remaining three-dimensional structured polymer pattern as an etching mask A semiconductor film, a doped film and a source / de on the gate insulating film Forming a lane electrode, selectively etching only the remaining 3D structure polymer pattern and remaining only the via hole defining pattern, forming a protective film on the entire surface of the substrate on which the via hole defining pattern remains; Forming a via hole exposing a portion of the surface of the source electrode by removing the via hole defining pattern; and forming a ITO thin film material on the front surface of the substrate and then selectively removing a portion of the source electrode through the via hole. Provided is a method of manufacturing a semiconductor device using a pattern of a three-dimensional structure including forming a connected ITO electrode.

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the core technical idea of the present invention, unlike the conventional method of manufacturing a thin film transistor element for a liquid crystal display device through a complicated process of repeatedly performing the alignment / exposure and etching process using a photomask (or reticle), TFT A plurality of materials are sequentially stacked on the substrate to be formed, and a polymer pattern having a three-dimensional structure including a source electrode defining pattern, a drain electrode defining pattern, and a via hole defining pattern is formed thereon. By sequentially performing a selective etching or a front surface etching process, a thin film transistor for a liquid crystal display device is manufactured. Thus, the object of the present invention can be easily achieved through such technical means.

1 is a cross-sectional view of a structure in which a three-dimensional structured polymer pattern is formed on a substrate on which a plurality of materials are stacked for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

1 illustrates a semiconductor material 108a and a doping material 110a on a substrate 102 on which a gate electrode 104a having an arbitrary pattern and a gate insulating film 106 formed in a form of filling the gate electrode 114a are stacked. ) And the electrode material 112a are sequentially stacked, and a three-dimensional structural polymer pattern 114 is formed thereon. That is, Figure 1 shows a structure in which the three-dimensional structure polymer pattern 114, which is the most important technical gist of the present invention, is laminated on the substrate 102.

In the structure of FIG. 1, G-SiN _x may be used as the gate insulating layer 106, a-Si: H may be used as the semiconductor material 108a, and N ⁺ may be used as the doping material 110a.

In addition, the three-dimensional structural polymer pattern 114 formed on the electrode material 112a includes a source electrode defining pattern 114a, a drain electrode defining pattern 114b, and a via hole defining pattern 114c. The 114a serves as an etch mask for forming the source electrode, the drain electrode defining pattern 114b serves as an etch mask for forming the drain electrode, and the via hole defining pattern 114c forms a thin film on the substrate 102. After the transistor TFT is formed, a pattern for forming a via hole for connecting the ITO electrode and the source electrode to be formed through a subsequent process when the protective film is deposited thereon.

Next, a series of processes for manufacturing a semiconductor device according to the present invention using the three-dimensional structural polymer pattern comprising the source electrode defining pattern, the drain electrode defining pattern, and the via hole defining pattern as described above will be described.

2A to 2K are flowcharts illustrating main processes of manufacturing a semiconductor device using a 3D structural polymer pattern according to a preferred embodiment of the present invention.

Referring to FIG. 2A, a metal material 104 is formed on a substrate 102 by performing a deposition process such as sputtering, PECVD, and the like by applying a photoresist thereon and then performing an exposure and development process. An etching mask 105 of a polymer having an arbitrary pattern is formed on the 104.

In this case, the etching mask may be formed through a process other than the conventional exposure process, for example, soft molding, capillary force lithography, pattern transfer method using Rigidplex, ultraviolet curable polymer, or the like. Of course there is.

Next, an etching process using the etch mask 105 as an etch barrier layer is performed to selectively remove the metal material 104, and thereafter, by removing (striping) the remaining etch mask 105, as an example, FIG. 2B. As shown in, a gate electrode 104a having an arbitrary pattern is formed on the substrate 102.

Subsequently, by sequentially performing a deposition process having an arbitrary process condition, as shown in FIG. 2C, the gate insulating film 106 and the semiconductor material (for example, the front surface of the substrate 102 on which the gate electrode 104a is formed) are formed. 108a), the doping material 110a and the electrode material 112a are sequentially formed. The gate insulating layer 106 may include a G-SiN _x or the like, an a-Si: H or the like as the semiconductor material 108a, or an N ⁺ doping film doped with n as the doping material 110a. The film 110 is intended to reduce contact resistance.

Next, a three-dimensional structural polymer pattern 114 formed of a source electrode defining pattern 114a, a drain electrode defining pattern 114b, and a via hole defining pattern 114c is formed on the electrode material 112a (FIG. 2D). The three-dimensional structure polymer pattern 114 is soft molding (capillary force lithography), pattern transfer method using Rigidflex previously proposed by the researchers including the present inventors, UV curable polymer, etc. It can be easily formed through.

Subsequently, an anisotropic etching process using an etching gas capable of etching the 3D structure polymer pattern 114 is performed to uniformly remove the top of the 3D structure polymer pattern 114 (front etching). As shown in FIG. 2E, the upper portion of the metal material 112a is selectively exposed. In this case, the shape of the source electrode defining pattern 114a, the drain electrode defining pattern 114b, and the via hole defining pattern 114c is maintained in the three-dimensional structure polymer pattern 114. In this case, the front surface etching of the 3D structure polymer pattern 114 is performed through a dry etching process.

In addition, an etching process using the remaining three-dimensional structure polymer pattern 114 as an etching mask is performed to selectively remove a portion of the metal material 112a, the doping material 110a, and the semiconductor material 108a to form a gate insulating film. By exposing a portion of the upper portion 106, as an example, as shown in FIG. 2F, the semiconductor film 108, the doped film 110, and the source / source are formed on the gate insulating film 106 having the gate electrode 104 formed thereunder. The drain electrode 112 is formed sequentially. In this case, the shape of the source electrode defining pattern 114a, the drain electrode defining pattern 114b, and the via hole defining pattern 114c is maintained in the 3D structure polymer pattern 114.

Here, since the pattern spacing (channel width) between the source electrode on the left and right sides and the center drain electrode is relatively narrow compared to the distance on the opposite side of the drain electrode of the source electrode on both sides, the metal material 112a and the doping material 110a. ) And the semiconductor material 108a are sequentially etched, while both the electrode material 112a and the doping material 110a are etched between the source electrode and the drain electrode, but only a part of the semiconductor material 108a is etched. That is, since the channel width is narrow between the source electrode and the drain electrode, and the etching speed is slow, the upper portion of the gate insulating layer 106 is not exposed. This is to prevent the channel from being cut off by exposing the surface of the gate insulating film 106.

On the other hand, unlike the above, as shown in FIG. 3 as an example, a polymer pattern (pattern for defining a metal slit) 114d capable of forming a slit when etching a metal material is inserted (that is, a pattern for defining a source electrode). The metal thin film slit serves as an etch mask so that the metal thin film slit serves as an etching mask to etch to a certain depth only at the channel portion, that is, both the electrode material 112a and the doping material 110a are etched, but the semiconductor The material 108a may allow only a portion to be etched.

Next, an anisotropic etching process using an etching gas capable of etching the three-dimensional structure polymer pattern 114 is performed to uniformly remove the upper portion of the three-dimensional structure polymer pattern 114 (front etching). As shown in FIG. 2G, the upper portion of the source electrode (left and right electrodes in the drawing structure) and the upper portion of the drain electrode (center electrode in the drawing structure) are selectively exposed. In this case, only the via hole defining pattern 114c remains in the three-dimensional structure polymer pattern 114.

Again, by performing a deposition process having an arbitrary process condition, as shown in FIG. 2H, for example, a protective film such as a protective film such as SiN _x on the entire surface of the substrate 102 where only the via hole defining pattern 114c remains. In this case, the thickness of the passivation layer 116 should be lower than the height of the via hole defining pattern 114c.

Subsequently, the via hole defining pattern 114c remaining in the form rising above the passivation layer 116 is removed, thereby forming a via hole 117 exposing an upper portion of the source electrode as shown in FIG. 2I as an example.

Next, the ITO electrode material 118a is formed on the front surface of the substrate 102 by completely depositing the via hole 117 as shown in FIG. 2J by performing a deposition process such as sputtering or PECVD. do.

Finally, after the photoresist is applied on the ITO electrode material 118a, an exposure and development process may be performed to form an etch mask having an arbitrary pattern on the ITO electrode material 118a, and the etch mask thus formed may be used as an etch barrier. By selectively removing a portion of the ITO electrode material 118a by performing a layer etching process and stripping the remaining etching mask, an example is electrically connected to the source electrode through the via hole 117, as shown in FIG. 2K. Complete the ITO electrode 118 is connected to. Here, of course, the patterning process for forming the ITO electrode may use a non-traditional patterning process as well as a conventional exposure process.

Therefore, in the present invention, the thin film transistor of the semiconductor device for LCD is subjected to three patterning processes, that is, a patterning process for forming a gate electrode, a patterning process for forming a three-dimensional structure polymer pattern, and a patterning process for forming an ITO electrode. TFT) can be manufactured.

As described above, according to the present invention, unlike the above-described conventional method of manufacturing a thin film transistor element for a liquid crystal display device through a complicated process of repeatedly performing the alignment / exposure and etching process using a photomask (or reticle) And sequentially stacking a plurality of materials on a substrate on which a TFT is to be formed, and forming a polymer pattern having a three-dimensional structure including a source electrode defining pattern, a drain electrode defining pattern, and a via hole defining pattern thereon. By sequentially performing a selective etching or a front surface etching process using a pattern, a thin film transistor for a liquid crystal display device may be manufactured, thereby simplifying a manufacturing process and improving productivity of a semiconductor device.

Claims (5)

A method of manufacturing a semiconductor element for a liquid crystal display device having a gate electrode and a source / drain electrode, Sequentially forming a semiconductor material, a doping material and an electrode material on the substrate on which the gate electrode and the gate insulating film are formed; Forming a three-dimensional structural polymer pattern including a source electrode defining pattern, a drain electrode defining pattern, and a via hole defining pattern; Exposing the upper portion of the electrode material by etching the 3D structure polymer pattern on the entire surface; A portion of the surface of the gate insulating film is selectively etched through the entire surface etching using the remaining three-dimensional structured polymer pattern as an etching mask, thereby selectively etching a portion of the electrode material, the doping material and the semiconductor material on the gate insulating film. Forming a semiconductor film, a doped film, and a source / drain electrode; Selectively front-etching only the remaining 3D structural polymer pattern to leave only the via hole defining pattern; Forming a protective film on an entire surface of the substrate on which the via hole defining pattern remains; Forming a via hole exposing a portion of a surface of the source electrode by removing the via hole defining pattern; A process of forming an ITO electrode connected to a source electrode through the via hole by forming an ITO thin film material on the front surface of the substrate and then selectively removing a portion thereof. Semiconductor device manufacturing method using a pattern of a three-dimensional structure comprising a. The method of claim 1, The 3D structure polymer pattern may further include a metal slit definition pattern serving as an etching mask when etching the metal material between the source electrode defining pattern and the drain electrode defining pattern. Semiconductor device manufacturing method. The method according to claim 1 or 2, The three-dimensional structural polymer pattern is formed on the electrode material through any one of soft molding, capillary force lithography, a pattern transfer method using Rigidflex, and an ultraviolet curable polymer. A semiconductor device manufacturing method using a pattern having a three-dimensional structure. The method according to claim 1 or 2, The front surface etching of the three-dimensional structure polymer pattern, a semiconductor device manufacturing method using a three-dimensional structure pattern, characterized in that performed by a dry etching process. The method according to claim 1 or 2, The protective film is a semiconductor device manufacturing method using a pattern having a three-dimensional structure, characterized in that formed to have a thickness at least lower than the thickness of the remaining via-hole defining pattern.

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