KR100673134B1 - Method for manufacturing of semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device is provided to secure discrete characteristics from source/drain regions and a resistive portion of an NMOS(N channel Metal Oxide Semiconductor) transistor by using a two-step ion implantation processes. A word line pattern is formed on an NMOS transistor region(a') of a semiconductor substrate(21). A first photoresist pattern for exposing source/drain forming regions and a resistive portion to the outside is formed on the resultant structure. A first ion implantation is performed on the resultant structure. A second photoresist pattern(37) for exposing the source/drain forming regions alone to the outside is formed on the resultant structure. A second ion implantation is performed on the resultant structure.

Description

Method for manufacturing a semiconductor device

1 is a process sectional view showing an impurity implantation process for forming a source / drain region and a resistor of a transistor according to the prior art;

2A-2C are process schematic diagrams illustrating one embodiment of an impurity implantation process for forming source / drain regions and resistor portions of a transistor in accordance with the method of the present invention;

<Brief description of the main parts of the drawing>

1, 21: semiconductor substrate 3, 23: word line

5: Photoresist Pattern 7: Mask for Impurity Injection

9: impurity implantation process 11: impurity implantation region

25: first photoresist pattern 27: first impurity implantation mask

29: first impurity implantation step 31: first impurity region

33: second photoresist pattern 37: second impurity implantation mask

39: second impurity implantation process 41: second impurity region

a, a ': transistor portion of NMOS

b, b ': resistance part

The present invention relates to a method for manufacturing a semiconductor device.

As the field of application of semiconductor devices expands today, there is an urgent need to develop a technology for manufacturing a large-capacity memory device in which the integration degree is improved and the electrical characteristics are not degraded. Accordingly, various studies have been conducted to obtain stable process conditions by improving photo-lithography processes, cell structures, physical property limitations of wiring forming materials and insulating film forming materials, and the like.

Meanwhile, as the integration of semiconductor devices increases, the size of physical dimensions such as channel lengths of MOS transistors and dielectric film thicknesses of gate lines decreases, and the effective channel length of semiconductor devices decreases accordingly. channel) effect.

In order to improve the short channel effect, (i) a method of reducing the thickness of the gate insulating film, (ii) a method of securing an effective channel length with respect to the gate line width by forming a recessed channel region under the gate line, or ( iii) When forming a source / drain region by an impurity implantation implanting an impurity into a specific portion of silicon or wafer under the gate, a shallow junction region in order to reduce the depletion region as much as possible The method of forming the above was introduced.

The impurity implantation process is primarily for forming the source / drain regions, but is also an important process for simultaneously forming a resistance portion of the device. The impurity implantation process uses N + impurities instead of conventional P + impurities to obtain more stable resistance.

In the previous semiconductor device fabrication, since the resistive portion space can be secured as much as the desired area, the impurity transistor portion and the resistive portion can be simultaneously formed in one impurity implantation process.

A method of manufacturing a semiconductor device including the impurity implantation process will be described in detail with reference to FIG. 1.

That is, referring to FIG. 1, the word line 3 is formed on the NMOS transistor portion a on the semiconductor substrate 1, and then a first photoresist layer (not shown) is formed on the entire surface thereof.

Exposing and developing the first photoresist layer (not shown) to form the first photoresist pattern 5 having the source / drain regions of the NMOS transistor portion a and the resistor portion b opened; An impurity implantation mask 7 is formed in which the source / drain regions of the NMOS transistor a and the resistor portion b are opened. Impurity injection process 9 is performed using the resultant as a mask. In this case, the impurity implantation process is carried out in 4E15 dose conditions using arsenic (As).

The impurity implantation process 9 forms an impurity implantation region 11 having the same resistance value on the source / drain region of the NMOS transistor portion a of the semiconductor substrate 1 and the resistor portion b.

However, with the development of semiconductor device manufacturing technology, the die size gradually decreases, and thus the resistance area decreases gradually. As described above, the same concentration of the source / drain regions and the resistance portions of the NMOS transistors can be obtained. When performing the impurity injection process, there is a limit to satisfying the characteristics of each region.

Accordingly, as the size of the semiconductor element is reduced, the source / drain regions of the NMOS transistor portion and the resistance portion of the NMOS transistor portion as described above cannot be secured, thereby limiting the design of the semiconductor element and causing malfunction of the semiconductor element.

Accordingly, the present inventors have actively researched and developed a semiconductor device manufacturing method capable of forming a source / drain region and a resistor of an NMOS transistor to overcome the above-mentioned problems without developing expensive equipment and to perform stable operation. The present invention has been completed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional transistor formation method, and is performed by dividing the impurity implantation process into two stages. An object of the present invention is to provide a method for manufacturing a semiconductor device of concept.

In order to achieve the above object, in the present invention

Forming a word line pattern on the NMOS transistor portion of the semiconductor substrate;

Forming a first photoresist pattern having a source / drain region of an NMOS transistor and an opening of a resistor on an entire surface of the resultant material;

Performing a first impurity implantation process on a semiconductor substrate using the first photoresist pattern;

Forming a second photoresist pattern in which a source / drain region of an NMOS transistor portion is opened on the resultant product; And

It provides a method for manufacturing a semiconductor device comprising the step of performing a second impurity implantation process on the semiconductor substrate using the second photoresist pattern.

In this case, the first impurity implantation process may secure the characteristics of the resistor unit, and the second impurity implantation process may secure the characteristics of the source / drain regions of the NMOS transistor.

Hereinafter, the present invention will be described in detail with reference to the drawings.

First, referring to FIG. 2A, a word line pattern 23 is formed on an NMOS transistor portion a ′ of a semiconductor substrate 21 having an isolation region (not shown). Not shown).

The word line pattern has a structure in which a polycrystalline poly layer (not shown), a conductor layer (not shown), and a hard mask nitride film (not shown) are sequentially stacked.

Exposing and developing the photoresist layer (not shown) to form a first photoresist pattern 23 having the source / drain regions of the NMOS transistor portion a 'and the resistor portion b' opened; A first impurity implantation mask 27 having a source / drain region of the NMOS transistor portion a 'and a resistor portion b opened is formed thereon. When the first impurity implantation process 29 is performed using the first photoresist pattern 23 and the first impurity implantation mask 27, a first impurity region 31 is formed.

In this case, the first impurity injection process 29 is performed by appropriately adjusting the amount of dose to secure the resistance value by using arsenic or phosphorus (phosphorous) thereof, preferably 3E15 dose. Amount is carried out.

Subsequently, the first impurity injection mask 27 and the first photoresist pattern 25 are removed from the resultant of FIG. 2A. In this case, the first photoresist pattern is removed by a general developing method.

Next, referring to FIG. 2B, a second photoresist pattern 33 and a second impurity injection mask 37 in which only the source / drain regions of the NMOS transistor portion a ′ are opened are formed on the resultant product. When the second impurity implantation process 39 is performed using the second photoresist pattern 33 and the second impurity implantation mask 37, the second impurity implantation is performed only in the source / drain regions of the MOS transistor portion a '. Region 41 is formed.

In this case, the second impurity injection process 39 is performed in a 1E15 dose amount.

By such a two-step impurity implantation process, a resistance value that satisfies the characteristics of the source / drain regions of the NMOS transistor portion can be secured.

Next, referring to FIG. 2C, the second impurity implantation mask 37 and the second photoresist pattern 33 are removed from the resultant product.

The source / drain regions of the NMOS transistor portion a 'on which the first impurity region 31 and the second impurity region 41 are formed by the above method are the resistance portions b' on which the first impurity region 31 is formed. Since the resistance value is lower, the individual characteristics of the NMOS transistor portion a 'and the resistor portion b' can be ensured.

In addition to the NMOS, the method can be used to form source / drain regions and resistor portions of PMOS transistors.

As described above, in the present invention, since individual characteristics of the source / drain regions and the resistor of the NMOS transistor can be secured, malfunction of the semiconductor device can be improved.

As described above, the impurity implantation process for the source / drain region and the resistor portion of the NMOS transistor can be performed in two stages to secure individual characteristics of the source / drain region and the resistor portion of the NMOS transistor. Malfunction can be improved.

Claims (5)

Forming a word line pattern on an NMOS transistor portion of a semiconductor substrate; Forming a first photoresist pattern having a source / drain region of an NMOS transistor and an opening of a resistor on an entire surface of the resultant material; Performing a first impurity implantation process on the semiconductor substrate using the first photoresist pattern; Forming a second photoresist pattern in which a source / drain region of an NMOS transistor portion is opened on the resultant product; And And performing a second impurity implantation process on the semiconductor substrate using the second photoresist pattern. The method of claim 1, The first impurity implantation process is a semiconductor device manufacturing method, characterized in that performed in 3E15 dose amount using arsenic. The method of claim 1, The second impurity implantation process is a semiconductor device manufacturing method characterized in that is carried out in a 1E15 dose amount using arsenic. The method of claim 1, The first and second impurity implantation process is a method of manufacturing a semiconductor device, characterized in that carried out using phosphorous (phosphorous) A semiconductor device manufactured by the method of claim 1.

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