KR100672172B1 - Programming method of flash memory device for improving program speed of the flash memory device using incremental step pulse programming - Google Patents

Abstract

The present invention relates to a method of programming a flash memory device using an ISPP method for improving a program speed. The method of programming a flash memory device using an ISPP method according to the present invention sets an initial program voltage to increase the number of program steps. Since a soft erase operation is performed on the overprogrammed cell after the program operation is reduced, the overall program speed can be improved and the disturb characteristic can be improved.

Over program, erase, verify voltage, erase bias voltage

Description

Programming method of flash memory device for improving program speed of the flash memory device using incremental step pulse programming}

1 is a flowchart illustrating a programming process using a conventional incremental step pulse programming (ISPP) method.

FIG. 2 is a diagram illustrating a change in voltage level of a word line of a page selected according to the program process illustrated in FIG. 1.

3 is a flowchart illustrating a program process using an ISPP scheme according to an embodiment of the present invention.

4 is a flowchart illustrating an erase process of over programmed memory cells illustrated in FIG. 3.

5 is a diagram schematically illustrating a flash memory device to which a program method using an ISPP method according to the present invention is applied.

6 is a graph illustrating threshold voltage distribution of memory cells according to a program process using an ISPP scheme according to the present invention.

7 is a flowchart illustrating a program process using an ISPP scheme according to another embodiment of the present invention.

8 is a flowchart illustrating an erase process of memory cells illustrated in FIG. 7.

<Explanation of symbols for main parts of drawing>

51: memory cell block 52: page buffer circuit

The present invention relates to a method of programming a flash memory device, and more particularly, to a method of programming a flash memory device using an incremental step pulse programming (ISPP) method.

In general, a flash memory device performs a program operation, an erase operation, and a read operation. The program operation of the flash memory device is executed in units of pages. As the word line bias voltage for the program is applied to the word line to which the memory cells of the selected page are connected, the memory cells are programmed. Recently, in order to improve the threshold voltage distribution of memory cells during programming, a program method using the ISPP method of programming the selected page several times while gradually increasing the word line bias voltage by a set step voltage unit has been implemented. Referring to Figures 1 and 2, briefly described a program process using a conventional ISPP method as follows. 1 is a flowchart illustrating a program process using a conventional ISPP scheme, and FIG. 2 is a diagram illustrating a change in voltage level of a word line of a page selected according to the program process illustrated in FIG. 1. As shown in FIGS. 1 and 2, in the program process using the conventional ISPP method, the program voltage is converted to the step voltage (K) for each step Dp1, Dp2, Dp3,..., DpK (K is an integer). The program operation proceeds in increments of Vs). After each of the program steps Dp1, Dp2, Dp3, ..., DpK, the verification steps Dv1, Dv2, Dv3, ..., DvK proceed respectively. In the verification steps Dv1, Dv2, Dv3,..., DvK, whether the memory cells are programmed is verified. As described above, in the conventional program process, the program step and the verify step are repeatedly executed until the program of all the memory cells is completed. Therefore, conventionally, there is a problem that the overall program time is increased. In addition, as the program process is repeatedly executed, a disturb phenomenon in which memory cells that should not be programmed are programmed increases, so that the disturb characteristic of the flash memory device is degraded. In order to prevent this, a method of reducing the program time of the flash memory device and improving the disturb characteristic by increasing the magnitude of the step voltage Vs has been applied. However, as the flash memory device is highly integrated, when the threshold voltage distribution of the memory cell is determined, there is a problem in that the program time can no longer be improved by the ISPP method.

Accordingly, the technical problem to be achieved by the present invention is to set the initial program voltage to a high value, reduce the number of program steps, and execute the soft erase operation on the overprogrammed cell after the program operation, thereby improving the overall program speed. The present invention provides a method for programming a flash memory device using an ISPP method.

Program method of a flash memory device using an ISPP method according to an aspect of the present invention for achieving the above technical problem, setting a program voltage; Inputting data into the page buffer circuit; Selecting a page to be programmed among a plurality of pages of the memory cell block; Supplying the program voltage to program memory cells of the selected page; Supplying a first verify voltage to a word line of the selected page to verify the memory cells and to detect over programmed memory cells according to the verify result; And performing an erase operation on the over programmed memory cells until the threshold voltage of the over programmed memory cells becomes a set voltage. Preferably, the set voltage is equal to the threshold voltage of a normally programmed memory cell.

According to another aspect of the present invention, there is provided a program method of a flash memory device using an ISPP method, the method including: setting a program voltage; Inputting data into the page buffer circuit; Selecting a page to be programmed among a plurality of pages of the memory cell block; Supplying the program voltage to program memory cells of the selected page; And performing an erase operation on the memory cells of the selected page.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be embodied in various other forms, and only the embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to inform you completely.

3 is a flowchart illustrating a program process using an ISPP scheme according to an embodiment of the present invention. Referring to FIG. 3, first, a program voltage supplied during a program operation to be started first is set (101). Preferably, in step 101, the program voltage may be set to a voltage high enough (e.g., 18V) for the memory cells to be programmed for one program cycle. As such, when the initial program voltage is set high, the memory cells may complete the program only by passing through one or two program cycles. Thereafter, the data DI to be programmed is input to the page buffer circuit 52 (see FIG. 5). Further, a page (for example, P2) to be programmed is selected from among the plurality of pages P1 to PN (N is an integer) of the memory cell block 51 (see FIG. 5) (103).

Next, as the program voltage VPGM is supplied to the word line WL2 of the selected page P2, the memory cells C1 to CM of the selected page P2 are programmed 104. Thereafter, a verification voltage PV1 (see FIG. 6) is supplied to the word line WL2 to verify the memory cells C1 to CM (105), and the memory cells C1 to CM according to the verification result. It is determined whether or not the program is completed. Here, the verification voltage PV1 may be set to be larger than a threshold voltage of unprogrammed cells and smaller than a threshold voltage of a programmed cell, as referenced in FIG. 6. As a result of the determination of step 106, if the programming of the memory cells C1 to CM is not completed, the program voltage VPGM is increased by a step voltage, and then the steps 104 to 106 are repeated. Is executed.

Thereafter, a verification voltage PV2 (see FIG. 6) is supplied to the word line WL2 of the selected page P2 to verify the memory cells C1 to CM (108) and over according to the verification result. It is determined whether programmed memory cells exist (109). As a result of the determination of step 109, when the over programmed memory cells exist, the over program until the threshold voltage of the over programmed memory cells becomes a set voltage (that is, the threshold voltage of normally programmed memory cells). An erase operation is performed on the memory cells in operation 110. Referring to FIG. 4, the step 110 will be described in more detail as follows. First, an erase bias voltage VB is supplied to the word line WL2 of the selected page P2 (111). Preferably, the erase bias voltage VB may be set to the verification voltage PV2 (for example, 1V) or a negative voltage (for example, −1V to −2V). In addition, the erase bias voltage VB may be set higher than a threshold voltage of a normally programmed memory cell and smaller than a threshold voltage of an over programmed memory cell.

In addition, the pass voltage VPASS is supplied to the word lines WL1 and WL3 to WLN of the non-selected pages P1 and P3 to PN (112). Preferably, the pass voltage VPASS may be set to a voltage high enough to turn on the memory cells C1 to CM of the non-selected pages P1 and P3 to PN (eg, 9.5 V). have. In an embodiment, the pass voltage may be applied to the word line WL1 disposed between the word line WL2 and the drain select line DSL of the selected page P2 among the word lines WL1 and WL3 to WLN. VPASS may be supplied, and a ground voltage may be supplied to the word lines WL3 to WLN disposed between the word line WL2 and the source select line SSL.

In addition, the erase prohibition voltage VEH is supplied to the bit lines BL2 to BLM to which the remaining memory cells C2 to CM are connected except for the over programmed memory cell (s) (for example, C1). ). Preferably, the erase prohibition voltage VEH may be set to an internal voltage VCC. As the erase voltage VE is supplied to the bit line BL1 to which the over programmed memory cell C1 is connected, the over programmed memory cell C1 is erased (114). Preferably, the erase voltage VE may be set to a high voltage (eg, 18V) higher than the internal voltage VCC.

 In this case, when the erase bias voltage VB is set to the verify voltage V2, since the memory cell C1 is over programmed, the memory cell C1 is turned off, and the memory cells C2 to CM are normally programmed. do. As a result, a voltage difference occurs only between the gate and the drain of the memory cell C1, so that the memory cell C1 is softly erased. In more detail, as the erase of the memory cell C1 proceeds, the threshold voltage of the memory cell C1 gradually decreases and becomes a set voltage (that is, a threshold voltage of a normally programmed cell). When the memory cell C1 is turned on. Therefore, since the current caused by the erase voltage VE applied to the bit line BL1 flows to the ground through the common source line CSL as the memory cell C1 is turned on, the memory cell C1. ) Is not excessively erased. Meanwhile, when the erase bias voltage VB is set to the negative voltage, all of the memory cells C1 to CM are turned off. However, since the erase prohibition voltage VEH is supplied to the bit lines BL2 to BLM, the memory cells C2 to CM are not erased. Since the erase voltage VE is supplied to the bit line BL1, a voltage difference occurs only between the gate and the drain of the memory cell C1, and only the memory cell C1 is erased. In this case, in order to prevent excessive erasing of the memory cell C1, an erase operation of the memory cell C1 may be performed only for a predetermined time.

Next, the program process using the ISPP method according to another embodiment of the present invention will be described in detail with reference to FIGS. 7 and 8. In FIG. 7, the steps 201 to 207 are substantially the same as the steps 101 to 107 described above with reference to FIG. 3, and thus a detailed description thereof will be omitted. As the steps 201 to 207 progress, when the program of the memory cells C1 to CM of the selected page P2 is completed, the threshold voltages of the memory cells C1 to CM of the selected page P2 are completed. The erase operation is performed on the memory cells C1 to CM until the set voltage (that is, the threshold voltage of the normally programmed memory cells) becomes 208. Referring to FIG. 8, the step 208 will be described in more detail as follows. In FIG. 8, since the steps 211 and 212 are substantially similar to the steps 111 and 112 described above with reference to FIG. 4, a detailed description thereof will be omitted. In the step 111, however, the erase bias voltage VB is set to the verification voltage V2 or a negative voltage. In the step 211, the erase bias voltage VB is not a negative voltage. There is a difference that is set only to the verification voltage PV2 (that is, a voltage larger than a threshold voltage of a normally programmed memory cell and smaller than a threshold voltage of an over programmed memory cell). Subsequently, as the erase voltage VE is supplied to the bit lines BL1 to BLM to which the memory cells C1 to CM of the selected page P2 are connected, over-programmed among the memory cells C1 to CM. Memory cells (eg, C1 and C2) are erased (213). In more detail, when the erase bias voltage VB is supplied to the word line WL2, since the memory cells C1 and C2 are over programmed, the memory cells C3 to CM are turned off. ) Is normally programmed, so it is turned on. As a result, a voltage difference occurs only between the gate and the drain of each of the memory cells C1 and C2, so that the memory cells C1 and C2 are softly erased. In more detail, as the erase of the memory cells C1 and C2 proceeds, the threshold voltages of the memory cells C1 and C2 gradually decrease, and the set voltage (that is, the threshold of a normally programmed cell) is reduced. Voltage), the memory cells C1 and C2 are turned on. Therefore, the current by the erase voltage VE applied to the bit lines BL1 and BL2 flows to the ground through the common source line CSL as the memory cells C1 and C2 are turned on. Excessive erase of the memory cells C1 and C2 is not performed.

As described above, the program method of the flash memory device using the ISPP method according to the present invention program the memory cells by setting the initial program voltage high enough, and then soft erase the over-programmed cells, so that the overall program time This can be reduced. In addition, since only a few program cycles are executed, the disturb characteristics of the memory cells can be improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, in the program method of the flash memory device according to the present invention, the initial program voltage is set high, the number of program steps is reduced, and after the program operation, the soft erase operation is performed on the overprogrammed cell. Program speed can be improved, and disturb characteristics can be improved.

Claims (13)

In the flash memory device program method using the ISPP method, Setting a program voltage; Inputting data into the page buffer circuit; Selecting a page to be programmed among a plurality of pages of the memory cell block; Supplying the program voltage to program memory cells of the selected page; Supplying a first verify voltage to a word line of the selected page to verify the memory cells and to detect over programmed memory cells according to the verify result; And Performing an erase operation on the over programmed memory cells until the threshold voltage of the over programmed memory cells becomes a set voltage; And the set voltage is equal to a threshold voltage of a normally programmed memory cell. The method of claim 1, wherein the program step, Supplying the program voltage to a word line of the selected page such that memory cells of the selected page are programmed; Supplying a second verify voltage to the word line, verifying the memory cells, and determining whether to program the memory cells according to the verify result; And If the program of the memory cells is not completed, increasing the program voltage by a step voltage, and then repeatedly executing the program voltage supplying step and the determining step, And the first verify voltage is greater than the second verify voltage. The method of claim 1, wherein performing the erase operation comprises: Supplying an erase bias voltage to a word line of the selected page; Supplying pass voltage to word lines of unselected pages; Supplying an erase inhibit voltage to bit lines to which remaining memory cells except the over programmed memory cells are connected; And And erasing the over programmed memory cells by supplying an erase voltage to bit lines to which the over programmed memory cells are connected. The method of claim 3, The erase bias voltage is greater than a threshold voltage of a programmed memory cell and less than a threshold voltage of the over programmed memory cell. The method of claim 3, And the erase prohibition voltage is an internal voltage, the erase voltage is greater than the erase prohibition voltage, and the pass voltage is greater than the erase bias voltage. The method of claim 3, The erase bias voltage is a negative voltage programming method of a flash memory device. The method of claim 3, wherein supplying the pass voltage comprises: Supplying the pass voltage to word lines of the non-selected page disposed between the word line of the selected page and the drain select line of the word lines of the non-selected pages; And And supplying a ground voltage to word lines of the unselected page disposed between a word line of the selected page and a source select line among the word lines of the unselected pages. In the flash memory device program method using the ISPP method, Setting a program voltage; Inputting data into the page buffer circuit; Selecting a page to be programmed among a plurality of pages of the memory cell block; Supplying the program voltage to program memory cells of the selected page; And And performing an erase operation on the memory cells of the selected page. The method of claim 8, wherein the program step, Supplying the program voltage to a word line of the selected page such that memory cells of the selected page are programmed; Supplying a verification voltage to the word line, verifying the memory cells, and determining whether to program the memory cells according to the verification result; And If the program of the memory cells is not completed, increasing the program voltage by a step voltage, and then repeatedly executing the program voltage supplying step and the determining step. The method of claim 8, wherein performing the erase operation comprises: Supplying an erase bias voltage to a word line of the selected page; Supplying pass voltage to word lines of unselected pages; And Supplying an erase voltage to the bit lines to which the memory cells of the selected page are connected to erase the memory cells of the selected page until the threshold voltage of the over programmed memory cells among the memory cells of the selected page becomes a set voltage. Including steps And the set voltage is equal to a threshold voltage of a normally programmed memory cell. The method of claim 8, The erase bias voltage is greater than a threshold voltage of a programmed memory cell and less than a threshold voltage of the over programmed memory cell. The method of claim 8, And the erase voltage is greater than an internal voltage and the pass voltage is greater than the erase bias voltage. The method of claim 10, wherein supplying the pass voltage comprises: Supplying the pass voltage to word lines of the non-selected page disposed between the word line of the selected page and the drain select line of the word lines of the non-selected pages; And And supplying a ground voltage to word lines of the unselected page disposed between a word line of the selected page and a source select line among the word lines of the unselected pages.

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