KR100670247B1 - Plasma display panel - Google Patents

Abstract

According to the present invention, an upper substrate and a lower substrate disposed to face the upper substrate; A first partition wall disposed between the upper substrate and the lower substrate and formed of a dielectric; A second partition formed on the lower substrate corresponding to the first partition and defining a discharge cell together with the upper substrate, the lower substrate, and the first partition; Upper discharge electrodes disposed in the first partition wall to surround the discharge cell; Lower discharge electrodes disposed in the first partition wall to surround the discharge cells and spaced apart from the upper discharge electrodes; A phosphor layer disposed in the discharge cell; A discharge gas filled in the discharge cell; A dielectric wall formed on the outermost side of the first partition wall at an inner surface of the upper substrate; And a frit formed on the inner surface of the lower substrate to overlap the dielectric wall to bond the upper substrate and the lower substrate to each other.

Description

Plasma display panel {Plasma display panel}

1 is a schematic exploded perspective view of a plasma display panel according to a conventional example.

FIG. 2 is a schematic cross-sectional view of the plasma display panel of the prior art shown in FIG.

FIG. 3 is a schematic plan view of the plasma display panel shown in FIG. 2.

4 is a schematic exploded perspective view of a plasma display panel according to the present invention.

5 is a schematic cross-sectional view of a plasma display panel according to the present invention.

FIG. 6 is a plan view of the plasma display panel shown in FIG. 4.

<Brief description of the major symbols in the drawings>

111. Upper substrate 112. First bulkhead

113. Top discharge electrode 114. Bottom discharge electrode

115. Discharge cell 121. Lower substrate

122. Address electrode 123 Dielectric layer

124. Second bulkhead 153. Frit

154. Dielectric wall 600. Light emitting display area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel in which mutual bonding of an upper substrate and a lower substrate is performed by cooperation of a dielectric wall and a frit.

The device employing the plasma display panel has a large screen, high quality, ultra-thin, light weight, and excellent characteristics of wide viewing angle, and is simpler to manufacture than other flat panel display devices and is easy to be enlarged. It has been in the spotlight as a flat panel display device.

The plasma display panel is classified into a direct current (DC) type, an alternating current (AC) type, and a hybrid type according to an applied discharge voltage, and may be classified into a counter discharge type and a surface discharge type according to a discharge structure. In general, an AC plasma display panel having an AC three-electrode surface discharge structure is generally employed.

1 shows a conventional AC three-electrode surface discharge plasma display panel.

The illustrated plasma display panel 10 is provided with an upper substrate 11 and a lower substrate 21 opposite thereto.

On the lower surface of the upper substrate 11, a pair of sustain electrodes 12 formed of a pair of a common electrode 13 and a scan electrode 14 forming a discharge gap with the common electrode 13 is formed. 13 and the scan electrodes 14 are embedded by the upper dielectric layer 15. A protective layer 16 is formed on the lower surface of the upper dielectric layer 15.

The address electrodes 22 are formed on the upper surface of the lower substrate 21 to cross the common electrodes 13 and the scan electrodes 14, and the address electrodes 22 are formed by the lower dielectric layer 23. Buried Discharge cells 25 are partitioned on the upper surface of the lower dielectric layer 23 by forming partition walls 24 spaced apart at predetermined intervals. Phosphor layers 26 are formed in the discharge cells 25, and discharge gas is filled in the discharge cells 25.

In the plasma display panel 10 configured as described above, the discharge cells 25 emit ultraviolet rays from the plasma generated by the discharge. Such ultraviolet rays excite the phosphor layer 26, and visible light is emitted from the phosphor layer 26 thus excited, thereby displaying an image.

2 is a schematic cross-sectional view of the plasma display panel shown in FIG. 1.

Referring to FIG. 2, the outermost discharge cells 27 are disposed at the outermost sides of the discharge cells 25 coated with the phosphors 26, and the dummy discharge cells 29 are disposed outside the outermost discharge cells 27. ) Is formed. The dummy discharge cell 29 is a space formed between the outermost partition wall 24a and the dummy partition wall 25. Since the phosphor is not coated, actual discharge does not occur. On the other hand, the frit 28 is disposed outside the dummy partition 25 so that the upper substrate 11 and the lower substrate 21 are bonded to each other.

3 is a plan view of the plasma display panel.

Referring to the drawings, the reference numeral 31 denotes a light emitting display area, which corresponds to a region in which the phosphor layer 26 is formed between the partition walls 24 and 24a in FIG. 2. The light emitting display area 31 is an area where a screen is displayed when the panel is driven. The dummy cell area 31 is formed outside the light emitting display area 31, which is an area formed between the outermost partition wall 24a and the dummy partition wall 25 in FIG. That is not an area. On the other hand, the frit 28 is applied to the edge of the dummy cell region 31 so that the upper substrate 11 and the lower substrate 21 are bonded to each other.

The bonding structure by frit 28 shown in Figs. 2 and 3 has a problem that it is quite difficult to make the application state uniform when the frit is applied to the surface along the edge of the substrate. That is, when the frit is applied to the surface of the substrate, the frit spreads due to its fluidity, and such spreading makes it difficult to keep the gap between the substrates constant. Therefore, there is a problem that panel noise is easily generated due to nonuniformity of the gap between the substrates when the plasma display panel is driven. In particular, when the gap between the upper and lower substrates 11 and 21 is widened, the bonding using frit causes many problems.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a plasma display panel having an improved bonding structure.

Another object of the present invention is to provide a plasma display panel which can achieve uniformity and noise reduction of frit coating.

In order to achieve the above object, according to the present invention,

An upper substrate and a lower substrate disposed to face the upper substrate;

A first partition wall disposed between the upper substrate and the lower substrate and formed of a dielectric;

A second partition formed on the lower substrate corresponding to the first partition and defining a discharge cell together with the upper substrate, the lower substrate, and the first partition;

Upper discharge electrodes disposed in the first partition wall to surround the discharge cell;

Lower discharge electrodes disposed in the first partition wall to surround the discharge cells and spaced apart from the upper discharge electrodes;

A phosphor layer disposed in the discharge cell;

A discharge gas filled in the discharge cell;

A dielectric wall formed on the outermost side of the first partition wall at an inner surface of the upper substrate;

And a frit formed on the inner surface of the lower substrate to overlap the dielectric wall to bond the upper substrate and the lower substrate to each other.

According to an aspect of the present invention, a first dummy partition wall formed on an inner surface of the upper substrate between the outermost side of the first partition wall and the dielectric wall and an inner surface of the lower substrate corresponding to the first dummy partition wall. And a second dummy partition wall formed thereon.

According to another feature of the invention, the height of the dielectric wall is substantially the same as the height of the first partition wall.

According to another feature of the present invention, an address electrode extending between the second partition walls is further provided on an inner surface of the lower substrate.

According to another feature of the invention, the address electrodes are covered by a dielectric layer further provided between the lower substrate and the phosphor layer.

Hereinafter, with reference to the preferred embodiment shown in the accompanying drawings the present invention will be described in more detail.

4 is a schematic exploded perspective view of the plasma display panel according to the present invention.

Referring to the drawing, the plasma display panel 100 includes an upper substrate 111 and a lower substrate 121 disposed to face the upper substrate 111. The upper substrate 111 and the lower substrate 121 are formed of a light transmissive material such as glass. In particular, since the image is displayed from the upper substrate 111, the upper substrate 111 preferably has excellent light transmittance. In addition, between the upper substrate 111 and the lower substrate 121, a first partition 112 and a second partition 124 are formed in a predetermined pattern and disposed up and down.

In the illustrated example, a cross-section of the first partition 112 and the second partition 124 has a rectangular closed partition in the form of a matrix. A lower surface of the first partition wall 112 corresponds to an upper surface of the second partition wall 124 and corresponds to a space defined by the first partition wall 112 and a space defined by the second partition wall 124, respectively.

In another example not shown in the drawings, the first and second bulkheads may be formed of a closed partition such as a waffle or a delta, or a cross section may be a polygon such as a triangle or a pentagon, or a closed partition such as a circle or an oval. Can be formed. In addition, the first partition may be formed as a closed partition, while the second partition may be formed in various combinations, such as formed as an open partition in the form of a stripe.

The first and second partition walls 112 and 124, together with the upper and lower substrates 111 and 121, have a red subpixel, a green subpixel, and a blue sub, constituting a unit pixel for color implementation. Among the pixels, each cell is divided into discharge cells 115 corresponding to one subpixel. The barrier ribs prevent erroneous discharge due to cross talk or the like between the divided discharge cells 115. As illustrated, the first and second partition walls 112 and 124 may be separately formed and assembled with each other, or the first and second partition walls may be integrally formed of the same material.

Meanwhile, address electrodes 122 are formed on an inner surface of the lower substrate 121, and the address electrodes 122 are covered by the dielectric layer 123. The address electrodes 122 are formed to correspond to the discharge cells 115 so as to select the discharge cells 115 to start discharge. Although the address electrodes 122 are illustrated as being formed in a stripe shape, the address electrodes 122 may be formed in other forms.

The dielectric layer 123 may prevent the positive electrode or the electrons from colliding with the address electrodes 122 when being discharged, thereby damaging the address electrodes 122 and inducing charge. The dielectric layer 123 may be formed of a dielectric such as PbO, B 2 O 3, SiO 2, Al 2 O 3, or the like.

The discharge cell 115 is formed with a phosphor layer 125 that is excited by ultraviolet light generated during sustain discharge to generate visible light. The phosphor layer 125 is formed over a space defined by the second partition wall 124, that is, the upper surface of the dielectric layer 123 and the side surfaces of the second partition wall 124. The phosphor layer 125 includes phosphors that are excited by ultraviolet rays generated during discharge to generate red, green, and blue visible light, respectively. For example, the red phosphor layer formed in the discharge cell corresponding to the red subpixel includes phosphors such as Y (V, P) O4: Eu, and the green phosphor layer formed in the discharge cell corresponding to the green subpixel is Zn2SiO4: The phosphor includes Mn, YBO3: Tb, and the like, and the blue phosphor layer formed in the discharge cell corresponding to the blue subpixel includes phosphors such as BAM: Eu.

Since the phosphor layer 125 is formed in the space defined by the second partition 124, the phosphor layer 125 is significantly spaced apart from the main region on the side of the first partition 112 where the sustain discharge occurs. Accordingly, the phosphor layer 125 may be prevented from being ion-sputtered by the charged particles, thereby improving lifespan characteristics, and even after the same image is implemented for a long time, the phenomenon of permanent afterimage generation may be significantly reduced.

A discharge gas is filled in the discharge cell 115. As the discharge gas, a conventional mixed gas including Xe for generating ultraviolet rays and Ne, which serves as a buffer, may be employed.

Meanwhile, in the first partition 112 that partitions the discharge cell 115 together with the second partition 124 as described above, the upper discharge electrodes 113 and the lower side which cause discharge in the discharge cells 115 are lowered. Discharge electrodes 114 are formed so as to be arranged up and down respectively. The upper discharge electrode 113 is disposed above the upper substrate 111 side, and the lower discharge electrode 114 is disposed below the upper discharge electrode 113 in the vertical direction. . The upper discharge electrode 113 and the lower discharge electrode 114 may be formed of a conductive metal such as aluminum, copper, silver, or the like.

The upper discharge electrode 113 and the lower discharge electrode 114 may be formed in, for example, a trapezoid, and may extend in a direction parallel to each other or in a direction perpendicular to each other. In the case of extending in parallel to each other, the upper discharge electrode 113 and the lower discharge electrode 114 may be used only for sustain discharge. In this case, the address electrode 122 is required for the address discharge. However, those skilled in the art will understand that when the upper discharge electrode 113 and the lower discharge electrode 114 extend in a direction orthogonal to each other, address discharge is possible without the address electrode 122.

The first partition wall 112 filling the upper discharge electrodes 113 and the lower discharge electrodes 114 is formed of a dielectric material, and thus prevents direct current from flowing between the upper discharge electrode 113 and the lower discharge electrode 114. Can be. In addition, it is possible to prevent the charged particles from directly colliding with the upper discharge electrode 113 and the lower discharge electrode 114 to damage the electrodes during discharge, and to easily accumulate the wall charges by inducing the charged particles. PbO, B 2 O 3, SiO 2, Al 2 O 3, or the like may be used as the dielectric for forming the first partition wall 112.

In addition, an MgO layer 116 having a predetermined thickness may be further formed on a side surface of the first partition wall 112. As the MgO film 116 is formed as described above, the collision of the charged particles generated during discharge directly with the first partition wall 112 may be blocked by the MgO film 116, and thus, by ion sputtering of the charged particles. Damage to the first partition wall 112 may be prevented. In addition, as the charged particles directly collide with the MgO film 116 as described above, secondary electrons that contribute to the discharge may be emitted from the MgO film 116, thereby enabling low voltage driving and emitting efficiency. This can be high.

5 is a schematic cross-sectional view of the plasma display panel according to the present invention.

Referring to the drawing, the first and second barrier ribs 112 and 124 are formed to correspond to each other between the upper substrate 111 and the lower substrate 121 to form a discharge cell 115. The first dummy partition wall 151 and the second dummy partition wall 152 are formed outside the outermost first partition wall 112a and the second partition wall 124a. The first dummy partition wall 151 and the second dummy partition wall 152 are substantially the same as the first partition wall 112 and the second partition wall 124 in terms of shape, material, and the like. For example, the first dummy partition wall 151 is formed of a dielectric similar to the first partition wall 112, and the second dummy partition wall 152 is also formed of the same material as the material for forming the second partition wall 124. The first dummy partition wall 151 and the second dummy partition wall 152 form a dummy cell region 149 together with the outermost first partition wall 112a and the outermost second partition wall 124a. In the dummy cell region 149, the light emitting display action does not occur.

According to one feature of the present invention, a dielectric wall 154 is formed on the inner surface of the upper substrate 111 to bond the upper substrate 111 and the lower substrate 112 to each other, and the dielectric wall 154 Correspondingly, the frit 153 is coated on the inner surface of the lower substrate 121. The frit 153 is bonded to the bottom surface of the dielectric wall 154 so that the upper substrate 111 and the lower substrate 112 can be bonded to each other.

The dielectric wall 154 may be formed of the same material as the dielectric material forming the first partition 112. The height of the dielectric wall 154 is preferably formed to be substantially the same as the height of the first partition wall 112. By forming the dielectric wall 154, uniformity may be ensured in the process of applying the frit 153. That is, since the frit 153 is disposed between the bottom surface of the dielectric wall 154 and the inner surface of the lower substrate 121, the frit thickness may be applied to a smaller thickness than the case where the dielectric wall 154 is not provided. Therefore, even if the phenomenon in which the frit 153 spreads due to the fluidity of the frit 153 occurs, the degree of spreading is relatively small, so that uniform application is possible. The thickness of the frit 153 is preferably formed to be equal to the height of the second partition wall 124.

6 is a plan view of the plasma display panel according to the present invention.

Referring to the drawings, most of the central portion of the upper substrate 111 corresponds to the light emitting display unit 600, the screen display operation occurs by the light emitting action of the phosphor layer in the light emitting display unit 600. The light emitting display unit 600 is a region defined by the outermost first partition 112a and the outermost second partition 124a in FIG. 5 and includes partitions on which the phosphor layer 125 is formed.

Meanwhile, the dummy cell region 610 is surrounded by the outer side of the light emitting display unit 600, and the dummy cell region 610 is the outermost first partition 112a and the outermost second partition 124a in FIG. 5. And a space defined by the first dummy partition wall 151 and the second dummy partition wall 152. The frit coating part 620 is formed to surround the outside of the dummy cell region 610, and a dielectric wall (154 of FIG. 5) is formed on an inner surface of the upper substrate 111 in the frit coating part 620. On the inner surface of the lower substrate 121, the frits 153 are formed to overlap each other.

Referring to the operation of the plasma display panel 100 configured as described above is as follows.

First, an address voltage is applied between an address electrode 122 and a lower discharge electrode 114 acting as a scan electrode, so that an address discharge occurs, and as a result of the address discharge, a discharge cell 115 to generate a sustain discharge is selected. Lose. After the address discharge is executed, if the sustain discharge voltage is alternately applied between the upper discharge electrode 113 and the lower discharge electrode 114 disposed in the selected discharge cell 115, the upper discharge electrode 113 and the lower discharge are applied. A sustain discharge occurs between the electrodes 114.

The sustain discharge is concentrated on the upper side of the discharge cell 115, and occurs in the vertical direction on all sides defining the discharge cell 115. As described above, the sustain discharge generated from all sides of the discharge cell 115 is gradually diffused to the center side of the discharge cell 115. Therefore, the discharge area becomes relatively wider than that of the conventional panel shown in FIG. 1, and the volume of the area where the sustain discharge occurs is increased, so that the space charge in the discharge cell 115, which has not been used conventionally, also contributes to light emission. do. Accordingly, the amount of plasma to be formed during discharge can be increased to enable low voltage driving. Ultraviolet rays are emitted while the energy level to the discharged gas excited by the sustain discharge is lowered. The ultraviolet rays excite the phosphor layer 125 formed in the discharge cell 115, and visible light is emitted from the excited phosphor layer 125 to realize an image.

Plasma display panel according to the present invention forms a dielectric wall on the inner surface of the upper substrate and to apply the frit to correspond to it can prevent the spread of the frit, it is possible to uniformly apply the thickness of the frit. Therefore, the generation of noise due to the uneven distribution of frits at the time of driving the panel can be significantly reduced.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

Claims (5)

An upper substrate and a lower substrate disposed to face the upper substrate; A first partition wall disposed between the upper substrate and the lower substrate and formed of a dielectric; A second partition formed on the lower substrate corresponding to the first partition and defining a discharge cell together with the upper substrate, the lower substrate, and the first partition; Upper discharge electrodes disposed in the first partition wall to surround the discharge cell; Lower discharge electrodes disposed in the first partition wall to surround the discharge cells and spaced apart from the upper discharge electrodes; A phosphor layer disposed in the discharge cell; A discharge gas filled in the discharge cell; A dielectric wall formed on the outermost side of the first partition wall at an inner surface of the upper substrate; And a frit formed on an inner surface of the lower substrate so as to overlap the dielectric wall to bond the upper substrate and the lower substrate to each other. The method of claim 1, A first dummy partition wall formed on an inner surface of the upper substrate between the outermost side of the first partition wall and the dielectric wall; and a second dummy partition wall formed on an inner surface of the lower substrate corresponding to the first dummy partition wall. Plasma display panel characterized in that it further comprises. The method of claim 1, And the height of the dielectric wall is the same as the height of the first partition wall. The method of claim 1, And an address electrode extending between the second partition walls on an inner surface of the lower substrate. The method of claim 4, wherein And the address electrodes are covered by a dielectric layer further provided between the lower substrate and the phosphor layer.

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