KR100656281B1 - Method for gapfilling in semiconductor device using deposition-etch-etch-deposition - Google Patents

Abstract

The present invention is to provide a gap fill method of a semiconductor device capable of preventing damage to the void caused by the insufficient amount of etching during the gap fill process using the DED (Deposition Etch Deposition) method or the lower layer caused by excessive etching amount. According to an embodiment of the present invention, a gap fill method of a semiconductor device may include forming a pattern having a gap on a semiconductor substrate, depositing a first HDP oxide layer on the pattern to partially fill the gap, and covering the first HDP oxide layer twice. Partially etching to leave the first HDP oxide film having a lower height while widening the gap inlet of the gap, and depositing a second HDP oxide film to completely gapfill the gap on the remaining first HDP oxide film, as described above. In the present invention, the gap fill margin of the ED method is insufficient due to the gap fill process using the DEED (Deposition Etch Etch Deposition) method. There is an effect that can be improved gaeppil without voids.

HDP, Gapfill, Void, DED, DEED

Description

Gap fill method of semiconductor device using DD method {METHOD FOR GAPFILLING IN SEMICONDUCTOR DEVICE USING DEPOSITION-ETCH-ETCH-DEPOSITION}             

1A to 1C illustrate a trench filling method using a DED method according to the prior art;

2A to 2E are cross-sectional views illustrating a trench gapfill method of a semiconductor device according to an embodiment of the present invention;

3 is a view quantifying the height, bottom thickness and width of the first HDP USG according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 pad oxide film

23: pad nitride film 24: trench

25 side wall oxide film 26 liner nitride film

27: liner oxide film 28, 28a, 28b: first HDP USG

29: Second HDP USG

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a gap fill method for semiconductor devices.

As semiconductor devices are highly integrated, design rules are becoming smaller. In particular, in the case of filling the trench during the shallow trench isolation (STI) process, which is one of the device isolation processes, the aspect ratio of the trenches is gradually increased due to the smaller CD (critical depth). Various gap-fill methods and materials have been proposed to fill these high aspect ratio trenches.

Generally, materials used for the gapfill include BPSG (Boron Phosphorus Silicate Glass), O ₃ -TEOS USG (Tetra Ethyl Ortho Silicate Undoped Silicate Glass), and high density plasma oxide (HDP oxide). However, BPSG requires a high temperature reflow process of 800 ° C. or higher and is not suitable for gapfilling small trenches due to the large amount of etching during wet etching. In addition, the O ₃ -TEOS USG has a less thermal budget than the BPSG, but the gap fill property is poor and thus cannot be applied to a highly integrated semiconductor device.

In order to solve this problem, a high-density plasma oxide film (hereinafter referred to as 'HDP oxide film') having less heat load and excellent gap fill characteristics has been introduced. In this case, the HDP oxide film is mainly an undoped silicon oxide, that is, HDP USG (High Density Plasma Undoped Silicate Glass).

The HDP USG mainly uses helium-based (He-base) HDP USG, which has a limited gap gap fill. This is because the aspect ratio increases as the cell size decreases and the device isolation height increases.

Trench gap fill method using helium gas is possible up to 4-5: 1 aspect ratio standard, but in the future 80nm class high density device requires aspect ratio of 7: 1 or more, there is a difficulty to reach the gap fill limit.

In addition, helium-based HDP USG has a problem in that an overhang is formed in the trench inlet due to the deposition characteristic, so that the gap fill is incomplete, thereby forming a void.

In order to solve the difficulty of trench gapfill, a DED (Deposition-Etch-Deposition) method using an NF ₃ gas having an etching function has been proposed.

1A to 1C are diagrams illustrating a trench filling method using a DED method according to the prior art.

First, as shown in FIG. 1A, a pad pattern laminated in the order of the pad oxide film 12 and the pad nitride film 13 is formed on the silicon substrate 11, and then the pad nitride film 13 is formed of a silicon as a hard mask. The substrate 11 is etched to a predetermined depth to form the trench 14.

Subsequently, after forming the sidewall oxide film 15 on the bottom and sidewalls of the trench 14, the liner nitride film 16 and the liner oxide film 17 are sequentially deposited on the entire surface.

Next, the first HDP USG 18 is deposited in the high-density plasma equipment to partially fill the trench 14.

As shown in FIG. 1B, the first HDP USG 18 is partially etched by flowing NF ₃ gas which has been used as a cleaning gas to etch the deposited first HDP USG 18 to form a subsequent trench 14. ) Make the shape easy to gap fill. Accordingly, the first HDP USG 18a having a shape that is easy to fill the subsequent trench 14 by the NF ₃ gas remains.

Thereafter, as illustrated in FIG. 1C, the second HDP USG 19 is deposited on the entire surface including the first HDP USG 18a to completely fill the trench 14.

The trench gap fill process (DED HDP USG) using the DED method as described above has an effect of reducing the generation of voids compared to helium-based HDP USG, but it is still inevitable that voids are generated.

Referring to FIGS. 1B and 1C, the prior art has a characteristic of etching only a side surface of the first HDP USG 18 by an intrinsic etching characteristic (chemical etching or isotropic etching) of NF ₃ during an etching process using NF ₃ gas. It is still not able to lower the height of the first HDP USG 18. That is, although the inlet of the trench 14 may be widened from 'W1' to 'W2' after the deposition of the first HDP USG 18, the height of the first HDP USG 18 still maintains the height 'H1' at the time of initial deposition. .

As described above, when the second HDP USG 19 is subsequently deposited in a state in which the height is not reduced, in particular, in the lack of etching amount with a sharp point, the step coverage margin is insufficient so that the void (see 'v' in FIG. 1C) Will occur.

Furthermore, there is a problem in that the degree of void generation is different for each position in the wafer (top, center, bottom), and varies depending on the number of wafers being processed.

In addition, the prior art has a problem that if the etching amount of the first HDP USG is excessively taken to facilitate the gap fill of the second HDP USG, the liner oxide film and the liner nitride film are lost.

As a result, in the prior art, how to set the target to be etched in the DED etching process is a very important variable. However, even if the optimum target is set under the process conditions, the etching process is very unstable, and since the gap gap margin is almost reached in the 80 nm device, voids or loss of the liner oxide film and the liner nitride film cannot be avoided.

The present invention is proposed to solve the above problems of the prior art, a semiconductor that can prevent the damage of the lower layer caused by the void or excessive etching amount caused by the insufficient amount of etching during the gap fill process using the DED method It is an object of the present invention to provide a gap fill method of a device.

The gap fill method of the semiconductor device of the present invention for achieving the above object is a step of forming a pattern having a gap on the semiconductor substrate, by depositing a first HDP oxide film on the pattern to partially fill the gap, the first HDP Partially etching the oxide film twice to leave the first HDP oxide film having a lower height while widening the gap opening of the gap, and depositing a second HDP oxide film to completely gap fill the gap on the remaining first HDP oxide film. Wherein the second etching of the first HDP oxide film comprises first etching the first HDP oxide film to widen an opening of the gap, and lowering the height of the first HDP oxide film. And secondary etching the etched first HDP oxide layer, wherein the primary etching is performed using a gas accompanying chemical etching. And, the second etching is characterized in that it proceeds by mixing the gas accompanying the gas and the chemical etching which involves physical sputtering, and wherein the primary etch using a NF _3, the second etching is NF ₃ and O _It is characterized by using a mixed gas of ₂ .

The gapfill method of the semiconductor device of the present invention may include forming a trench in a semiconductor substrate, depositing a first HDP oxide film on the semiconductor substrate to partially gapfill the trench, and widening the gapfill opening of the trench. Etching the oxide film in-situ first, etching the first in-situ-etched first HDP oxide film in-situ secondly to lower the height of the first HDP oxide film, and on the second-etched first HDP oxide film. And depositing a second HDP oxide layer to completely gap fill the trench, wherein the first in situ etching is performed using NF ₃ as a main gas, and the second in situ etching is NF. _3, characterized in that it proceeds by mixing He and O _2.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

The present invention to be described later proposes a Deposition-Etch-Etch-Deposition (DEED) method in which a gap having a large aspect ratio is gapfilled with HDP USG using a DED method.

As will be described in detail later, the DEED method includes a first HDP USG deposition process, a first in situ etching process using NF ₃ , a second in situ etching process using NF ₃ and O _2, and a second HDP USG deposition process. Here, the first in situ etching process is a chemical etching using the chemical properties of NF ₃ , the second in situ etching process is a chemical etching by NF ₃ and the etching using physical sputtering O ₂ has.

2A to 2E are cross-sectional views illustrating a trench gapfill method of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, after the pad oxide film 22 and the pad nitride film 23 are sequentially formed on the semiconductor substrate 21, the photoresist film is coated, exposed, and developed on the pad nitride film 23 to isolate the device. To form an ISO mask (not shown).                     

Subsequently, the pad nitride film 23 and the pad oxide film 22 are etched using the ISO mask as an etching barrier to expose the surface of the semiconductor substrate 21. Next, after removing the ISO mask, the semiconductor substrate 21 is etched to a predetermined depth using the pad nitride film 23 as a hard mask to form the trench 24.

Next, the sidewall oxidation layer 25 is formed on the bottom and the sidewalls of the trench 24 by performing wall oxidation to remove the damage generated during the etching of the trench 24.

Next, a liner nitride layer 26 and a liner oxide layer 27 are sequentially formed on the entire surface including the trench 24 on which the sidewall oxide layer 25 is formed. At this time, the liner nitride layer 26 is to relieve stress to the semiconductor substrate 21 to improve the refresh characteristics, and the liner oxide layer 27 prevents the liner nitride layer 26 from being oxidized and etched during a subsequent HDP process. It is for.

After deposition to the liner oxide layer 27 as described above, the aspect ratio of the trench 24 becomes 5: 1 or more, and the trench is formed by depositing an oxide film having a high density plasma method (HDP) to fill the trench 24 having such a high aspect ratio. Landfill (24). For example, the semiconductor substrate 21 on which the liner oxide film 27 is formed is transferred to the high density plasma deposition chamber, and then HDP USG filling the trench 24 is deposited. As is well known, in the high density plasma deposition process, sputter etching and oxide deposition are performed simultaneously to provide excellent gap fill characteristics. Therefore, argon (Ar) or helium (He) is used as an inert gas for generating sputter etching, and silane (SiH ₄ ) and oxygen (O ₂ ) gas are used as oxide film deposition gases.

Hereinafter, HDP USG deposition uses a DEED method.

First, the first HDP USG deposition process, which is a first step of the DEED method, is performed.

As shown in FIG. 2B, a first HDP USG 28 is deposited that partially fills the trench 24. In this case, the deposition gas is used by mixing silane (SiH ₄ ), oxygen (O ₂ ) and helium (He), and the first HDP USG within the deposition thickness range where the peaks of the neighboring first HDP USG 28 do not adhere to each other. Use the power to raise the height of (28) as much as possible.

For example, the flow rate of silane (SiH ₄ ) is maintained at 50 sccm-70 sccm, the flow rate of oxygen (O ₂ ) is 70 sccm-90 sccm, and the flow rate of helium (He) is in the range of 400 sccm-600 sccm. In addition to the above-described flow rate of the deposition gas, in order to obtain a low deposition rate of the first HDP USG 28, adjustment of bias power must be accompanied, and the bias power (or high frequency (HF) power) is in the range of 500W to 700W. Applies from On the other hand, source power (or low frequency (LF) power) for plasma generation and maintenance is applied in the range of 3000W to 4000W.

As a result of depositing the first HDP USG 28 under the above conditions, the thickness on the pad nitride layer 23 is 150 nm, and the thickness of the sidewalls over-deposited in the horizontal direction on the sidewalls of the trench 24 is 60 nm, and the bottom thickness raised from the bottom of the trench 24 is 100 nm.                     

However, despite the thin deposition of the first HDP USG 28 to a thickness of 150 nm as described above, the height H11 of the first HDP USG 38 in a subsequent step is small because the effect of reducing the aspect ratio originally possessed by the trench 24 to be gap-filled is small. To reduce and widen the width (W11).

In order to realize the reduction of the height H11 and the width W11 of the first HDP USG 38, an etching process, which is the second step of the DEED method, is performed, but the first in-situ of the two in-situ etching processes is performed. Proceed with the etching process.

As shown in FIG. 2C, the etching process is performed in the same high-density plasma chamber, that is, in-situ, but the first in-situ etching process using NF ₃ gas as the main gas is performed.

The primary in-situ etching process using an NF ₃ gas, using the NF ₃ gas is used alone or a mixed gas of NF ₃ and He. At this time, the flow rate of NF ₃ is 10 sccm to 150 sccm, and the flow rate of He is limited to 500 sccm to 1000 sccm. Here, hydrogen (H ₂ ) may be added at a flow rate of 800 sccm to 900 sccm to obtain better etching profile characteristics. In other words, the addition of hydrogen gas can obtain the effect of removing some of the point of the first deposition.

Source power and bias power are used at 3000W to 6000W and 500W to 1500W, respectively, and the etching thickness is about 10 nm to 50 nm based on the flat semiconductor substrate so as not to damage the upper part of the pattern.

As such, when the first in-situ etching process is performed while flowing NF ₃ gas and He simultaneously, the etching characteristics of the first HDP USG 28 are reduced by the intrinsic etching characteristics (isotropic etching) of the NF ₃ gas. Insignificant but wider.

In detail, the first HDP USG 28 during the first deposition is partially etched by the NF ₃ gas and remains as the first HDP USG 38a which widens the gap fill inlet of the trench 24. Here, the portion of the first HDP USG 28 formed in the bottom portion of the trench 24 is hardly etched, and it can be seen that the etching is mainly performed on the sidewalls of the trench 24 rather than the etching on the pad nitride layer 23. .

Therefore, after the first in situ etching process, the remaining first HDP USG 28a has a shape of 'W12' wider than the initial deposition, but the height H11 is still maintained at the same level as the initial deposition. do.

Next, a second in-situ etching process, which is the second of the DEED etching processes, is performed.

As shown in FIG. 2D, the secondary in-situ etching process uses a mixed gas of NF ₃ , He, and O ₂ . At this time, the flow rate of NF ₃ is 40 sccm to 120 sccm, the flow rate of He is 100 sccm to 500 sccm, and the flow rate of O ₂ is limited to 50 sccm to 160 sccm. The source power and the bias power are used at 3000 W to 6000 W and 500 W to 1500 W, respectively, and the etching thickness is about 10 nm to 50 nm based on the flat semiconductor substrate so as not to damage the upper part of the pattern.

As such, when the second in-situ etching process is performed while flowing NF ₃ , He, and O ₂ simultaneously, the intrinsic etching characteristics (chemical etching) of the NF ₃ gas and the inherent etching characteristics (physical sputtering) of O ₂ are obtained. By the etching characteristic of the first HDP USG 28a has a form in which the height is reduced to 'H12'. In this case, the NF ₃ gas mainly serves to etch the material that is etched and redeposited by the O ₂ gas, rather than acting to widen the width, thereby preventing the width from decreasing. That is, reducing the height of the first HDP USG 28a to 'H12' is possible only by physical sputtering using only O ₂ gas, but the material generated after the physical sputtering is re-deposited on the sidewalls, so that there is a tendency to decrease the height. Therefore, by using the NF ₃ gas at the same time to remove the redeposited material to maintain the area W12 after the first in situ etching.

In detail, the first HDP USG 28a subjected to the first in situ etching is partially etched by the O ₂ gas and the NF ₃ gas and remains as the first HDP USG 28b whose height is reduced to 'H 12'. Here, it can be seen that the portion formed in the bottom portion of the trench 24 among the first HDP USG 28a is hardly etched, and the portion formed in the upper portion of the trench 24 is mainly etched.

In the second in situ etching process, since the fluorine nitrogen is bonded in the first HDP USG 28b film, the reflective index of the film is maintained in the range of 1.46 to 1.5 to improve the stability of the film.

Finally, the deposition process, which is the last process of the DEED method, is performed.                     

As shown in FIG. 2E, the second HDP USG 29 is deposited to completely fill the trench 24 on the first HDP USG 28b having a significantly reduced height through first and second in situ etching processes.

At this time, unlike the first HDP USG 28 at the time of the first deposition, the second HDP USG 29 is deposited to have a thickness of 50 nm to 5000 nm using a deposition condition with a high deposition rate.

For example, of the 2HDP USG (29) also silane (SiH _4), oxygen (O ₂₎ and helium silane (SiH ₄₎ to speed up the deposition rate for mixing with a (He) as a deposition gas The flow rate of 40 sccm to 120 sccm, the flow rate of oxygen (O ₂ ) to 50 sccm to 160 sccm, and the flow rate of helium (He) are maintained in the range of 100 sccm to 500 sccm. In addition to the flow rate of the deposition gas, in order to obtain a fast deposition rate of the second HDP USG 29, the adjustment of the bias power (Bias power) should be accompanied, the bias power is preferably raised to the range of 2000W ~ 3000W. On the other hand, the source power is applied in the range of 4500W to 6000W.

The deposition rate at the bottom of the trench 24 is higher than the deposition rate at the sidewalls of the trench 24 by using deposition conditions for realizing a high deposition rate in the deposition process of the second HDP USG 29 as described above. Because of the high, the trench 24 can be sufficiently gapfilled without voids. In addition, since the height of the first HDP USG 28 at the time of initial deposition is reduced to 'W12' which is widened to 'H12' through the first and second in situ etching processes, the second HDP USG 29 may be gap-filled without voids. Can be.

3 is a view quantifying the height, bottom thickness and width of the first HDP USG according to an embodiment of the present invention.

Referring to FIG. 3, when the first and second in-situ etching processes are performed after the deposition of the first HDP USG, the height is almost unchanged until the first in-situ etching process, but is rapidly decreased during the second in-situ etching process.

And, it can be seen that the bottom thickness is still unchanged even after the first and second in situ etching processes after deposition.

Finally, it can be seen that the area decreases during the first in situ etching process after deposition and hardly changes during the second in situ etching process.

In the above-described embodiment, the gap fill method of the trench for device isolation has been described, but it is applicable to all gap fill processes of a semiconductor device using HDP USG as a gap fill material of a gap. For example, the present invention may be applied to an interlayer dielectric gap fill process using HDP USG.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has an effect of gap gap filling without voids by improving the gap fill margin of the DED method by using the gap fill process using the DEED method.

Claims (12)

Forming a pattern with a gap on the semiconductor substrate; Depositing a first HDP oxide layer on the pattern to partially fill the gap; Partially etching the first HDP oxide layer twice, leaving the first HDP oxide layer having a lower height while widening the gap opening of the gap; And Depositing a second HDP oxide film on the remaining first HDP oxide film to completely gap fill the gap; A gap fill method of a semiconductor device comprising a. The method of claim 1, Etching twice of the first HDP oxide film, First etching the first HDP oxide layer to widen an opening of the gap; And Second etching the first etched first HDP oxide layer to lower the height of the first HDP oxide layer A gap fill method of a semiconductor device comprising a. The method of claim 2, The first etching is performed using a gas accompanying chemical etching, the second etching is a gap fill method of a semiconductor device, characterized in that by proceeding by mixing the gas accompanied by physical etching and the gas accompanied by chemical etching. The method of claim 3, The first etching is using the NF ₃ , the second etching is a gap fill method of a semiconductor device, characterized in that using a mixed gas of NF ₃ and O ₂ . Forming a trench in the semiconductor substrate; Depositing a first HDP oxide layer on the semiconductor substrate to partially gapfill the trench; First in situ etching the first HDP oxide layer to widen the gap fill inlet of the trench; Etching the first in-situ-etched first HDP oxide layer in-situ second-in situ to lower the height of the first HDP oxide layer; And Depositing a second HDP oxide layer on the second in situ etched first HDP oxide layer to completely gap fill the trench; A gap fill method of a semiconductor device comprising a. The method of claim 5, The first in-situ etching is performed using the NF ₃ as the main gas gap fill method of a semiconductor device. The method of claim 6, The first in situ etching, Hep and H ₂ are mixed with the NF ₃ to advance the gap fill method of a semiconductor device. The method of claim 7, wherein The flow rate of the NF ₃ is 10sccm to 150sccm, the flow rate of He is 500sccm to 1000sccm, the flow rate of the H ₂ is 800sccm to 900sccm. The method of claim 8, The first in-situ etching is a gap fill method of a semiconductor device, characterized in that the source power and the bias power is used at 3000W to 6000W, 500W to 1500W, respectively. The method of claim 5, The second in situ etching, A gap fill method of a semiconductor device, characterized by advancing NF ₃ , He and O ₂ . The method of claim 10, The flow rate of the NF ₃ is 40sccm ~ 120sccm, the He flow rate is 100sccm ~ 500sccm, the flow rate of the O ₂ is 50sccm ~ 160sccm The gap fill method of a semiconductor device. The method of claim 11, The secondary in-situ etching method uses a source power and a bias power of 3000W to 6000W and 500W to 1500W, respectively.

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