KR100655072B1 - semiconductor wafer aligner pin assembly - Google Patents

semiconductor wafer aligner pin assembly Download PDF

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KR100655072B1
KR100655072B1 KR1020000075902A KR20000075902A KR100655072B1 KR 100655072 B1 KR100655072 B1 KR 100655072B1 KR 1020000075902 A KR1020000075902 A KR 1020000075902A KR 20000075902 A KR20000075902 A KR 20000075902A KR 100655072 B1 KR100655072 B1 KR 100655072B1
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aligner
semiconductor wafer
wafer
aligner pin
body portion
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KR1020000075902A
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KR20020047472A (en
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이윤성
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

반도체 웨이퍼를 프로세스 챔버내로 로딩하기 전에 웨이퍼의 플랫 존을 얼라인할 시에 발생될 수 있는 얼라이너 핀의 픽킹 링 이탈문제를 해결하기 위하여 개선된 구조를 가지는 반도체 웨이퍼 얼라이너 핀 어셈블리 구조가 개시된다. 그러한 반도체 웨이퍼 얼라이너 핀 어셈블리 구조는, 대체로 원형으로 된 바디부와 상기 바디부의 일단에 형성된 단차부를 가지는 얼라이너 핀과, 반도체 웨이퍼를 픽킹하기 위해 상기 얼라이너 핀의 상기 단차부에 내주면이 압착 삽입되며 상기 얼라이너 핀의 단차부의 에지부가 개방되어지도록 하기 위해 일측부가 상기 바디부에 면접촉되는 오링파트를 가짐을 특징으로 한다.
Disclosed is a semiconductor wafer aligner pin assembly structure having an improved structure to solve the picking ring deviation of aligner pins that may occur when aligning the flat zone of the wafer prior to loading the semiconductor wafer into the process chamber. . Such a semiconductor wafer aligner pin assembly structure has an aligner pin having a generally circular body portion and a stepped portion formed at one end of the body portion, and an inner circumferential surface of the aligner pin is inserted into the stepped portion for picking the semiconductor wafer. And an O-ring part having one side portion in surface contact with the body portion to open the edge portion of the stepped portion of the aligner pin.

반도체 웨이퍼, 로딩, 웨이퍼의 플랫 존, 얼라인 Semiconductor Wafers, Loading, Flat Zone, Alignment of Wafers

Description

반도체 웨이퍼 얼라이너 핀 어셈블리 구조{semiconductor wafer aligner pin assembly} Semiconductor wafer aligner pin assembly             

도 1은 본 발명에 적용가능한 반도체 웨이퍼 로딩 및 언로딩 장치의 평면구조도1 is a plan view of a semiconductor wafer loading and unloading apparatus applicable to the present invention.

도 2는 종래기술에 따른 반도체 웨이퍼 얼라이너 핀 어셈블리 구조도2 is a structural diagram of a semiconductor wafer aligner pin assembly according to the prior art

도 3은 본 발명의 실시 예에 따른 반도체 웨이퍼 얼라이너 핀 어셈블리 구조도
3 is a structural diagram of a semiconductor wafer aligner pin assembly according to an embodiment of the present invention.

본 발명은 반도체소자의 제조장치 분야에 관한 것으로, 특히 반도체 웨이퍼 얼라이너 핀 어셈블리 구조에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of manufacturing devices for semiconductor devices, and more particularly, to a semiconductor wafer aligner pin assembly structure.

근래에 컴퓨터 등과 같은 정보 매체의 급속한 보급에 따라 메모리 반도체 등과 같은 반도체 장치도 비약적으로 발전하고 있다. 그 기능 면에 있어서, 상기 반도체 장치는 고속으로 동작하는 동시에 메모리인 경우 대용량의 저장 능력을 가질 것이 요구된다. 이러한 요구에 부응하여 반도체소자는 집적도, 신뢰도 및 응답 속도 등을 향상시키는 방향으로 제조 기술이 지속적으로 발전되고 있다. 특히 하이 퍼포먼스 디바이스를 사용자들이 요구함에 따라 그러한 반도체 소자를 제조하는 제조장비의 퍼포먼스는 매우 중요하게 대두되고 있다. In recent years, with the rapid spread of information media such as computers, semiconductor devices such as memory semiconductors are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity in the case of a memory. In response to these demands, the manufacturing technology of semiconductor devices has been continuously developed to improve the degree of integration, reliability, and response speed. In particular, as users demand high-performance devices, the performance of manufacturing equipment for manufacturing such semiconductor devices becomes very important.

일반적으로, 반도체 제조공정 중에는 프로세스 챔버로 웨이퍼를 로딩 및 언로딩하는 공정이 있는데 이는, 도 1과 같은 반도체 웨이퍼 로딩 및 언로딩 장치에 의해 수행된다. Generally, there is a process of loading and unloading a wafer into a process chamber during a semiconductor manufacturing process, which is performed by a semiconductor wafer loading and unloading apparatus as shown in FIG. 1.

도 1에서 보여지는 장치내에서, 얼라이너(3)에는 얼라인용 핀 어셈블리(30) 복수로 탑재되는데, 이는 통상적으로 도 2와 같이 되어있다. In the apparatus shown in FIG. 1, the aligner 3 is mounted with a plurality of alignment pin assemblies 30, which is typically as shown in FIG. 2.

도 2는 종래기술에 따른 반도체 웨이퍼 얼라이너 핀 어셈블리 구조도로서, 웨이퍼가 프로세스 챔버내로 로딩되기 전에 웨이퍼의 플랫 존을 맞추어 정렬하기 위하여, 3개의 얼라인용 핀 어셈블리(30)가 있으며, 이는 각기 단차부(23)를 가지는 얼라이너 핀(20)과 상기 얼라이너 핀(20)의 단차부(23)에 삽인되어 웨이퍼를 지지하는 픽킹 링(25)을 가진다. 상기 픽킹 링(25)의 구조는 도 2의 하부에 도시된 확대도에서 보여지는 바와 같이 상기 단차부(23)의 에지부를 완전히 덮고 있기 때문에 웨이퍼의 픽킹시 웨이퍼의 표면과의 부착력이 강하게 된다. 따라서, 반도체 웨이퍼를 프로세스 챔버내로 로딩하기 전에 웨이퍼의 플랫 존을 얼라인할 시에 얼라이너 핀의 픽킹 링이 이탈되는 문제가 빈번하게 초래된다. FIG. 2 is a schematic diagram of a semiconductor wafer aligner pin assembly according to the prior art, in which there are three alignment pin assemblies 30 for aligning the flat zone of the wafer before the wafer is loaded into the process chamber, each of which has a stepped portion. And a picking ring 25 inserted into the stepped portion 23 of the aligner pin 20 to support the wafer. Since the structure of the picking ring 25 completely covers the edge portion of the stepped portion 23 as shown in the enlarged view shown in the lower part of FIG. 2, the adhesion force to the surface of the wafer is strong during the picking of the wafer. Therefore, a problem frequently arises in that the picking ring of the aligner pin is dislodged when aligning the flat zone of the wafer before loading the semiconductor wafer into the process chamber.

상기한 바와 같이, 종래에는 반도체 웨이퍼를 프로세스 챔버내로 로딩하기 전에 웨이퍼의 플랫 존을 얼라인할 시에 얼라이너 핀의 픽킹 링이 이탈되는 문제가 있어 왔다.
As described above, there has conventionally been a problem in that the picking ring of the aligner pin is detached when the flat zone of the wafer is aligned before the semiconductor wafer is loaded into the process chamber.

본 발명의 목적은 상기한 종래의 문제점을 해소할 수 있는 반도체 웨이퍼 얼라이너 핀 어셈블리 구조를 제공함에 있다. An object of the present invention is to provide a semiconductor wafer aligner pin assembly structure that can solve the above-mentioned conventional problems.

본 발명의 다른 목적은 반도체 웨이퍼를 프로세스 챔버내로 로딩하기 전에 웨이퍼의 플랫 존을 얼라인할 시에 발생될 수 있는 얼라이너 핀의 픽킹 링 이탈문제를 해결할 수 있는 반도체 웨이퍼 얼라이너 핀 어셈블리 구조를 제공함에 있다. It is another object of the present invention to provide a semiconductor wafer aligner pin assembly structure that can solve the picking ring deviation of the aligner pins that may occur when aligning the flat zone of the wafer before loading the semiconductor wafer into the process chamber. Is in.

상기한 목적을 달성하기 위한 본 발명의 양상(aspect)에 따르면, 반도체 웨이퍼 얼라이너 핀 어셈블리 구조는, 대체로 원형으로 된 바디부와 상기 바디부의 일단에 형성된 단차부를 가지는 얼라이너 핀과, 반도체 웨이퍼를 픽킹하기 위해 상기 얼라이너 핀의 상기 단차부에 내주면이 압착 삽입되며 상기 얼라이너 핀의 단차부의 에지부가 개방되어지도록 하기 위해 일측부가 상기 바디부에 면접촉되는 오링파트를 가짐을 특징으로 한다.In accordance with an aspect of the present invention for achieving the above object, a semiconductor wafer aligner pin assembly structure includes an aligner pin having a generally circular body portion and a stepped portion formed at one end of the body portion, and a semiconductor wafer. An inner circumferential surface is press-inserted into the stepped portion of the aligner pin for picking, and one side portion has an O-ring part in surface contact with the body portion to open the edge portion of the stepped portion of the aligner pin.

상기한 구조에 따라, 반도체 웨이퍼를 프로세스 챔버내로 로딩하기 전에 웨이퍼의 플랫 존을 얼라인할 시에 발생될 수 있는 얼라이너 핀의 픽킹 링 이탈이 방지되거나 최소화 될 수 있다.
According to the above structure, the picking ring deviation of the aligner pin, which may occur upon aligning the flat zone of the wafer before loading the semiconductor wafer into the process chamber, can be prevented or minimized.

이하, 본 발명의 바람직한 실시 예를 첨부한 도면을 참조하여 상세히 설명하 기로 한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

도 1은 본 발명에 적용 가능한 로딩 및 언로딩 장치의 전체적인 평면도이다. 반도체 웨이퍼 로딩 및 언로딩 장치는 실질적으로 중앙부위에 탑재된 핸들링 로봇(2)을 가지는 베이스 프레임(1)를 포함한다. 상기 로봇(2)은 얼라이너(3), 두 개의 카세트 테이블(4), 및 수송 컨테이너 테이블(5) 및 가아드 페퍼 수송 메카니즘(1)에 의해 둘러쌓여져 있고,이들 모두는 베이스 프레임(1)내에 배열된다. 전체 장치는 핸들링 로봇(2)에 대하여 대향 관계로 배열됨에 의해 컴팩트하게 구성되어 있다. 각 부품들은 이하에서 기술될 것이다. 핸들링 로봇(2)은 로봇 아암(2b)에 의해 안정된 석션 헤드(2a)를 포함한다. 상기 로봇 아암(2b)는 수직적으로 움직임 가능하고, 수평적으로 신장 및 수축 가능하다. 상기 로봇 아암(2b)는 얼라이너(3), 카세트 테이블(4), 및 컨테이너 테이블(5)중의 선택된 하나에 적용될 수 있다. 수직 및 수평 움직임에 의해, 상기 로봇 아암(2b)는 원하는 위치로 세트될 수 있고 얼라이너(3), 카세트 테이블(4), 및 컨테이너 테이블(5)으로부터 신장되거나 수축될 수 있다. 로봇 아암(2b)의 회전에 의해 석션 헤드의 석션 표면은 상부 또는 하부로 터닝될 수 있다. 상기 얼라이너(3)는 공급되는 웨이퍼의 플랫방향의 상을 잡기 위해 광전자 센서(3a)를 포함한다. 그럼에 의해 웨이퍼의 위치와 방향이 검출된다. 상기 얼라이너(3)는 웨이퍼를 미리 설정된 위치와 필요한 방향으로 조정한다. CCD 카메라(7)는 상기 얼라이너(3)의 위헤 배치되어 에칭 또는 다른 수단의 의해 웨이퍼의 표면에 대하여 확정된 인식 데이터를 리드한다. 1 is an overall plan view of a loading and unloading apparatus applicable to the present invention. The semiconductor wafer loading and unloading device comprises a base frame 1 having a handling robot 2 mounted substantially at the center portion. The robot 2 is surrounded by an aligner 3, two cassette tables 4, and a transport container table 5 and a guard pepper transport mechanism 1, all of which are base frame 1. Arranged within. The whole device is compactly arranged by being arranged in an opposing relationship with respect to the handling robot 2. Each part will be described below. The handling robot 2 comprises a suction head 2a stabilized by a robot arm 2b. The robot arm 2b is vertically movable and horizontally extendable and retractable. The robot arm 2b can be applied to a selected one of the aligner 3, the cassette table 4, and the container table 5. By vertical and horizontal movement, the robot arm 2b can be set to the desired position and can be extended or retracted from the aligner 3, the cassette table 4, and the container table 5. By the rotation of the robot arm 2b the suction surface of the suction head can be turned up or down. The aligner 3 includes an optoelectronic sensor 3a for catching an image in the flat direction of the wafer to be supplied. The position and orientation of the wafer are thereby detected. The aligner 3 adjusts the wafer in a predetermined position and in the required direction. The CCD camera 7 is arranged above the aligner 3 to read the determined recognition data on the surface of the wafer by etching or other means.

도 2중 얼라이너(3)에 적용되는 반도체 웨이퍼 얼라이너 핀 어셈블리 구조를 보인 도 3을 참조하면, 얼라이너 핀(20)과, 오링파트(26)가 보여진다. 상기 얼라이너 핀(20)은 대체로 원형으로 된 바디부(20)와 상기 바디부의 일단에 형성된 단차부(23)를 가지며, 상기 오링파트(26)는 반도체 웨이퍼(10)를 픽킹하기 위해 상기 얼라이너 핀(20)의 상기 단차부(23)에 내주면이 압착 삽입되며 상기 얼라이너 핀의 단차부의 에지부가 개방되어지도록 하기 위해 일측부가 상기 바디부에 면접촉된다. 여기서, 상기 얼라이너 핀 어셈블리는 웨이퍼를 얼라인 하기 위해 3개로 설치된다. 또한, 상기 오링파트의 외경은 상기 바디부의 외경보다 적어도 큰 것이 좋으며, 상기 오링파트는 웨이퍼 압착력이 양호한 고무재질일 수 있다. Referring to FIG. 3, which shows a semiconductor wafer aligner pin assembly structure applied to the aligner 3 in FIG. 2, the aligner pin 20 and the O-ring part 26 are shown. The aligner pin 20 has a generally circular body portion 20 and a stepped portion 23 formed at one end of the body portion, and the oring part 26 is used to pick the semiconductor wafer 10. An inner circumferential surface is press-inserted into the stepped portion 23 of the liner pin 20 and one side portion is in surface contact with the body portion so that the edge portion of the stepped portion of the aligner pin is opened. Here, three aligner pin assemblies are installed to align the wafer. In addition, the outer diameter of the O-ring part is preferably at least larger than the outer diameter of the body portion, the O-ring part may be a rubber material having a good wafer compression force.

따라서, 반도체 웨이퍼를 프로세스 챔버내로 로딩하기 전에 웨이퍼의 플랫 존을 얼라인할 시에 웨이퍼와의 접촉면적이 종래의 경우에 비해 줄어들므로, 얼라이너 핀의 픽킹용 오링 이탈이 방지되거나 최소화되어진다. Thus, when aligning the flat zone of the wafer prior to loading the semiconductor wafer into the process chamber, the contact area with the wafer is reduced as compared with the conventional case, so that the picking of the aligner pins for the O-ring deviation is prevented or minimized.

상기에서는 본 발명의 바람직한 실시 예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다. 예를 들어, 오링파트의 형상을 원형에서 변경하여 다각형의 형태로 사안에 따라 적절히 개량할 수 있음은 물론이다.
Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can. For example, it is a matter of course that the shape of the O-ring part can be appropriately improved according to the matter in the form of a polygon by changing from a circle.

상기한 바와 같은 반도체 제조장비의 구조에 따르면, 반도체 웨이퍼를 프로세스 챔버내로 로딩하기 전에 웨이퍼의 플랫 존을 얼라인할 시에 발생될 수 있는 얼라이너 핀의 픽킹 링 이탈이 방지되거나 최소화 되는 효과가 있다.


















According to the structure of the semiconductor manufacturing equipment as described above, the picking ring deviation of the aligner pin, which may be generated when the flat zone of the wafer is aligned before loading the semiconductor wafer into the process chamber, is prevented or minimized. .


















Claims (4)

반도체 웨이퍼 얼라이너 핀 어셈블리 구조에 있어서:In the semiconductor wafer aligner pin assembly structure: 대체로 원형으로 된 바디부와 상기 바디부의 일단에 형성된 단차부를 가지는 얼라이너 핀과;An aligner pin having a generally circular body portion and a stepped portion formed at one end of the body portion; 반도체 웨이퍼를 픽킹하기 위해 상기 얼라이너 핀의 상기 단차부에 내주면이 압착 삽입되며 상기 얼라이너 핀의 단차부의 에지부가 개방되어지도록 하기 위해 일측부가 상기 바디부에 면접촉되는 오링파트를 가짐을 특징으로 하는 구조.An inner circumferential surface is press-inserted into the stepped portion of the aligner pin to pick the semiconductor wafer, and one side portion has an O-ring part having surface contact with the body portion to open the edge portion of the stepped portion of the aligner pin. Structure. 제1항에 있어서, 상기 오링파트의 외경은 상기 바디부의 외경보다 적어도 큼을 특징으로 하는 구조.The structure of claim 1, wherein an outer diameter of the O-ring part is at least larger than an outer diameter of the body portion. 제1항에 있어서, 상기 오링파트는 고무재질임을 특징으로 하는 구조.The structure of claim 1, wherein the O-ring part is made of rubber. 제1항에 있어서, 상기 얼라이너 핀 어셈블리는 웨이퍼를 얼라인 하기 위해 3개로 설치됨을 특징으로 하는 구조.2. The structure of claim 1 wherein the aligner pin assemblies are installed in three to align the wafer.
KR1020000075902A 2000-12-13 2000-12-13 semiconductor wafer aligner pin assembly KR100655072B1 (en)

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