KR100650768B1 - Cell transistor threshold voltage trimming circuit and method thereof - Google Patents

Abstract

A threshold voltage trimming circuit and method of a cell transistor are provided to converge a threshold voltage of the cell transistor of a specific die deviated from a target value, on the target value by using cell trimming of modulating the threshold voltage of the cell transistor according to the voltage of a well where a cell is formed. A monitor cell array(10) includes plural cell transistors having the same threshold voltage characteristics as a main cell transistor. A target voltage generation part(30) turns on the cell transistor by applying a threshold voltage target value to the monitor cell array. A reference threshold voltage model part(20) includes a model resistor receiving an external power supply voltage, and the model resistor has the total resistance value of the monitor cell array when the threshold voltage of the cell transistor has the threshold voltage target value. A VBB(bulk bias voltage) providing unit(40) generates a reference voltage by using a voltage proportional to the output current of the monitor cell array and the reference threshold voltage model part respectively, and makes the threshold voltage of the cell transistor converge on the threshold voltage target value by applying a VBB proportional to the reference voltage to the cell transistor.

Description

Cell transistor threshold voltage trimming circuit and method thereof

1 is a diagram illustrating a distribution of threshold voltage windows of a cell transistor and threshold voltages of a cell transistor according to a conventional technology shrink;

2 is a circuit diagram illustrating a cell transistor threshold voltage trimming according to an embodiment of the present invention;

3 is a graph showing a trend of a cell transistor threshold voltage according to VBB;

4 is a view for explaining a change in the defective rate before and after trimming the cell transistor threshold voltage.

<Description of the symbols for the main parts of the drawings>

10: monitor cell array 20: reference threshold voltage model

30: target voltage generator 40: VBB generator

42: D / A converter 44: Up-down counter

46: comparator 50: first resistor

52: second resistor 60: decoder

62: register 70: counter control unit

72: pulse generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a threshold voltage trimming circuit of a cell transistor, and more particularly, to extracting an average cell threshold voltage of a die and using a well voltage to compensate for process variations in the threshold voltage of a DRAM cell transistor. A voltage trimming circuit and a method thereof are provided.

In general, the threshold voltage of a cell transistor refers to V _GS at which current I _DS starts to flow when V _GS of the MOS transistor is increased from 0 to +. The threshold voltage of such a cell transistor is the most important factor in securing operating margin among various factors that determine the yield of DRAM products.

In terms of process, the threshold voltage of the cell transistor is varied due to the complex action of almost all process steps, so managing the threshold voltage variation of the cell transistor is an absolute requirement for securing a stable yield of the process. .

In terms of design, the threshold voltage window of the cell transistor covering the threshold voltage fluctuation range of the cell transistor is introduced by introducing a sufficient design margin and fluctuation compensation concept so that the threshold voltage of the cell transistor does not affect the circuit operation even if there is some variation. It is necessary to secure a window.

However, as technology shrinks, gate CD (critical dimension) and ISO CD, which affect the threshold voltage variation of the cell transistor, continue to decrease, and the process variation of the threshold voltage of the cell transistor is gradually increasing. Moreover, the demand for refresh time to meet low-power products has increased dramatically, and the demand for cell turn-on resistance for reviving high-speed DRAM operation continues to decrease, so the threshold of cell transistors The upper limit of the voltage is decreasing.

Here, the CD (critical dimension) is the minimum line width, which is difficult to realize technically, or close to the final line width of the pattern obtained by transferring the pattern converted from the layout of the product into the reticle on the actual wafer. It refers to the line width of a small pattern, such as a DICD (Develop Inspection CD), a photoresist formed during photolithography, and a final inspection CD (FICD), in which a pattern is finally formed through an etching process.

On the other hand, shrinking the gate CD means a more rapid increase in channel leakage due to a decrease in the threshold voltage of the cell transistor, so that the lower limit of the threshold voltage of the cell transistor is also increased, resulting in a good die. The threshold voltage window width of the cell transistor to be obtained is reduced.

FIG. 1 is a diagram illustrating a distribution of threshold voltage windows of a cell transistor and threshold voltages of a cell transistor according to a conventional technology shrink. Referring to FIG. 1, it can be seen that the threshold voltage window of the cell transistor according to the technology shrink is narrowed and the variation range of the cell transistor threshold voltage of the die increases as compared with the case of the existing technology, thereby increasing the defective die.

FIG. 1 illustrates a correlation between a cell transistor threshold voltage and a fail bit when the cell transistor threshold voltage is small in the conventional technology, and FIG. 2 shows a cell transistor threshold voltage and fail bit when the cell transistor threshold voltage is small in the shrink technology. FIG. 3 shows the correlation between the cell transistor threshold voltage and the fail bit when the cell transistor threshold voltage is large in the prior art, and FIG. 4 shows the cell transistor threshold voltage when the cell transistor threshold voltage is large in the shrink technique. FIG. 5 shows the target management level of the fail bit caused by the change of the cell transistor threshold voltage.

In addition, the number 6 represents the lower limit target value of the cell transistor threshold voltage in the conventional technology, the number 7 represents the lower limit target value of the cell transistor threshold voltage in the shrink technology, and the number 8 represents the upper limit target value of the cell transistor threshold voltage in the conventional technology, FIG. 9 shows the upper limit target value of the cell transistor threshold voltage in the shrink technique.

In addition, Fig. 10 shows the product-specific cell transistor threshold voltage measured within the target range in a white circle, and Fig. 11 shows the product-specific cell transistor threshold voltage outside the target range in the conventional technology. In Fig. 12, the number 12 shows the cell transistor threshold voltage value of each product managed within the target range of the shrink technology in white triangle, and the number 13 shows the product out of the target range in the shrink technology. The cell transistor threshold voltage measurement for each product is indicated by a black triangle.

In other words, in order to meet the product requirements of low power and high speed operation, the threshold voltage window of the cell transistor is continuously decreasing, and the variation of the threshold voltage of the cell transistor is generally increasing with technology shrink. to be.

Therefore, when the reduction of the threshold voltage window of the cell transistor and the increase in the variation of the threshold voltage of the cell transistor are combined, there is a problem in that the fail rate of the DRAM increases rapidly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and deviates from the target value by using a principle ('cell trimming') in which the threshold voltage of the cell transistor is modulated according to the voltage V _BB value of the well where the cell is formed. An object of the present invention is to provide a cell transistor threshold voltage trimming circuit and a method for converging a threshold voltage of a cell transistor of a specific die to a target value.

To this end, the present invention provides a cell transistor threshold voltage trimming circuit and a method for monitoring the threshold voltage of a cell transistor of a die and selecting an appropriate VBB according to the deviation of the target value of the cell transistor threshold voltage.

In order to achieve the above object, the present invention includes a monitor cell array including a plurality of cell transistors having the same threshold voltage as the main cell transistor; A target voltage generator configured to turn on the cell transistor by applying a threshold voltage target value CVT_ref to the monitor cell array; A reference threshold voltage model unit including a model resistor receiving an external power supply voltage VDD, wherein the model resistor has a total resistance of the monitor cell array when the threshold voltage of the cell transistor has the threshold voltage target value; And generating a reference voltage by using a voltage proportional to an output current of the monitor cell array and the reference threshold voltage model unit, and applying a bulk bias voltage VBB proportional to the reference voltage to the cell transistor. It includes; VBB providing means for causing the threshold voltage of the convergence to the threshold voltage target value.

Here, the monitor cell array includes a cell transistor threshold voltage target voltage CVT_ref generated by the target voltage generator, a power supply voltage VDD applied to a drain, and a source having a common ground. It is preferable that the pair is configured in parallel connection.

The apparatus further includes a first resistor to which the first voltage is applied by the first current flowing through the monitor cell array and a second resistor to which the second voltage is applied by the second current flowing to the reference threshold voltage model.

The VBB providing unit generates a counter up / counter down signal by generating a voltage difference obtained by comparing the first voltage and the second voltage, and outputs a counter up / counter down signal. Output up-down counter, D / A converter that receives the code and converts it into analog voltage value, and outputs the bulk bias voltage of absolute value proportional to the reference voltage with the analog voltage value as reference voltage (Vref_b) It includes a VBB generator.

In addition, the comparator and the up-down counter is preferably operated by receiving a clock.

The apparatus may further include a decoder for decoding the code received from the up-down counter, and a register for storing the decoded code, wherein the register is connected to a pad for outputting the decoded code to the outside.

In order to achieve the above object, the present invention comprises the steps of constructing a monitor cell array of a plurality of cell transistors having the same characteristics as the threshold voltage of the main cell transistor; Setting a model resistor having a resistance of the monitor cell array when the threshold voltage of the cell transistor has a threshold voltage target value; Applying a threshold voltage target value CVT_ref to the monitor cell array to turn on the cell transistor, and applying an external power supply voltage to the model resistor; Generating a reference voltage using a voltage proportional to the output current of the monitor cell array and the model resistor; And applying a bulk bias voltage VBB proportional to the reference voltage to the cell transistor so that the threshold voltage of the cell transistor converges to a threshold voltage target value.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram illustrating a cell transistor threshold voltage trimming according to an embodiment of the present invention. 2, a cell transistor threshold voltage trimming circuit according to an embodiment of the present invention includes a monitor cell array 10, a reference threshold voltage model 20, a target voltage generator 30, a comparator 46, An up-down counter 44, a D / A converter 42, a VBB generator 40, a decoder 60, a register 62, a counter control unit 70, and a pulse generator 72 are included.

The monitor cell array 10 is a monitoring array for extracting a cell transistor threshold voltage of a main cell. Therefore, the monitor cell array 10 may be manufactured in the same layout and the same process as the main cell to have the characteristics of the main cell, that is, the characteristics of the main cell transistor threshold voltage. The array unit may be composed of a parallel connection of thousands of cell transistors.

The monitor cell array 10 may further include an R1 resistor 50 to which a voltage is applied by the output current of the monitor cell array.

The reference threshold voltage model section 20 monitors cell array 10 characteristic, the cell transistor when having a target value of the threshold voltage as the same model, the resistance (R _model) block that has a value and the overall resistance value, the monitor cell array through the trim A reference value for checking whether the cell transistor threshold voltage (10) has reached the target value is provided.

Here, trimming refers to converging the cell transistor threshold voltage of a specific die deviating from the target value to a target value by using the principle that the cell transistor threshold voltage is modulated according to the voltage VBB value of the well in which the cell is formed. . The voltage VBB of the well is a bulk bias voltage of the cell transistor for reducing the cell leakage and stabilizing the threshold voltage. 3 is a graph illustrating the trend of the cell transistor threshold voltage according to VBB, and shows that the cell transistor threshold voltage varies according to VBB.

The reference threshold voltage model unit 20 may further include an nMOS transistor M1 for switching an external power supply voltage VDD and applying it to a model resistor. The turn-on resistance of the nMOS transistor M1 and R It is preferable that the layout size of the series connection resistance value of the _model is determined so that the influence of the process variation is minimized.

The reference threshold voltage model unit 20 further includes an R2 resistor 52 to which a voltage is applied by the output current of the reference threshold voltage model unit 20. This R2 resistor 52 is preferably connected in series with the model resistor.

The target voltage generator 30 supplies a gate voltage for turning on the monitor cell array 10. When the trimming start signal Trim_start is enabled, the target voltage generator 30 generates a constant voltage corresponding to the target voltage voltage CVT_ref of the cell transistor threshold voltage.

An independent cell transistor threshold voltage trimming function may be provided in the target voltage generator 30 to compensate for variations between dies of the cell transistor threshold voltage value.

The comparator 46 is a voltage applied to the output current I1 of the monitor cell array 10 (voltage applied to R1) and a voltage (R2) proportional to the output current I2 of the reference threshold voltage model unit 20. ) Is input and compared to generate a counter up / counter down signal.

The up-down counter 44 is reset by the trimming start signal Trim_start and has an initialized trim code value n-bit, and then counts up or counts down from the comparator 46. The trim code (trim_code) is updated by receiving a (count_down) signal and performing an up / down counting.

The D / A converter 42 converts the trim code updated at the up-down counter 44 into an analog voltage value.

The VBB generator 40 generates a VBB having an absolute value proportional to the reference voltage using the analog voltage value input from the D / A converter 42 as the reference voltage Vref_b.

The decoder 60 receives a trim code from the up-down counter 44 and decodes it in the register 62. The trim code value stored in the register 62 may be output through the pad during a specific test of the circuit, and finally used as VBB trimming fuse cutting information. The register 62 is preferably a 2 ^n- bit register so that it can store n-bit trim codes.

The counter controller 70 receives the trim code from the up-down counter 44 and disables the pulse generator 72 so that the up-down counter 44 no longer operates when the trim code has the maximum value or the minimum value. Let's do it.

The pulse generator 72 generates the number of pulses defined by the trimming start signal Trim_start. The minimum required number of pulses of the pulse generator 72 is the final state in which the threshold voltage value of the monitor cell array modified by modulating the voltage VBB of the well is within the range of the variation amount corresponding to the target voltage target value by one bit. It is desirable to set assuming a situation where the required number of pulses is maximized to ensure that the counter is counted up to.

In the most extreme situation, for example, if the resolution of the trim code input from the up-down counter 44 is n-bit and the initial value is a, the counter must counter to 0 or 2 ⁿ -1 before the suspend voltage When the target value or the threshold voltage target value is reached with the smallest difference, the required number of counters, that is, the number of pulses, is the larger of a or 2 ^n- 1-a. Therefore, it is preferable that the minimum number of pulses required is determined to be MAX (2 ^n- 1-a, a) or more.

The n-bit resolution here means that the up-down counter 44 can do 2 ⁿ counters. For example, if it is a 4-bit resolution, you can specify 0-15 separated states.

The following describes the operation of the cell transistor threshold voltage trimming circuit according to an embodiment of the present invention.

First, when the trimming start signal is enabled, the target voltage generator generates a gate voltage CVT_ref for turning on the monitor cell array and applies it to the gate of the monitor cell array. The voltage CVT_ref applied to the gate of the monitor cell array is a target value of the cell transistor threshold voltage.

When CVT_ref is applied to the gate of the monitor cell array and the gate is turned on, the turn-on current I1 of the transistors constituting the monitor cell array is generated. The current I1 is affected by the actual value of the cell transistor threshold voltage. As the cell transistor threshold voltage increases, the current I1 decreases.

In addition, when the trimming start signal is enabled, the nMOS transistor M1 of the reference cell transistor threshold voltage model part is turned on to generate a current I2. The current I2 generated at this time is preferably adjusted to be equal to the current I1 flowing in the monitor cell array when the cell transistor threshold voltage reaches the target value CVT_ref supplied by the target voltage generator.

That is, if the cell transistor threshold voltage is larger than the target value CVT_ref, the current I1 is smaller than the current I2, and if the cell transistor threshold voltage is smaller than the target value CVT_ref, the current I1 is larger than the current I2.

When the current I1 and the current I2 input two voltages proportional to the magnitude of the current through the resistor R1 and the resistor R2, respectively, the comparator compares the two input voltages and counts up or counts down the signal. Occurs.

The up-down counter receives a count up or count down signal from a comparator, performs up or down counting to update the initialized trim code, and inputs the updated trim code to the D / A converter.

The D / A converter converts the trim code received from the up-down counter into an analog voltage value and inputs it to the VBB generator. The VBB generator generates a VBB having an absolute value proportional to the reference voltage by using the analog voltage value input from the D / A converter as the reference voltage Vref_b. At this time, VBB is updated in a direction in which the cell transistor threshold voltage value of the monitor cell array converges to the target value CVT_ref.

That is, when the cell transistor threshold voltage is smaller than the target value CVT_ref, the absolute value of VBB is increased, and when the cell transistor threshold voltage is larger than the target value CVT_ref, it is corrected in the direction of decreasing the absolute value of VBB.

Through the cell trimming process described above, the threshold voltage of the cell transistor of the specific die deviating from the target value can be converged to the target value.

FIG. 4 is a diagram for explaining a defect rate change before and after trimming the cell transistor threshold voltage. As shown in FIG. 4, before the cell transistor threshold voltage trimming, the cell transistor threshold voltage distribution has the same distribution as that of FIG. Although the defective rate corresponding to the region occurs, after trimming the cell transistor threshold voltage, the cell transistor threshold voltage distribution is corrected as shown in FIG. 15, and the defective rate corresponding to the FIG. 17 region is generated. As can be seen that the defect rate can be reduced.

On the other hand, cell transistor threshold voltage trimming is preferably performed at the earliest stage of the normal test of the wafer. For example, after obtaining VBB trimming information for each die, trimming fuse cutting is performed to reduce the variation of the cell transistor threshold voltage, and then a probe test is performed, or the VBB forcing level for each die in consideration of the VBB trimming information. After determining the forcing level and performing a probe test, trimming fuse cutting can be performed later.

As described above, the cell transistor threshold voltage trimming circuit and the method of the present invention monitor the threshold voltage of the cell transistors of the die and select the appropriate VBB according to the deviation of the target value of the cell transistor threshold voltage to die the cell transistor threshold voltage. As a result of the correction, there is an effect of increasing production yield and increasing production yield and decreasing production cost.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (7)

A monitor cell array including a plurality of cell transistors having the same threshold voltage as a main cell transistor; A target voltage generator configured to turn on the cell transistor by applying a threshold voltage target value CVT_ref to the monitor cell array; A reference threshold voltage model unit including a model resistor receiving an external power supply voltage VDD, wherein the model resistor has a total resistance of the monitor cell array when the threshold voltage of the cell transistor has the threshold voltage target value; A reference voltage is generated using a voltage proportional to an output current of the monitor cell array and the reference threshold voltage model unit, and a bulk bias voltage VBB proportional to the reference voltage is applied to the cell transistor to provide a reference voltage. VBB providing means for causing the threshold voltage to converge to the threshold voltage target value; Threshold voltage trimming circuit of a cell transistor comprising a. The method of claim 1, The monitor cell array A cell transistor threshold voltage target voltage CVT_ref generated by the target voltage generator is applied to a gate, a power supply voltage VDD is applied to a drain, and a plurality of pairs of cell transistors having a common ground source are connected in parallel. Threshold Trimming Circuit of Cell Transistor. The method of claim 1, And a first resistor to which the first voltage is applied by the first current flowing through the monitor cell array, and a second resistor to which the second voltage is applied by the second current flowing to the reference threshold voltage model. Threshold Trimming Circuit of Cell Transistor. The method of claim 3, wherein The VBB providing means A comparator for generating a counter up / counter down signal and outputting a voltage difference compared with the first voltage and the second voltage; An up-down counter which receives the counter up / counter down signal and outputs a counter code; A D / A converter for receiving the code and converting the analog voltage value to the analog voltage value; The analog voltage value is referred to as a reference voltage (Vref_b), and includes a VBB generator for outputting a bulk bias voltage of an absolute value proportional to the reference voltage Threshold Trimming Circuit of Cell Transistor. The method of claim 4, wherein The comparator and the up-down counter operate by receiving a clock. Threshold Trimming Circuit of Cell Transistor. The method of claim 4, wherein Decoder for decoding the code received from the up-down counter, Further comprising a register for storing the decoded code, The register is connected to a pad for outputting the decoded code to the outside Threshold Trimming Circuit of Cell Transistor. Constructing a monitor cell array with a plurality of cell transistors having characteristics equal to the threshold voltage of the main cell transistor; Setting a model resistor having a resistance of the monitor cell array when the threshold voltage of the cell transistor has a threshold voltage target value; Applying a target voltage target value CVT_ref to the monitor cell array to turn on the cell transistor and applying an external power supply voltage to the model resistor; Generating a reference voltage using a voltage proportional to the output current of the monitor cell array and the model resistor; And Applying a bulk bias voltage VBB proportional to the reference voltage to the cell transistor such that the threshold voltage of the cell transistor converges to a threshold voltage target value. Threshold voltage trimming method of a cell transistor comprising a.

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