KR100649866B1 - Method for manufacturing semiconductor package - Google Patents

Method for manufacturing semiconductor package Download PDF

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KR100649866B1
KR100649866B1 KR1020000084889A KR20000084889A KR100649866B1 KR 100649866 B1 KR100649866 B1 KR 100649866B1 KR 1020000084889 A KR1020000084889 A KR 1020000084889A KR 20000084889 A KR20000084889 A KR 20000084889A KR 100649866 B1 KR100649866 B1 KR 100649866B1
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South Korea
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semiconductor package
warpage
molding
attaching
resin
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KR1020000084889A
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Korean (ko)
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KR20020055688A (en
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박성수
김영호
이선구
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020000084889A priority Critical patent/KR100649866B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

본 발명은 반도체 패키지 제조방법에 관한 것으로서, 반도체 패키지 제조용 부재의 몰딩영역 반대면에 몰딩수지와 유사한 열팽창계수를 갖는 접착수단을 부착하여, 반도체 패키지의 각 제조공정중 특히 몰딩공정후, 몰딩된 수지의 수축에 의하여 발생하는 부재의 워피지 현상을 상쇄시킬 수 있도록 한 반도체 패키지 제조방법을 제공하고자 한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package, wherein an adhesive means having a thermal expansion coefficient similar to that of a molding resin is attached to an opposite surface of a molding region of a member for manufacturing a semiconductor package, and in particular, after each molding process of the semiconductor package, An object of the present invention is to provide a method of manufacturing a semiconductor package capable of canceling a warpage phenomenon of a member caused by shrinkage.

반도체 패키지, 접착수단, 워피지, 몰딩수지, 수축Semiconductor package, adhesive means, warpage, molding resin, shrinkage

Description

반도체 패키지 제조 방법{Method for manufacturing semiconductor package} Method for manufacturing semiconductor package             

도 1은 본 발명에 따른 반도체 패키지 제조 방법을 나타내는 단면도,1 is a cross-sectional view showing a semiconductor package manufacturing method according to the present invention;

도 2는 종래의 반도체 패키지를 나타내는 단면도.2 is a cross-sectional view showing a conventional semiconductor package.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

10 : 부재 12 : 몰딩수지10 member 12 molding resin

14 : 워피지 흡수수단 16 : 반도체 칩14: warpage absorbing means 16: semiconductor chip

18 : 와이어 20 : 인출단자18: wire 20: withdrawal terminal

30 : 수지층 32 : 전도성패턴30: resin layer 32: conductive pattern

34 : 커버코트
34: cover coat

본 발명은 반도체 패키지 제조 방법에 관한 것으로서, 반도체 패키지의 제조공정중에 발생하는 워피지 현상을 감소시킬 수 있도록 한 반도체 패키지 제조 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package manufacturing method, and more particularly, to a semiconductor package manufacturing method capable of reducing warpage phenomenon occurring during a manufacturing process of a semiconductor package.                         

공통적으로 반도체 패키지는 그 구조에 관계없이, 인쇄회로기판, 회로필름등 각종 부재의 칩탑재영역에 반도체 칩을 부착하는 공정과; 상기 부재의 와이어 본딩영역과 상기 반도체 칩의 본딩패드간을 와이어로 본딩하는 공정과; 상기 반도체 칩과 와이어등을 포함하는 부재의 몰딩영역을 수지로 몰딩하는 공정등을 거치게 된다.Commonly, a semiconductor package includes a step of attaching a semiconductor chip to a chip mounting region of various members such as a printed circuit board and a circuit film, regardless of its structure; Bonding a wire bonding region of the member to a bonding pad of the semiconductor chip with a wire; The process of molding the molding region of the member including the semiconductor chip, the wire, and the like with resin is performed.

특히, 상기 몰딩공정을 마친 반도체 패키지는 몰딩다이로부터 탈형된 후, 몰딩수지를 경화시키기 위하여, 오븐에 넣고 소정의 온도와 시간으로 경화시키게 된다.Particularly, after the molding process, the semiconductor package is demolded from the molding die, and then placed in an oven and cured at a predetermined temperature and time in order to cure the molding resin.

이때, 상기 인쇄회로기판과 회로필름 부재를 이용한 반도체 패키지의 몰딩수지는 일면에만 몰딩된 상태로서, 몰딩 다이의 열(175±5℃)을 받아 고온의 상태지만, 몰딩다이로부터 탈형된 후, 오븐에 넣기 전까지는 상온상태에서 이송됨에 따라, 급격한 온도 저하로 수축을 하게 되고, 그에따라 반도체 패키지 제조용 부재가 몰딩수지면쪽으로 만곡되게 휘어지는 워피지(휨:warpage)현상을 일으키게 된다.At this time, the molding resin of the semiconductor package using the printed circuit board and the circuit film member is molded on only one surface, and receives a heat (175 ± 5 ° C.) of the molding die, but is hot, but after being demoulded from the molding die, As it is transported at room temperature until it is put in, it contracts due to a sudden drop in temperature, thereby causing a warpage phenomenon in which a member for manufacturing a semiconductor package is bent toward the molding resin surface.

좀 더 상세하게는, 상기 부재와 몰딩수지는 열팽창계수(CTE: Coefficient of Thermal Expansion)가 서로 다르기 때문에, 상온에서 몰딩수지의 수축이 더욱 크게 일어남에 따라, 상기 반도체 패키지가 스트립 또는 매트릭스 배열을 이루며 제조되어 있는 부재가 전체적으로 휘어지게 되는 것이다.More specifically, since the coefficient of thermal expansion (CTE) of the member and the molding resin are different from each other, as the shrinkage of the molding resin occurs at room temperature, the semiconductor package forms a strip or matrix array. The manufactured member is bent as a whole.

결국, 상기와 같은 부재의 휨 현상은 반도체 패키지 내부의 와이어 단락, 칩 크랙과 같은 반도체 패키지의 불량을 낳게 된다.As a result, the warpage phenomenon of the member may lead to defects in the semiconductor package such as wire shorts and chip cracks in the semiconductor package.

또한, 몰딩공정과 경화공정후에 트리밍(trimming)이나 포밍(forming)등의 공정등에 서 부재가 휘어진 상태이기 때문에 공정상의 핸들링(Handling)을 하는데 어려움이 따르게 된다.In addition, since the member is bent in a trimming process or a forming process after the molding process and the curing process, it is difficult to handle the process.

따라서, 본 발명은 상기와 같은 점을 감안하여, 반도체 패키지 제조용 부재의 몰딩영역 반대면에 몰딩수지와 유사한 열팽창계수를 갖는 워피지 흡수수단을 부착하여, 반도체 패키지의 각 제조공정중 특히 몰딩공정후, 몰딩된 수지의 수축에 의하여 발생하는 부재의 워피지 현상을 상쇄시킬 수 있도록 한 반도체 패키지 제조 방법을 제공하는데 그 목적이 있다.
Therefore, in view of the above, the present invention attaches a warpage absorbing means having a thermal expansion coefficient similar to that of a molding resin on the opposite side of the molding region of the member for manufacturing a semiconductor package, and particularly after molding during each manufacturing process of the semiconductor package. It is an object of the present invention to provide a method for manufacturing a semiconductor package that can cancel a warpage phenomenon of a member caused by shrinkage of a molded resin.

상기한 목적을 달성하기 위한 본 발명은:The present invention for achieving the above object is:

부재의 칩부착영역에 반도체 칩을 부착하는 공정과, 상기 반도체 칩의 본딩패드와 부재의 본딩영역간을 와이어로 본딩하는 공정과, 상기 반도체 칩과 와이어를 포함하는 부재의 상면을 수지로 몰딩하는 공정과, 상기 부재의 상면에 노출된 인출단자 부착용 랜드에 인출단자를 융착하는 공정을 포함하는 반도체 패키지 제조방법에 있어서,Attaching a semiconductor chip to a chip attaching region of the member, bonding a bonding pad of the semiconductor chip to a bonding region of the member with a wire, and molding a top surface of the member including the semiconductor chip and the wire with a resin. And a step of fusing the lead-out terminal to the land for attaching the lead-out terminal exposed on the upper surface of the member.

상기 수지와 유사한 열팽창계수를 갖는 워피지 흡수수단을 상기 부재의 저면에 분리 가능하게 미리 부착시켜서, 상기 칩 부착 공정과, 와이어 본딩공정과, 몰딩공정과, 인출단자 부착공정중에 발생하는 부재의 워피지를 상기 워피지 흡수수단에서 상쇄시킬 수 있도록 한 것을 특징으로 한다. The warpage absorbing means having a thermal expansion coefficient similar to that of the resin is previously attached to the bottom of the member so as to be detachable, so that the warpage of the member generated during the chip attaching step, the wire bonding step, the molding step, and the drawing terminal attaching step is performed. It is characterized in that sebum can be offset by the warpage absorbing means.                     

특히, 상기 반도체 패키지의 제조 완료후, 상기 워피지 흡수수단을 떼어내는 단계가 더 진행됨을 특징으로 한다.In particular, after the manufacture of the semiconductor package, the step of removing the warpage absorbing means is further characterized in that it proceeds.

여기서 본 발명의 실시예를 첨부한 도면을 참조로 더욱 상세하게 설명하면 다음과 같다.Hereinafter, the embodiment of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도 1은 본 발명에 따른 반도체 패키지 제조 방법을 나타내는 단면도로서, 상기 반도체 패키지를 제조하는데 사용되는 부재는 인쇄회로기판 또는 회로필름이고, 이하 인쇄회로기판을 예로들어 설명한다.1 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to the present invention, wherein a member used to manufacture the semiconductor package is a printed circuit board or a circuit film.

상기 인쇄회로기판은 일면 구조로서, 첨부한 도 1내지 도 2에 도시한 바와 같이 베이스층인 절연재질의 수지층(30)과, 이 수지층(30)의 상면에 전기적인 배선 회로를 이루며 얇게 식각 처리된 동재질의 전도성패턴(32)과. 상기 전도성패턴중 와이어 본딩용 전도성패턴과 인출단자 부착용 전도성패턴을 외부로 노출시키면서 수지층(30)상에 도포된 커버코트(34)로 구성되어 있다.The printed circuit board has a single-sided structure. As shown in FIGS. 1 to 2, the resin layer 30 of an insulating material, which is a base layer, and an electrical wiring circuit are formed on the upper surface of the resin layer 30. Etched copper conductive pattern 32 and. The conductive pattern is composed of a cover coat 34 coated on the resin layer 30 while exposing the conductive pattern for wire bonding and the conductive pattern for attaching the drawing terminal to the outside.

상기와 같은 구조로 이루어진 인쇄회로기판의 상면에는 대개 커버코트로 도포된 칩부착영역과, 이 칩부착영역을 포함하는 몰딩영역이 형성되어 있다.On the upper surface of the printed circuit board having the above structure, a chip attaching region usually coated with a cover coat and a molding region including the chip attaching region are formed.

특히, 본 발명의 주된 특징으로서, 상기 인쇄회로기판과 같은 부재(10)의 저면에는 몰딩수지(12)와 유사한 열팽창계수를 갖는 필름 형태의 워피지흡수수단(14)이 미리 부착되어진다.In particular, as a main feature of the present invention, a film-like warpage absorbing means 14 having a thermal expansion coefficient similar to that of the molding resin 12 is previously attached to the bottom surface of the member 10 such as the printed circuit board.

따라서, 상기 부재(10)의 칩부착영역에 반도체 칩(16)을 부착하는 단계를 진행하고, 이어서 상기 반도체 칩(16)의 본딩패드와 부재(10)의 와이어 본딩용 전도성패턴간을 와이어(18)로 본딩하는 단계를 진행한 후, 반도체 칩(16)과 와이어(18) 등이 포함되어 있는 부재(10)의 몰딩영역을 수지(12)로 몰딩하는 단계를 진행시키게 된다.Therefore, the process of attaching the semiconductor chip 16 to the chip attaching region of the member 10 is performed, and then a wire is formed between the bonding pad of the semiconductor chip 16 and the conductive pattern for wire bonding of the member 10. After the bonding to 18, the molding region of the member 10 including the semiconductor chip 16, the wire 18, and the like is molded into the resin 12.

이때, 상술한 바와 같이 몰딩수지(12)는 부재(10)의 일면에만 몰딩된 상태로서, 몰딩다이의 열(175±5℃)을 받아 고온의 상태지만, 몰딩다이로부터 탈형된 후, 수지의 경화를 위하여 오븐에 넣기 전까지는 상온 상태이기 때문에, 급격한 온도 저하로 몰딩수지(12)는 수축을 하게 되는 바, 상기 워피지 흡수수단(14)도 몰딩수지(12)의 수축과 함께 수축을 하게 된다.At this time, as described above, the molding resin 12 is molded only on one surface of the member 10, and receives a heat (175 ± 5 ° C.) of the molding die, but is in a high temperature state, but after demolding from the molding die, Since it is at room temperature until it is put in an oven for curing, the molding resin 12 contracts due to a sudden drop in temperature, so that the warpage absorbing means 14 also contracts with the shrinking of the molding resin 12. do.

즉, 상기 몰딩수지(12)의 수축에 의하여 부재(10)가 몰딩수지(12)쪽으로 만곡되며 휘어지는 워피지 현상을 일으킬 수 있지만, 부재(10)의 반대면에 부착된 워피지 흡수수단(14)도 부재(10)를 끌어 당기는 수축을 하게 된다.That is, although the member 10 may be bent toward the molding resin 12 by the contraction of the molding resin 12 and may cause warpage, the warpage absorbing means 14 may be attached to the opposite surface of the member 10. ) Will also make a contraction that pulls the member 10.

보다 상세하게는, 상기 워피지 흡수수단(14)의 열팽창계수는 몰딩수지(12)의 열팽창계수과 서로 유사하기 때문에 그 수축율도 유사하게 나타나게 되는 바, 따라서 상기 워피지 흡수수단(14)의 수축은 몰딩수지(12)의 수축을 상쇄시키는 동시에 부재(10)가 몰딩수지(12)쪽으로 휘어지는 것을 잡아주게 되어, 결국 부재(10)의 워피지를 크게 줄일 수 있게 된다.More specifically, since the coefficient of thermal expansion of the warpage absorbing means 14 is similar to the coefficient of thermal expansion of the molding resin 12, the shrinkage is also similar, so that the shrinkage of the warpage absorbing means 14 is At the same time offsetting the shrinkage of the molding resin 12 to hold the member 10 to bend toward the molding resin 12, it is possible to reduce the warpage of the member 10 significantly.

한편, 상기 부재(10)의 몰딩수지(12) 주변으로 노출되어 있는 인출단자 부착용 전도성패턴에 전도성의 솔더볼과 같은 다수의 인출단자(20)를 부착하는 단계를 마지막으로 본 발명의 반도체 패키지(100)가 제조된다.Meanwhile, the step of attaching a plurality of lead terminals 20, such as conductive solder balls, to the lead terminal attaching conductive pattern exposed around the molding resin 12 of the member 10, the semiconductor package 100 of the present invention ) Is manufactured.

이에, 상기 반도체 패키지(100)의 제조 완료후, 상기 워피지 흡수수단(14)을 떼어내게 된다.Thus, after the manufacture of the semiconductor package 100, the warpage absorbing means 14 is removed.

이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지 제조 방법에 의하면 수지로 몰딩된 면의 반대쪽면에 수지와 유사한 열팽창계수를 갖는 워피지 흡수수단을 부착시켜 줌으로써, 몰딩수지의 수축을 상쇄시키는 동시에 몰딩수지의 수축에 따라 부재가 몰딩수지쪽으로 휘어지는 것을 잡아주게 되어, 결국 반도체 패키지의 워피지를 크게 줄일 수 있는 효과를 얻어낼 수 있다.As described above, according to the method of manufacturing a semiconductor package according to the present invention by attaching the warpage absorbing means having a thermal expansion coefficient similar to that of the resin molded surface on the opposite side of the resin molded, to offset the shrinkage of the molding resin and molding As the resin shrinks, the member is bent toward the molding resin, so that the warpage of the semiconductor package can be greatly reduced.

Claims (2)

부재의 칩부착영역에 반도체 칩을 부착하는 공정과, 상기 반도체 칩의 본딩패드와 부재의 본딩영역간을 와이어로 본딩하는 공정과, 상기 반도체 칩과 와이어를 포함하는 부재의 상면을 수지로 몰딩하는 공정과, 상기 부재의 상면에 노출된 인출단자 부착용 랜드에 인출단자를 융착하는 공정을 포함하는 반도체 패키지 제조방법에 있어서,Attaching a semiconductor chip to a chip attaching region of the member, bonding a bonding pad of the semiconductor chip to a bonding region of the member with a wire, and molding a top surface of the member including the semiconductor chip and the wire with a resin. And a step of fusing the lead-out terminal to the land for attaching the lead-out terminal exposed on the upper surface of the member. 상기 수지와 유사한 열팽창계수를 갖는 워피지 흡수수단을 상기 부재의 저면에 분리 가능하게 미리 부착시켜서, 상기 칩 부착 공정과, 와이어 본딩공정과, 몰딩공정과, 인출단자 부착공정중에 발생하는 부재의 워피지를 상기 워피지 흡수수단에서 상쇄시킬 수 있도록 한 것을 특징으로 하는 반도체 패키지 제조 방법.The warpage absorbing means having a thermal expansion coefficient similar to that of the resin is previously attached to the bottom of the member so as to be detachable, so that the warpage of the member generated during the chip attaching step, the wire bonding step, the molding step, and the drawing terminal attaching step is performed. The semiconductor package manufacturing method characterized in that the sebum can be offset by the warpage absorbing means. 제 1 항에 있어서, 상기 반도체 패키지의 제조 완료후, 상기 워피지 흡수수단을 떼어내는 단계가 더 진행됨을 특징으로 하는 반도체 패키지 제조 방법.The method of claim 1, wherein after the manufacturing of the semiconductor package is completed, removing the warpage absorbing means is further performed.
KR1020000084889A 2000-12-29 2000-12-29 Method for manufacturing semiconductor package KR100649866B1 (en)

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