KR100638744B1 - Semiconductor memory device and method for fabricating the same - Google Patents

Abstract

The present invention is to provide a semiconductor memory device and a method of manufacturing the semiconductor memory device that can increase the cell efficiency by reducing the routing area as possible by reducing the RC delay by reducing the wiring resistance, the manufacturing method of the semiconductor memory device of the present invention And forming a first insulating layer on the semiconductor substrate having a core / peripheral region defined thereon, forming a bit line on the cell region and the core / peripheral region, respectively, and forming a second insulating layer on the entire surface including the bit line. Forming a connecting layer on the second insulating film in the core / peripheral region, forming a third insulating film on the entire surface including the connecting layer, and forming the third insulating film, the connecting layer, and the second insulating film. Etching to form a contact hole for opening an upper portion of the bit line formed in the core / peripheral region, and forming a contact plug embedded in the contact hole And forming a metal wire connected to the connection layer in parallel with the contact plug.

Capacitor, Metallization, RC Delay, Signal Attenuation, Plate, Connection Layer, Parallel Connection

Description

Semiconductor memory device and method of manufacturing the same {SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME}             

1 is a view showing the structure of a semiconductor memory device according to the prior art;

2 is a view illustrating signal attenuation minimization caused by RC delay according to the prior art;

3 is a diagram illustrating a structure of a semiconductor memory device according to an embodiment of the present invention;

4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention;

5 is a cross-sectional view taken along line II ′ of FIG. 4C;

6 illustrates minimizing signal attenuation due to RC delay in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 device isolation film

33: first interlayer insulating film 34: first landing plug contact

35a, 35b: bit line 36: second interlayer insulating film

37: second landing plug contact 38: etching barrier film

39: capacitor oxide 40: storage node

41a, 41b: dielectric film 42a: plate

42b: connecting layer 43: third interlayer insulating film

44: barrier metal 45: tungsten plug

46 metal wiring (M1)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor memory device in which a plate of a capacitor is used as a wiring layer in a core / periphery.

Generally, a DRAM is divided into a cell region (cell matrix) and a core / peripheral region. A bit line and a capacitor are formed in the cell region, and a bit line is formed in the core / peripheral region.

1 is a view showing the structure of a semiconductor memory device according to the prior art.

As shown in FIG. 1, an isolation region 12 is formed in a semiconductor substrate 11 defined as a cell region and a core / peripheral region, and a lower landing plug contact 14 is formed in an active region of the semiconductor substrate 11. And the upper landing plug contact 17 are vertically connected, and a capacitor including the storage node 19, the dielectric layer 20, and the plate 21 is connected to the upper landing plug contact 17. Here, the lower landing plug contact 14 and the upper landing plug contact 17 are insulated between the neighboring coplanar landing plug contacts by the first interlayer insulating film 13 and the second interlayer insulating film 16.

The bit line 15a is positioned below the capacitor, and the bit line 15b is formed in the core / peripheral region.

In FIG. 1, the storage node 19 of the capacitor has a concave structure by the capacitor oxide 18, and the bit line 15b of the core / peripheral region is the capacitor oxide 18, the third interlayer insulating film 22 and The second interlayer dielectric layer 16 is connected to the metal lines M1 and 25 through a contact hole formed by etching. Here, the metal wire 25 is connected to the bit line 15b through the barrier metal 23 and the tungsten plug 24 embedded in the contact hole.

As described above, in the prior art, the plate 21 of the capacitor is formed only in the cell region and the fuse region (not shown), and the plate is not used without a special role in the core / peripheral region. In other words, the number of layers in the core / peripheral region is limited to only gates, bit lines, metal interconnections, and contacts, so that the circuit area design can no longer reduce the routing area. This is inherently limited in increasing cell efficiency.

2 is a diagram illustrating signal attenuation minimization caused by RC delay according to the prior art.

Referring to FIG. 2, it can be seen that the signal attenuation x due to the RC delay is remarkably generated compared to the ideal signal IS.

The present invention has been proposed to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor memory device that can increase the cell efficiency by reducing the routing area to the maximum by reducing the RC delay by reducing the wiring resistance. There is this.

The semiconductor memory device of the present invention for achieving the above object is a semiconductor substrate having a cell region and a core / peripheral region defined, the first insulating film on the semiconductor substrate, the first and the second formed on the cell region and the core / peripheral region, respectively A bit line on an insulating layer, a second insulating layer covering the entire surface including the bit line, a storage node of a capacitor formed on the second insulating layer on the cell region, a dielectric layer and a plate stacked on the storage node, and the core / periphery A contact connected to a bit line of the core / peripheral region through a connection layer having a plate shape formed on the second insulation layer above the region, a third insulation layer on the connection layer, the third insulation layer, the connection layer, and a second insulation layer; A plug, and a metal wire connected in parallel with the connection layer while being connected to the contact plug, wherein the connection layer and the plate Is formed on the same plane, and the connection layer and the plate is characterized in that the same conductive film.

In the method of manufacturing a semiconductor memory device of the present invention, forming a first insulating layer on a semiconductor substrate in which a cell region and a core / peripheral region are defined, and forming bit lines on the cell region and the core / peripheral region, respectively. Forming a second insulating film on the entire surface including the bit line; forming a plate-like connection layer on the second insulating film in the core / peripheral region; and a third insulating film on the entire surface including the connection layer. Forming a contact hole to etch the third insulating layer, the connection layer, and the second insulating layer to open an upper portion of the bit line formed in the core / peripheral region, and to form a contact plug buried in the contact hole. And forming a metal wiring connected to the connection layer in parallel with the contact plug, wherein the forming of the connection layer is performed in a phase manner. Forming a storage node of a capacitor in the cell region on the second insulating layer, sequentially forming a dielectric film and a plate conductive film on the entire surface including the storage node, and selectively etching the plate conductive film and the dielectric film Forming a dielectric layer and a plate of a capacitor in a cell region and simultaneously forming the connection layer in the core / peripheral region, wherein the connection layer is selected from TiN, W, Ru, Ir, or Pt; Or a laminated film thereof.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a diagram illustrating the structure of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 3, the semiconductor memory device includes a semiconductor substrate 31 in which a cell region and a core / peripheral region are defined, a first interlayer insulating layer 33 on the semiconductor substrate 31, and a cell region and a core / peripheral region. A second interlayer insulating film 36 covering the entire surface including the bit lines 35a and 35b and the bit lines 35a and 35b on the first interlayer insulating film 33 respectively formed on the region, and a second interlayer insulating film above the cell region ( A connection layer formed on the storage node 40 of the capacitor formed on the capacitor 36, the dielectric film 41a and the plate 42a stacked on the storage node 40, and the second interlayer insulating layer 36 on the core / peripheral region. Bit line of the core / peripheral region through the second interlayer insulating film 43, the third interlayer insulating film 43, the connecting layer 42b, and the second interlayer insulating film 36 on the connection layer 42b. Tungsten plug 45 connected to 35b, and metal wires 46 and M1 connected to the tungsten plug 45 and connected in parallel with the connection layer 42b.

In FIG. 3, the storage node 40 of the capacitor is formed inside the opening formed by etching the etch barrier film 38 and the capacitor oxide 39 formed on the second interlayer insulating film 36, and thus, the core / peripheral. The tungsten plug 45 formed in the region penetrates to the capacitor oxide 39 inserted between the second interlayer insulating film 36 and the third interlayer insulating film 43.

As shown in FIG. 3, the connection layer 42b is formed on the same plane as the plate 42a formed in the cell region in the core / peripheral region, thereby connecting the connection layer 42b to the metal wiring 46 in parallel. . At this time, the connection layer 42b is formed at the same time as the plate 42a formed as the same conductive film as the plate 42a formed in the cell region.

As a result, in the present invention, the connection layer 42b formed in the core / peripheral region is connected in parallel with the metal wiring 46 through the tungsten plug 45.

4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

As shown in FIG. 4A, after the device isolation layer 32 is formed on the semiconductor substrate 31 in which the cell region and the core / peripheral region are defined, a word line (not shown) is formed on the semiconductor substrate 31. .

Next, a first interlayer insulating film 33 is formed over the semiconductor substrate 31, and the first interlayer insulating film 33 is selectively etched to form a contact hole for opening the active region of the cell region. The first landing plug contacts LPC1 and 34 are formed on the first landing plug contacts LPC1 and 34.

Next, a bit line 35a is formed in the cell region above the first landing plug contact 34. At this time, the bit line 35b is also formed in the core / peripheral region. At this time, although not shown, an interlayer insulating film may be formed under the bit lines 35a and 35b, and the bit lines 35a and 35b form a hard mask nitride film on the uppermost layer.

Next, after the second interlayer insulating layer 36 is formed on the entire surface including the bit lines 35a and 35b, the second interlayer insulating layer 36 is selectively etched to form an upper portion of the first landing plug contact 34 of the cell region. Form a contact hole for opening the. Then, a second landing plug contact 37 embedded in the contact hole is formed. In this case, the second landing plug contact 37 is formed between the bit lines 35a formed in the cell region and is vertically connected to the first landing plug contact 34. The second landing plug contact 37 is formed through an etch back or CMP process, and a material for forming the second landing plug contact 37 is a polysilicon film or a polysilicon film and an anti-oxidation film (Ti or TiN). Used) laminated structure.

Next, an etching barrier layer 38 and a capacitor oxide 39 are sequentially formed on the second landing plug contact 37. At this time, the etching barrier film 38 deposits a nitride film with a thickness of 200 GPa to 2000 GPa, and the capacitor oxide 39 deposits TEOS, BPSG and PSG with a thickness of 8000 GPa to 30000 GPa.

Next, a mask and an etching process are performed only in the cell region to form an opening (not shown) in which the storage node of the capacitor is to be formed. In this case, the opening opens the upper portion of the second landing plug contact 37.

Next, a cylindrical storage node 40 is formed in the opening.

In this case, the storage node 40 is formed by depositing a polysilicon film, TiN, W, Ru, Ir, Pt or RuO ₂ to a thickness of 50 kV to 500 kV, followed by a storage node separation process. Here, the storage node separation process uses an etch back or CMP process. After the storage node separation process as described above may be annealed in the 400 ℃ to 700 ℃ range to improve the quality of the storage node. Then, a cleaning process is further performed to remove the oxide film (or nitride film) generated after the annealing.

Next, the dielectric film 41 and the plate conductive film 42 are sequentially formed on the entire surface of the capacitor oxide 39 including the storage node 40.

Here, the dielectric layer 41 is formed by depositing a NO, ONO, HfO _2, Ta _2O5, TaON, STO or BST by using a CVD or ALD method, whereby, the thickness is 50Å~300Å range. After the deposition, heat treatment is performed in the range of 400 ° C. to 800 ° C. to improve the film quality.

Then, the plate conductive film 42 is deposited with polysilicon, TiN, W, Ru, Ir or Pt, and 100 m to 2000 m thick of these laminated films, and heat-treated at 400 ° C. to 800 ° C. to improve film quality after deposition. Proceed.

As shown in FIG. 4B, an etching process is performed on the plate conductive film 42 and the dielectric film 41 to form the dielectric film 41a and the plate 42a of the capacitor in the cell area and at the same time the core / peripheral area. The dielectric film 41b and the connection layer 42b are also formed.

Here, the dielectric film 41a and the plate 42a formed in the cell region constitute a capacitor, and the connection layer 42b formed in the core / peripheral region serves as an interconnection layer for parallel connection between subsequent metal lines. .

As described above, when the plate 42a of the capacitor is formed, the connection layer 42b is formed by remaining the same conductive film as the plate 42a of the cell region in the core / peripheral region. In this case, the plate 42a and the connection layer 42b are not connected to each other, and the connection layer 42b formed in the core / peripheral region has a plate shape instead of a line shape so that subsequent metal wires are connected in parallel to each other.

As shown in FIG. 4C, the third interlayer insulating film 43 is formed on the front surface including the plate 42a and the connection layer 42b to have a thickness of 1000 to 10000 microns, and then a CMP process is performed to improve the level difference.

Subsequently, the M1C process is performed. In this case, the M1C process is a process for forming a contact of a metal wiring, and comprises a contact hole process and a contact filling process. Only the M1C process in the core / peripheral region will be described below.

First, the contact hole process may be performed on the third interlayer insulating layer 43, the connection layer 42b, the dielectric layer 41b, the capacitor oxide 39, the etching barrier layer 38, and the second interlayer insulating layer 36 in the core / peripheral region. All of the portions are etched to open the upper part of the bit line 35b formed in the core / peripheral region. At this time, the etching target is in the range of 5000 kPa to 30000 kPa.

The contact buried process is a contact plug process, in which a barrier metal 44 is deposited on the entire surface including a contact hole having an open upper portion of the bit line 35b until the contact hole is completely filled on the barrier metal 44. A tungsten film is deposited. Subsequently, an etch back or CMP process is performed to form a barrier metal 44 and a tungsten plug 45 embedded in the contact hole.

The tungsten plug 45 penetrates to the connection layer 42b and is connected to the bit line 35b.

As described above, after the M1C process, a conductive film for metal wiring is deposited on the entire surface, and a mask and an etching process are performed on the conductive film to form metal wirings M1 and 46 connected to the tungsten plug 45.

5 is a cross-sectional view taken along line II ′ of FIG. 4C.

Referring to FIG. 5, in the core / peripheral region, the connection layer 42b is connected to the tungsten plug and connected in parallel with the metal wiring 46.

As described above, the present invention forms a connection layer 42b to apply the plate used in the cell region as a mounting line in the core / peripheral region, and the connecting layer 42b is connected by parallel connection with the metal wiring 46. Reduce the resistance of the wire This minimizes signal attenuation due to RC delay.

6 illustrates minimization of signal attenuation due to RC delay according to an embodiment of the present invention.

6, although the signal attenuation 52 occurs due to the RC delay compared to the ideal signal 51, RC delay reduction can be obtained by routing the connection layer in parallel with the metal wiring, thereby reducing the signal size. It can be seen that it is minimized. Reference numeral 53 denotes the attenuated signal according to the prior art.

As a result, the present invention can reduce the wiring resistance by leaving the plate of the cell region in the core / peripheral region as a connecting layer and connecting it in parallel with the metal wiring, thereby minimizing the RC delay of the critical signal. do.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of reducing the wiring resistance by connecting in parallel with the existing metal wiring by using the plate of the cell region as the connection layer of the core / peripheral region.

In addition, the present invention has the effect of increasing the cell efficiency by reducing the area of the core / peripheral area by minimizing the RC delay of the critical signal by minimizing the RC delay of the critical signal by using a connection layer in parallel with the metal wiring.

Claims (11)

Forming a first insulating layer on the semiconductor substrate having a cell region and a core / peripheral region defined therein; Forming bit lines on the cell region and the core / peripheral region, respectively; Forming a second insulating layer on the entire surface including the bit line; Forming a plate-type connection layer on the second insulating layer in the core / peripheral region; Forming a third insulating layer on the entire surface including the connection layer; Etching the third insulating layer, the connection layer, and the second insulating layer to form a contact hole for opening an upper portion of the bit line formed in the core / peripheral region; Forming a contact plug embedded in the contact hole; And Forming a metal wiring on the contact plug in parallel with the connection layer Method of manufacturing a semiconductor memory device comprising a. The method of claim 1, Forming the plate-shaped connection layer, Forming a storage node of a capacitor in the cell region on the second insulating layer; Sequentially forming a dielectric film and a plate conductive film on the entire surface including the storage node; And Selectively etching the plate conductive layer and the dielectric layer to form a dielectric layer and a plate of the capacitor in the cell region and simultaneously forming the plate-shaped connection layer in the core / peripheral region Method of manufacturing a semiconductor memory device comprising a. The method of claim 2, Forming the plate-shaped connection layer, The method of manufacturing a semiconductor memory device, further comprising the step of performing a heat treatment to improve the film quality of the connection layer. The method of claim 3, The heat treatment is, A process for producing a semiconductor memory device, characterized in that it proceeds in the range of 400 ° C to 800 ° C. The method according to claim 1 or 2, The plate-shaped connection layer, A method for manufacturing a semiconductor memory device, characterized in that it is selected from TiN, W, Ru, Ir, or Pt, or formed from a laminated film thereof. The method according to claim 1 or 2, The plate-shaped connection layer is formed to have a thickness of 100 mW to 2000 mW. A semiconductor substrate having a cell region and a core / peripheral region defined therein; A first insulating layer on the semiconductor substrate; Bit lines on the first insulating layer formed on the cell region and the core / peripheral region, respectively; A second insulating layer covering the entire surface including the bit line; A storage node of a capacitor formed on the second insulating layer on the cell region; A dielectric film and a plate stacked on the storage node; A connection layer having a plate shape formed on the second insulating layer on the core / peripheral region; A third insulating layer on the connection layer; A contact plug connected to the bit line of the core / peripheral region through the third insulating layer, the connection layer, and the second insulating layer; And A metal wiring connected to the contact plug and connected in parallel with the connection layer Semiconductor memory device comprising a. The method of claim 7, wherein And the connection layer and the plate are formed on the same plane. The method of claim 8, The connecting layer and the plate is a semiconductor memory device, characterized in that the same conductive film. The method of claim 9, The connecting layer and the plate, A semiconductor memory device, which is selected from TiN, W, Ru, Ir, or Pt, or a laminated film thereof. The method of claim 9, And the connecting layer and the plate are 100 mW to 2000 mW thick.

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