KR100636989B1 - High-speed latch comparator - Google Patents

Abstract

A high-speed latch comparator is provided to remove the phenomena missing the timing due to clock skew phenomena in high-speed and the delay time in the circuit by maintaining high output during half-period clock in which the latch comparator is not operated as a comparator. In a first latch circuit(110), a current path is connected to a power supply voltage and between a first node(Nd1) and a second node(Nd2), and a gate is cross-coupled with the other drain. In a second latch circuit(120), the current path is connected between the first node(Nd1) and a ground voltage and between the second node(Nd2) and the ground voltage, and a gate is cross-coupled with the other drain. In a first input circuit(130), the current path is connected between the first node(Nd1) and the ground voltage, is installed with the second latch circuit(120) in parallel and receives an input signal and a clock signal. In a second input circuit(140), the current path is connected between the second node(Nd2) and the ground voltage, is installed with the second latch circuit(120) in parallel and receives the input signal and the clock signal. In a third latch circuit(150), the current path is connected between the power supply voltage and the first output terminal and the second output terminal, a gate is cross-coupled with the other drain and is connected to the first latch circuit(110) in parallel. In a first common voltage maintaining unit(160), the current path is connected between the first output terminal and the ground voltage. The gate is connected to the gate of the first node(Nd1) and maintains the threshold voltage close to the common mode voltage. In a second common voltage maintaining unit(170), the current path is connected between the second output terminal and the ground voltage. The gate is connected to the gate of the second node(Nd2) and maintains the threshold voltage close to the common mode voltage.

Description

2-speed high speed latch comparator {HIGH-SPEED LATCH COMPARATOR}

1 is a circuit diagram showing a comparator according to one example of the prior art.

2 is a waveform diagram illustrating a differential output with respect to an input waveform of a general comparator.

3 is a circuit diagram showing a two-stage high speed latch comparator according to the present invention.

4 is a waveform diagram showing a differential output with respect to the input waveform of the two-stage high speed latch comparator according to the present invention.

* Explanation of symbols for the main parts of the drawings

110 and 120: first and second latch circuit portion

130, 140: first and second input circuit portion

150: third latch circuit portion

160,170: first and second common voltage holding unit

The present invention relates to a comparator of an A / D converter. In particular, the 'high' output always remains constant even during a half-period clock when the latch comparator does not operate as a comparator. The present invention relates to a two-speed high speed latch comparator capable of eliminating timing mismatches.

Analog-to-digital conversion technology (A / D converters) typically requires both analog and digital signal processing on the same chip. This is suitable for the completion of integrated circuits in MOS technology such as CMOS technology. The number of circuits has been improved for the design of converters with MOS devices.

Prior arts include Patent Application No. 1998-30447 (SMOS comparator for A / D converter) and Patent Application No. 2000-84523 (name: Auto-zero comparator with improved operating speed). The design of the comparator focuses on improving speed, improving reliability by reducing noise, and designing low power.

1 is a circuit diagram illustrating a comparator according to an example of the prior art, and FIG. 2 is a waveform diagram illustrating a differential output with respect to an input waveform of a general comparator.

The comparator includes first and second NMOS differential pair circuits MN1 and MN2, first and second latch circuits MN3 and MN4 (MP1 and MP2), reset circuit MP3, and output circuit INV1, INV2) and the like.

Gates of the first and second NMOS differential pair circuits MN1 and MN2 are respectively connected to a first input terminal to which the first input signal INPUT1 is applied and a second input terminal to which a second input signal INPUT2 is applied. In the reset circuit MP3, the clock signal CLK is applied to the gate, and the PMOS transistor MP3 having a channel formed between the nodes N1 and N2 corresponding to the drains of the NMOS transistors MN1 and MN2. Consists of

The first latch circuits MN3 and MN4 are formed of NMOS transistors MN3 and MN4 having drains connected to both ends of the reset circuit MP3 and the sources connected to each other. Gates of the NMOS transistors MN3 and MN4 are cross coupled to the drains of other NMOS transistors, respectively.

Next, the second latch circuit includes PMOS transistors MP1 and MP2 having sources connected to a power supply voltage and drains connected to the nodes N1 and N2, respectively. Gates of the PMOS transistors MP1 and MP2 are connected to nodes N1 and N2 corresponding to drains of other PMOS transistors, respectively, to form a cross shape.

The output circuit is composed of inverters INV1 and INV2 having input terminals respectively connected to nodes to which gates of the PMOS transistors are connected.

The comparator configured as described above is applied to the gates of the transistors MP3, MN6, and MN7, respectively, when the clock signal CLK, which transitions to the 'low' level in the tracking mode. As a result, only the PMOS transistor MP3 is turned on and the others MN6 and MN7 are turned off.

The PMOS transistor MP3 is turned on when the clock signal CLK transitioned to the 'low' level is applied and acts as a small resistance between the nodes N1 and N2. This is to balance the circuit and bias current is distributed to the NMOS transistors MN3 and MN4 of the cross-coupled latch circuit. This causes the entire circuit to act as an amplifier, increasing the gain.

Next, when the clock signal CLK transitions to the 'high' level, the PMOS transistor MP3 is turned off. The differential current from the NMOS transistors MN1 and MN2, which are input differential pairs, is due to the differential voltages of the nodes N1 and N2.

The difference voltage is amplified by a positive amplifier so that the voltages of the nodes N1 and N2 diverge toward a predetermined value by the input voltage to the reference voltage. As a result, the voltage levels of the nodes N1 and N2 are further amplified.

In the case of a general latch comparator, as shown in FIG. 2, when the output is 'high', the clock comes out as 'high' only for half a cycle and falls to 'low' for the other half cycle.

In this case, in a high speed comparator with one cycle falling to 1 ns, this causes an error due to clock skew.

Accordingly, an object of the present invention is to ensure that the 'high' output always comes out even during a half-period clock when the latch comparator does not operate as a comparator, so that timing is not corrected due to clock skew or delay time in a circuit during high speed operation. It is to provide a two-speed high speed latch comparator that can eliminate the phenomenon.

Technical means of the present invention for achieving the above object, in the comparator of the analog-to-digital converter: the current path is connected between the power supply voltage and the first node and the second node, respectively, the gate terminal is connected to the other drain end A first latch circuit portion that responds to the response; A second latch circuit unit having a current path connected between the first node and the ground voltage and a second node and the ground voltage, respectively, and having a gate terminal connected to the other drain terminal to respond; A first input circuit unit connected to a current path between the first node and a ground voltage and installed in parallel with a second latch circuit unit to receive and respond to an input signal and a clock signal, respectively; A second input circuit unit connected to the current path between the second node and the ground voltage and installed in parallel with the second latch circuit unit to receive and respond to input signals and clock signals, respectively; A third latch circuit unit having a current path connected between the power supply voltage and the first output terminal and the second output terminal, respectively, the gate terminal of which is connected to the other drain terminal, and connected in parallel with the first latch circuit unit; A first common voltage maintenance unit connected to the first output terminal and the ground voltage, and having a gate terminal connected to the first node to maintain a threshold voltage close to a common mode voltage; And a second common voltage maintaining unit connected to a current path between the second output terminal and the ground voltage, and having a gate terminal connected to the second node in response to maintain a threshold voltage close to a common mode voltage. It is done.

Specifically, the first latch circuit unit may include: a first PMOS transistor having a current path connected between the power supply voltage and the first node and having a gate terminal connected to the second node; And a second PMOS transistor having a current path connected between the power supply voltage and the second node and having the first node and a gate terminal connected thereto, wherein the second latch circuit part includes a current between the first node and the ground voltage. A first NMOS transistor having a passage connected thereto and a gate end connected to the second node; And a second NMOS transistor having a current path connected between the second node and a ground voltage and having the first node and a gate terminal connected thereto.

The first input circuit unit may further include: a third NMOS transistor having a current path connected to the first node and connected in parallel with the first NMOS transistor to receive a clock signal; And a fourth NMOS transistor connected between a source terminal of the third NMOS transistor and a ground voltage and receiving an input signal, wherein the second input circuit unit includes a current path connected to the second node. A fifth NMOS transistor connected in parallel with the NMOS transistor to receive a clock signal; And a sixth NMOS transistor connected with a current path between the source terminal of the fifth NMOS transistor and a ground voltage and receiving an input signal.

The third latch circuit unit may include: a third PMOS transistor having a current path connected between the power supply voltage and the first output terminal and having a second output terminal and a gate terminal connected thereto; And a fourth PMOS transistor having a current path connected between the power supply voltage and the second output terminal and having a first output terminal and a gate terminal connected thereto, wherein the first common voltage holding unit has a current path connected to the first output terminal. A seventh NMOS transistor, the seventh NMOS transistor being responsive to the signal of the first node; And an eighth NMOS transistor having a current path connected between a source terminal of the seventh NMOS transistor and a ground voltage and responsive to an output signal of the first node. The second common voltage holding unit includes a current at the second output terminal. A ninth NMOS transistor coupled to the passage but responsive to a signal from a second node; And a tenth NMOS transistor connected to a current path between the source terminal of the ninth NMOS transistor and a ground voltage, and responding to a signal of a second node.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram illustrating a two-stage high speed latch comparator according to the present invention. FIG. 4 is a waveform diagram showing a differential output with respect to an input waveform of the two-stage high speed latch comparator according to the present invention. The second latch circuit unit 120, the first input circuit unit 130, the second input circuit unit 140, the third latch circuit unit 150, the first common voltage holding unit 160, and the second common voltage holding unit ( 170).

The first latch circuit unit 110 is configured such that a current path is connected between the power supply voltage VDD, the first node Nd1, and the second node Nd2, and a gate terminal is connected to the other drain terminal to respond. The second latch circuit unit 120 has a current path connected between the first node Nd1 and the ground voltage GND and the second node Nd2 and the ground voltage GND, and a gate terminal is connected to the other drain terminal. The first input circuit unit 130 has a current path connected between the first node Nd1 and the ground voltage GND, and is installed in parallel with the second latch circuit unit 120 to provide an input signal. In response to the inp and the clock signal clk, the second input circuit 140 is connected to the current path between the second node Nd2 and the ground voltage GND. It is installed in parallel with 120 to receive and respond to the input signal (inn) and the clock signal (clk), respectively It can control.

In the third latch circuit unit 150, a current path is connected between the power supply voltage VDD, the first output terminal (outp), and the second output terminal (outn), and a gate terminal is connected to the other drain terminal. It is configured to be connected in parallel with the circuit unit 110, the first common voltage holding unit 160 is a current path is connected between the first output terminal (outp) and the ground voltage (GND), the first node (Nd1) Is connected to the gate terminal in response to maintain a threshold voltage close to the common mode voltage, and the second common voltage holding unit 170 is connected between the second output terminal (outn) and the ground voltage (GND). A current path is connected to the gate terminal, but a gate terminal is connected to the second node Nd2, and is configured to maintain a threshold voltage close to the common mode voltage.

Looking at the detailed configuration of each of the circuit blocks as follows.

The first latch circuit unit 110 includes a first PMOS transistor MP1 having a current path connected between the power supply voltage VDD and the first node Nd1 and having a gate terminal connected to the second node Nd2, and A current path is connected between the power supply voltage VDD and the second node Nd2, and the second PMOS transistor MP2 is connected to the first node Nd1 and the gate terminal thereof. ) Is a first NMOS transistor MN1 having a current path connected between the first node Nd1 and a ground voltage GND, and having a gate terminal connected to the second node Nd2, and the second node Nd2. And a second NMOS transistor MN2 having a current path connected between the ground voltage GND and the first node Nd1 and a gate terminal thereof.

A third NMOS transistor MN3 having a current path connected to the first node Nd1 and connected in parallel with a first NMOS transistor MN1 to receive a clock signal clk; And a fourth NMOS transistor MN4 having a current path connected between the source terminal of the third NMOS transistor MN3 and the ground voltage GND and receiving an input signal inp, and the second input circuit unit 140. A fifth NMOS transistor MN5 connected with a current path to the second node Nd2 and connected in parallel with a second NMOS transistor MN2 to receive a clock signal clk, and the fifth NMOS transistor MN5. The sixth NMOS transistor MN6 is connected to a current path between the source terminal and ground voltage GND, and receives an input signal inn.

The third latch circuit unit 150 includes a third PMOS transistor MP3 having a current path connected between the power supply voltage VDD and the first output terminal outp and having a second output terminal and a gate terminal connected thereto. And a fourth PMOS transistor (MP4) connected between the power supply voltage (VDD) and the second output terminal (outn) and connected with the first output terminal (outp) and the gate terminal, and maintaining a first common voltage. The unit 160 has a current path connected to the first output terminal (outp), and the source terminal and the ground of the seventh NMOS transistor MN7 and the seventh NMOS transistor MN7 in response to a signal of the first node Nd1. A current path is connected between the voltage GND and the eighth NMOS transistor MN8 responds to an output signal of the first node Nd1. The second common voltage holding unit 170 includes the second output terminal outn. Is connected to the current path, but responds to the signal of the second node Nd2, the ninth NMOS transistor MN9. And a tenth NMOS transistor MN10 that connects a current path between the source terminal of the ninth NMOS transistor MN9 and the ground voltage GND and responds to a signal of the second node Nd2.

The latch comparator compares analog input signals and amplifies them to a level of signal level that can be processed in a digital circuit by 'high' or 'low', and is generally applied to an A / D converter so that the final It is located at the stage.

In the case of a general latch comparator, the 'high' signal outputted as shown in FIG. 2 described above is supplied with a digital 'high' signal level of 1.8 V, for example, only for a half cycle of a clock, and a voltage of 0 V or a common mode voltage (for a remaining half cycle clock). 1.8V supply voltage is 0.9V). In the case of the high speed comparator, one cycle becomes shorter and may cause errors due to clock skew in high speed operation.

In order to solve this problem, the latch comparator includes a first stage circuit unit including a first latch circuit unit 110, a second latch circuit unit 120, a first input circuit unit 130, and a second input circuit unit 140; The combination of the two-stage circuit unit consisting of the third latch circuit unit 150, the first common voltage holding unit 160 and the second common voltage holding unit 170, 'high' even during the half-cycle clock that does not operate the comparator By keeping the output constant, the period is shortened during high-speed operation, eliminating timing mismatches due to clock skew or delay time in the circuit.This allows the final digital output to have a 50% duty cycle Spaced, and the lowest digital LSB output (not shown).

That is, in the flash A / D converter, a comparator generally uses a latch comparator for high speed operation. In the present invention, a positive feedback circuit composed of input transistors MN4 and MN6, clock control switches MN3 and MN5, and an inverter chain is used. (MN1, MN2, MP1, MP2), and in order to reduce the error rate due to clock skew or delay time in the circuit during high-speed operation, the third latch circuit unit 150 and the first and second common parts are arranged in the rear stage. The circuit of the voltage holding parts 160 and 170 was added.

In addition, the latch comparator samples the output of the front end amplifier and converts the value to the voltage level required by the digital stage. In the present invention, a high speed latch comparator is used after the second end amplifier has a latch. Cascode type amplifies the signal to enable digital signal processing at the 0.7V voltage level at the front and reduces the error rate. The formula for calculating the error rate is shown in Equation 1.

Where A1 represents the voltage gain of the front-end amplifier, A2 represents the gain of the first latch, T1 and T2 represent the positive feedback operation time (T / 2) of each latch, and τ1 and τ2 represent the refresh time of each latch.

Then, it looks at the detailed configuration and operation of the two-stage latch comparator according to the present invention.

First, the circuit configuration of the two-stage high speed latch comparator consists of the fourth and sixth NMOS transistors MN4 and MN6 as input switches, the third and fifth NMOS transistors MN3 and MN5 as clock control switches, and a positive feedback chain. The first and second latch circuits MP1, MP2, MN1, and MN2 have a third latch circuit (MP3, MP4) at the rear end to reduce the error rate due to clock skew or delay time in the circuit during high speed operation. Common voltage holding units MN7 to MN10 were added.

In the operation of the latch comparator, when the clock clk is 1, the third and fifth NMOS transistors MN3 and MN5 are turned on, and the input signals (eg, through the fourth and sixth NMOS transistors MN4 and MN6) are turned on. inp and inn enter the positive feedback circuits MP1, MP2, MN1, and MN2 composed of inverter chains.

When the next clock clk is 0, the third and fifth NMOS transistors MN3 and MN5 are turned off, and the signal input during the previous half cycle is instantaneously amplified by the positive feedback circuits MP1, MP2, MN1 and MN2. It comes out to the output terminals Nd1 and Nd2 of the comparator and must be returned again within half a period of the clock clk.

On the other hand, in general, the latch comparator is positioned at the end of the analog circuit in order to amplify the analog signal to a signal level that can be processed by the digital circuit. Only when the clock is zero, the signal comes out at a supply voltage of 1.8V, the digital 'high' signal level, and when the clock is 1, it drops to a certain voltage to 0V or the common-mode voltage (0.9V for the 1.8V supply). In the case of the high speed comparator, one cycle becomes shorter, and the output of the comparator remains 'high' only for a half cycle of the clock, which may cause errors due to clock skew in high speed operation. In fact, when applied to a high speed A / D converter, even in the lowest LSB stage, even if signal synchronization occurs, the code does not come out correctly and an error occurs.

In order to eliminate such a phenomenon, the circuits MP3 to MN10 are added to the rear stage like the comparator of the present invention and are configured in two stages.

By connecting two transistors in series such as the seventh to tenth NMOS transistors MN7 to MN8 and MN9 to MN10 to maintain the threshold voltage close to the common mode voltage, the output of the comparator (outp, outn) as shown in FIG. By keeping the voltage as a 'high' signal or a 'low' signal even when the clock is inactive with respect to the clock clk, the signal 'high' or 'low' is continuously generated for all the clocks clk.

For example, when the 'low' signal enters the inputs of the seventh and eighth NMOS transistors MN7 and MN8, and the ninth and tenth NMOS transistors MN9 and MN10 enter the 'high' signal, the seventh. And the eighth NMOS transistors MN7 and MN8 are turned off, and the ninth and tenth NMOS transistors MN9 and MN10 are turned on so that a 'low' signal 0V is output to the second output terminal (outn). Since the third PMOS transistor MP3 is turned on and the fourth PMOS transistor MP4 is turned off, the high voltage signal 1.8V is output to the first output terminal outp.

As a result, the period is shortened during high-speed operation, eliminating timing mismatch due to clock skew or delay time in the circuit.This resulted in the final digital output having 50% duty cycle and accurate equal intervals. However, accurate digital output is also provided.

While specific embodiments of the present invention have been described and illustrated above, it will be apparent that the present invention may be embodied in various modifications by those skilled in the art. Such modified embodiments should not be understood individually from the technical spirit or the prospect of the present invention, but should fall within the claims appended to the present invention.

Therefore, in the present invention, the 'high' output always remains constant even during the half-period clock when the latch comparator does not operate as a comparator, thereby preventing timing mismatch due to clock skew or delay time in a circuit during high speed operation. This eliminates the advantage of providing an accurate and reliable latch comparator even at high speeds.

Claims (8)

In the comparator of an analog-to-digital converter: A first latch circuit unit connected to a power supply voltage and a current path between the first node and the second node, respectively, and having a gate end connected to the other drain end thereof (cross coupling); A second latch circuit unit having a current path connected between the first node and the ground voltage and a second node and the ground voltage, respectively, and having a gate terminal connected to the other drain terminal to respond; A first input circuit unit connected to a current path between the first node and a ground voltage and installed in parallel with a second latch circuit unit to receive and respond to an input signal and a clock signal, respectively; A second input circuit unit connected to the current path between the second node and the ground voltage and installed in parallel with the second latch circuit unit to receive and respond to input signals and clock signals, respectively; A third latch circuit unit having a current path connected between the power supply voltage and the first output terminal and the second output terminal, respectively, the gate terminal of which is connected to the other drain terminal, and connected in parallel with the first latch circuit unit; A first common voltage maintaining unit connected to a current path between the first output terminal and a ground voltage, and having a gate terminal connected to the first node in response to maintain a threshold voltage close to a common mode voltage; And A second common voltage holding unit connected to the second output terminal and a ground voltage, and having a gate terminal connected to the second node in response to maintain a threshold voltage close to a common mode voltage; 2-speed high speed latch comparator. The method of claim 1, wherein the first latch circuit portion, A first PMOS transistor having a current path connected between the power supply voltage and the first node and having a gate terminal connected to the second node; And a second PMOS transistor having a current path connected between the power supply voltage and the second node and having the first node and a gate terminal connected thereto. The method of claim 1, wherein the second latch circuit portion, A first NMOS transistor having a current path connected between the first node and a ground voltage and a gate end of the second node; And a second NMOS transistor having a current path connected between the second node and a ground voltage and the first node and a gate terminal thereof connected to each other. The method of claim 1, wherein the first input circuit unit, A third NMOS transistor having a current path connected to the first node but connected in parallel with the first NMOS transistor to receive a clock signal; And a fourth NMOS transistor connected between a source terminal of the third NMOS transistor and a ground voltage and receiving an input signal. The method of claim 1, wherein the second input circuit unit, A fifth NMOS transistor having a current path connected to the second node but connected in parallel with a second NMOS transistor to receive a clock signal; And a sixth NMOS transistor coupled to a current path between the source terminal and the ground voltage of the fifth NMOS transistor and receiving an input signal. The method of claim 1, wherein the third latch circuit portion, A third PMOS transistor having a current path connected between the power supply voltage and a first output terminal and having a second output terminal and a gate terminal connected thereto; And a fourth PMOS transistor having a current path connected between the power supply voltage and the second output terminal and having the first output terminal and the gate terminal connected thereto. The method of claim 1, wherein the first common voltage holding unit, A seventh NMOS transistor having a current path connected to the first output terminal and responsive to a signal of a first node; And an eighth NMOS transistor coupled to a current path between the source terminal of the seventh NMOS transistor and a ground voltage and responsive to an output signal of the first node. The method of claim 1, wherein the second common voltage holding unit, A ninth NMOS transistor having a current path connected to the second output terminal and responsive to a signal of a second node; And a tenth NMOS transistor coupled with a current path between a source terminal of the ninth NMOS transistor and a ground voltage and responsive to a signal of a second node.

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