KR100345682B1 - Comparator for poerating at a high speed - Google Patents

Abstract

The present invention is to provide a comparison device that is implemented in a non-linear amplification and pipeline structure through a positive feedback structure to perform a high-speed comparison operation, for which the present invention is to compare in response to a control signal first and second Storage means for receiving and storing an input signal; First amplifying means for receiving a signal output from the storage means and amplifying the first signal in response to a reset signal which is an inverted control signal; And second amplifying means for receiving a first amplified signal output from the first amplifying means, a second amplifying signal, and finally outputting first and second output signals in response to the latch signal, the inverted reset signal. .

Description

Comparator for poerating at a high speed}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator for amplifying a voltage difference between two input signals and performing a comparison operation on the two signals. In particular, the present invention relates to an analog-digital converter (ADC). The present invention relates to a comparison device for high speed operation.

As is well known, ADCs are the devices required to interface the analog external world and the internal digital world in measurement systems, microcontroller units (MCUs), digital signal processors (DSPs), and communication chips. It has a comparator inside to convert it to. At this time, since the operation speed of the comparator directly affects the performance of the ADC, a comparator capable of faster operation is required to implement a high speed ADC.

Conventional comparators are mainly implemented using Bipolar Junction Transistors (BJTs) because of the low transconductance of metal oxide semiconductors (MOS) and mismatches between devices. There is a problem that the manufacturing cost is high because the consumption and implementation area becomes large.

In addition, another conventional comparator may be implemented using a single ended differential amplifier or a fully differential amplifier, or by cascading the differential amplifiers. In this conventional comparator, a linear amplification is proportional to the transconductance and the output resistance of the MOS, and thus, when a given resolution is high, a gain (that is, an amplification factor) must be large, thereby causing an operation speed to be slow.

The present invention has been made to solve the above problems, the object of the present invention is to implement a non-linear amplification and pipeline structure through the positive feedback structure to provide a comparison device performing a fast comparison operation.

1A is a block diagram of one embodiment of a comparator in accordance with the present invention;

FIG. 1B is an exemplary waveform diagram of a control signal (SAMPLE) for controlling the comparator of FIG. 1A according to the present invention. FIG.

2 is an exemplary circuit diagram of a first amplifier of a comparator according to the present invention.

3 is an exemplary circuit diagram of a second amplifier of a comparator according to the present invention;

* Description of the main parts of the drawing

200: reset unit 210: first feedback unit 220: second feedback unit

230: potential stabilization unit 240: bias unit

250, 260: output unit

300: latch portion

The present invention for achieving the above object, the storage means for receiving and storing the first and second input signal to be compared in response to the control signal; First amplifying means for receiving a signal output from the storage means and amplifying the first signal in response to a reset signal which is an inverted control signal; And second amplifying means for receiving a first amplified signal output from the first amplifying means, second amplifying the second amplifying signal, and finally outputting first and second output signals in response to the latch signal which is an inverted reset signal. Is done.

FIG. 1A is an embodiment block diagram of a comparator according to the present invention, and FIG. 1B is an embodiment waveform diagram of a control signal SAMPLE for controlling the comparator of FIG. 1A according to the present invention.

1A and 1B, the comparator of the present invention receives the two signals INP and INN to be compared in response to the control signal SAMPLE and stores the sample and hold unit 100 and the inverted control. A first amplifier 120 for receiving and amplifying signals INP1 and INN1 output from the sample and hold unit 100 in response to a reset signal RESET which is a signal SAMPLE, and an inverted reset signal RESET A second amplification to receive and amplify the first amplified signals OUTN1 and OUTP1 output from the first amplifier 120 in response to the latch signal LATCH. The unit 140 is made.

When the control signal SAMLE input from the outside is "high" (section A in FIG. 1B), the input signals INP and INN are stored in the sample and hold unit 100, and the second amplifier unit ( 140 outputs the previously compared value as final output signals OUTP and OUTN in response to the latch signal LATCH of "high". At this time, the first amplifier 120 is reset to the reset state by the reset signal RESET of "low".

When the control signal SAMPLE is " low " (section B of FIG. 1B), the sample and hold unit 100 retains the input signals INP and INN, and the second amplifier 140 The operation is stopped by the latch signal LATCH of "low". In this case, the first amplifier 120 receives the signals INP1 and INN1 stored in the sample and hold unit 100 in response to the reset signal RESET of “high” and performs an amplification operation for comparison. When the control signal SAMLE is "high" again and the reset signal RESET is "low", the amplified signals OUTN1 and OUTP1 are output to the second amplifier 140.

2 is an exemplary circuit diagram of a first amplifier of a comparator according to the present invention, and a capacitor-connected NMOS for coupling and transferring signals INP1 and INN1 output from a sample and hold unit 100. Accurate comparison operation between the transistors N0 and N1 and the PMOS transistors P0 and P1 respectively connected to the power supply voltage terminals and receiving the input signals coupled from the capacitor-connected NMOS transistors N0 and N1 to their gates, respectively, are performed. The reset unit 200 resets and drives the amplifier in response to the reset signal RESET, the first feedback unit 210 for feedback operation in response to the drain voltage of the PMOS transistor P0, and the PMOS transistor P1. A second feedback unit 220 for feedback operation in response to the drain voltage of Equation 8), a potential stabilizer 230 for connecting the first and second feedback units 210 and 220 to stabilize the potential of the signal, Connected between the power supply voltage terminal and the ground power supply terminal A bias unit 240 for supplying a constant bias voltage, and an output unit 250 or 260 for driving output signals OUTN1 and OUTP1 in response to the drain voltage of the PMOS transistor P0 and the bias voltage. .

In detail, as shown in FIG. 2, the reset unit 200 is connected between the gate terminal and the drain terminal of the PMOS transistor P0 and receives the reset signal RESET through the gate. A PMOS transistor P3 connected between the gate terminal and the drain terminal of the PMOS transistor P1 and receiving the reset signal RESET to the gate, and one side of the drain terminal of the PMOS transistor P1 is connected to the gate, and the reset signal to the gate. One side is connected to the PMOS transistor P4 receiving the (RESET) input and the drain terminal of the PMOS transistor P0, and the PMOS transistor P5 receiving the reset signal RESET to the gate.

In addition, one side of the first feedback unit 210 is connected to the power supply voltage terminal, and the NMOS transistor N2 to which the drain voltage of the PMOS transistor P0 is input to the gate is connected to the drain terminal of the PMOS transistor P1. And an NMOS transistor N3 having a gate terminal connected to the other side of the PMOS transistor P4 and a power supply voltage terminal and the other side of the PMOS transistor P4, and an NMOS transistor having a gate terminal connected to the other side of the NMOS transistor N2. N4 and the NMOS transistor N5 connected between the other side of the NMOS transistor N2 and the ground power supply terminal and receiving the bias voltage to the gate, and between the other side and the ground power supply terminal of the PMOS transistor P4, the gate The NMOS transistor N6 receives a low bias voltage, and the second feedback unit 220 has an NMOS transistor having one side connected to a power supply voltage terminal and a drain voltage of the PMOS transistor P1 being input to the gate. N7 and an NMOS transistor N8 having one side connected to the drain terminal of the PMOS transistor P0 and the gate end connected to the other side of the PMOS transistor P5, and a power supply voltage terminal and the other side of the PMOS transistor P5. An NMOS transistor N9 connected to the other side of the NMOS transistor N7 and an NMOS transistor N10 connected between the other side of the NMOS transistor N7 and a ground power supply terminal and receiving a bias voltage to the gate; The NMOS transistor N11 is connected between the other side of the PMOS transistor P5 and the ground power supply terminal and receives a bias voltage through a gate, and the other side of the NMOS transistor N3 and the other side of the NMOS transistor N8 are connected to each other. It is configured to be.

The potential stabilization unit 230 is connected between the other side of the NMOS transistor N3 and the ground power supply terminal, and the gate end of the NMOS transistor N12 and the NMOS transistor N8 connected to the other side of the NMOS transistor N2. The NMOS transistor N13 is connected between the other side and the ground power supply terminal, and the gate terminal is connected to the other side of the NMOS transistor N7.

The output unit 250 is connected between a power supply voltage terminal and an output terminal for outputting the output signal OUTN1, an NMOS transistor N14 to which a drain voltage of the PMOS transistor P0 is applied to the gate, and an output signal OUTN1. It is connected between the output terminal and the ground power supply terminal for outputting the NMOS transistor (N15) is applied a bias voltage to the gate, the output unit 260 is connected between the power supply terminal and the output terminal for outputting the output signal (OUTP1), NMOS transistor N16 to which the drain voltage of the PMOS transistor P1 is applied to the gate, and NMOS transistor N17 to which a bias voltage is applied to the gate, connected between the output terminal and the ground power supply terminal which output the output signal OUTP1. .

Finally, the bias unit 240 is composed of a PMOS transistor P6, an NMOS transistor N18, and an NMOS transistor N19 which are sequentially connected between a power supply voltage terminal and a ground power supply terminal, and the PMOS transistor P6 is a gate. The terminal and the drain terminal are commonly connected, the gate terminal of the NMOS transistor N18 is connected to the gate terminal and the drain terminal of the commonly connected PMOS transistor P6, and the drain terminal and the gate terminal of the NMOS transistor N19 are commonly connected. It is composed.

Referring to Figure 2 looks at the operation of the first amplifier.

When the reset signal RESET is input to "low", the PMOS transistors P2, P3, P4, and P5 of the reset unit 200 are all turned on to gate the PMOS transistors P0 and P1. When the voltages at the stage and the drain terminal are made equal to a constant voltage, and the reset signal RESET is input to "high", all of the PMOS transistors P2, P3, P4, and P5 of the reset unit 200 are turned off. -off), the input signals INP1 and INN1 are transferred to the PMOS transistors P0 and P1 through the capacitor-connected NMOS transistors N0 and N1, respectively.

On the other hand, when the input signal INP1 is greater than the input signal INN1, the drain voltage of the PMOS transistor P0 is smaller than the drain voltage of the PMOS transistor P1. The drain voltage of the PMOS transistor P0 is controlled by the gate of the NMOS transistor N3 through the NMOS transistor N2, the NMOS transistor N5, the NMOS transistor N4, and the NMOS transistor N6 of the first feedback unit 210. The drain voltage of the NMOS transistor N3, that is, the drain voltage of the PMOS transistor P1 is increased. The drain voltage of the PMOS transistor P1 is gated through the NMOS transistor N7, the NMOS transistor N10, the NMOS transistor N9, and the NMOS transistor N11 of the second feedback unit 220. The drain voltage of the NMOS transistor N8, that is, the drain voltage of the PMOS transistor P0 is further reduced. When the drain voltage of the PMOS transistor P0 is smaller than the drain voltage of the PMOS transistor P1, the difference is further amplified by the first and second feedback units 210 and 220, thereby increasing the difference. When the drain voltage of the PMOS transistor P1 is stabilized to some extent, the output voltages OUTN1 and OUTP1 are outputted through the NMOS transistors N14, N15, N16, and 17 of the output units 250 and 260.

3 is a circuit diagram illustrating a second amplifier of a comparator according to the present invention. The PMOS transistor is connected to a power supply voltage terminal and receives the signals OUTP1 and OUTN1 output from the first amplifier 120 as a gate, respectively. (P7, P8), a latch unit 300 for latching and outputting the output signals OUTP and OUTN in response to the latch signal LATCH, and a feedback operation in response to the drain voltage of the PMOS transistor P7. A first feedback part 310, a second feedback part 320 for feedback operation in response to the drain voltage of the PMOS transistor P8, and the first and second feedback parts 310 and 320 to be connected to each other. A potential stabilization unit 330 for stabilizing a potential, a bias unit 340 connected between a power supply voltage terminal and a ground power supply terminal for supplying a constant bias voltage, a drain voltage of the PMOS transistor P7, and the bias Drives output signals OUTN and OUTP in response to voltage The latch unit 300 is connected to the drain terminal of the PMOS transistor P7, and has an NMOS transistor N21 and a PMOS transistor (L21) for receiving a latch signal LATCH through a gate. The NMOS transistor N20 is connected to the drain terminal of P8 and receives a latch signal LATCH through a gate.

As shown in the figure, the second amplifier is the same as the configuration of the first amplifier except that the reset unit 200 of the first amplifier is replaced by the latch unit 300, Detailed description will be omitted.

An operation of the second amplifying unit will be described with reference to FIG. 3.

When the latch signal LATCH is input to "low", the second amplifier is not operated, and when the latch signal LATCH is input to "high", the NMOS transistors N20 and N21 of the latch unit 300 are turned on. It is turned on and latched.

When a differential signal is applied to the signals OUTP1 and OUTN1 output from the first amplifier 120, the drain voltages of the PMOS transistors P7 and PMOS transistors P8 are PMOS transistors P7 and PMOS. It is determined by the gate voltage of the transistor P8. For example, when the gate voltage of the PMOS transistor P7 is greater than the gate voltage of the PMOS transistor P8, the drain voltage of the PMOS transistor P7 becomes smaller than the drain voltage of the PMOS transistor P8. The drain voltage of the PMOS transistor P7 passes through the NMOS transistor N22, the NMOS transistor N25, the NMOS transistor N24, and the NMOS transistor N26 of the first feedback unit 310 to the gate of the NMOS transistor N23. The drain voltage of the NMOS transistor N23, that is, the drain voltage of the PMOS transistor P8 is higher. The drain voltage of the PMOS transistor P8 is transferred to the NMOS transistor N28 through the NMOS transistor N27, the NMOS transistor N30, the NMOS transistor N29, and the NMOS transistor N31 of the second feedback unit 320. The drain voltage of the NMOS transistor N28 is further reduced by being applied to the gate terminal.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, a comparator having a faster comparison speed can be realized by including a sample and hold part driven by a pipeline in response to a control signal, and first and second amplification parts, and first and second amplification. Non-linear amplification by implementing the feedback structure has an excellent effect of performing a comparative operation with a smaller area and faster.

In addition, fast comparison of the input signal enables high speed ADCs.

Claims (10)

Storage means for receiving and storing first and second input signals to be compared in response to a control signal input from the outside and outputting the first and second signals; First amplifying means for receiving and amplifying a signal output from the storage means in response to a reset signal which is an inverted signal of the control signal through a first inverting means; And In response to the latch signal which is an inverted signal of the reset signal through the second inverting means, the first amplified signal outputted from the first amplifying means is received and amplified for the second time, and then the first and second output signals are finally outputted. A second amplifying means, The first amplification means, Capacitor-connected first and second NMOS transistors for coupling and transferring the first and second signals output from the storage means, respectively; First and second PMOS transistors connected to a power supply voltage terminal and receiving input signals coupled to the gates from the first and second NMOS transistors connected to the capacitors, respectively; Reset means for reset driving the first amplifying means in response to the reset signal for accurate comparison operation of the comparison device; First feedback means for feedback operation in response to a drain voltage of the first PMOS transistor; Second feedback means for feedback operation in response to a drain voltage of the first PMOS transistor; Potential stabilization means connected to said first and second feedback means for stabilizing a potential of a signal; Bias voltage supply means connected between a power supply voltage terminal and a ground power supply terminal for supplying a constant bias voltage; And First and second output means for driving the first and second output signals in response to the drain voltage and the bias voltage of the first PMOS transistor Comparing device for high speed operation comprising a. The method of claim 1, When the control signal is at the "high" level, the storage means receives and stores the first and second input signals, the first amplification means resets the first amplification operation by the reset signal, and A second amplifying means sends out a signal previously amplified by the latch signal to the first and second output signals, When the control signal is at the "low" level, the storage means maintains the stored first and second input signals as they are, and the first amplifying means is stored in the storage means by the reset signal. Outputs the signal amplified by the first amplifying operation to the second amplifying means when the control signal transitions back to a “high” level after receiving the second input signal; And the amplifying means stops the second amplifying operation by the latch signal. The method of claim 1, wherein the reset means, A third PMOS transistor connected between the gate terminal and the drain terminal of the first PMOS transistor and receiving the reset signal through a gate; A fourth PMOS transistor connected between the gate terminal and the drain terminal of the second PMOS transistor and receiving the reset signal through a gate; A fifth PMOS transistor having one side connected to a drain terminal of the second PMOS transistor and receiving the reset signal through a gate; And A sixth PMOS transistor having one side connected to a drain terminal of the first PMOS transistor and receiving the reset signal through a gate; Comparing device for a high speed operation comprising a. The method of claim 3, wherein the first feedback means, A third NMOS transistor having one side connected to a power supply voltage terminal and receiving a drain voltage of the first PMOS transistor as a gate; A fourth NMOS transistor having one side connected to a drain end of the second PMOS transistor and a gate end connected to the other side of the fifth PMOS transistor; A fifth NMOS transistor connected between a power supply voltage terminal and the other side of the fifth PMOS transistor, and a gate end thereof connected to the other side of the third NMOS transistor; A sixth NMOS transistor connected between the other side of the third NMOS transistor and a ground power supply terminal and receiving the bias voltage through a gate; And A seventh NMOS transistor connected between the other side of the fifth PMOS transistor and a ground power supply terminal and receiving the bias voltage through a gate; Comparing device for a high speed operation comprising a. The method of claim 4, wherein the second feedback means, An eighth NMOS transistor having one side connected to a power supply voltage terminal and receiving a drain voltage of the second PMOS transistor as a gate; A ninth NMOS transistor having one side connected to a drain end of the first PMOS transistor and a gate end connected to the other side of the sixth PMOS transistor; A tenth NMOS transistor connected between a power supply voltage terminal and the other side of the sixth PMOS transistor, and a gate end thereof connected to the other side of the eighth NMOS transistor; An eleventh NMOS transistor connected between the other side of the eighth NMOS transistor and a ground power supply terminal and receiving the bias voltage through a gate; And A twelfth NMOS transistor connected between the other side of the sixth PMOS transistor and a ground power supply terminal and receiving the bias voltage as a gate; And the other side of the fourth NMOS transistor and the other side of the ninth NMOS transistor are connected to each other. The method of claim 5, wherein the potential stabilization means, A thirteenth NMOS transistor connected between the other side of the fourth NMOS transistor and a ground power supply terminal, and a gate end thereof connected to the other side of the third NMOS transistor; And A fourteenth NMOS transistor connected between the other side of the ninth NMOS transistor and a ground power supply terminal, and a gate end thereof connected to the other side of the eighth NMOS transistor; Comparing device for a high speed operation comprising a. The method of claim 1, wherein the first output means, A third NMOS transistor connected between a power supply voltage terminal and a first output terminal for outputting the first output signal and to which a drain voltage of the first PMOS transistor is applied to a gate; And A fourth NMOS transistor connected between the first output terminal and a ground power supply terminal and receiving the bias voltage through a gate; The second output means, A fifth NMOS transistor connected between a power supply voltage terminal and a second output terminal for outputting the second output signal, and to which a drain voltage of the second PMOS transistor is applied to a gate; A sixth NMOS transistor connected between the second output terminal and a ground power supply terminal and receiving the bias voltage through a gate; Comparing device for a high speed operation comprising a. The method of claim 1, wherein the bias voltage supply means, A third PMOS transistor, a third and a fourth NMOS transistor, which are sequentially connected between a power supply voltage terminal and a ground power supply terminal, A gate terminal and a drain terminal of the third PMOS transistor are commonly connected; The gate terminal of the third NMOS transistor is connected to the gate terminal and the drain terminal of the third PMOS transistor connected in common, and the drain terminal and the gate terminal of the fourth NMOS transistor is configured for high speed operation, characterized in that for Comparator. The method of claim 1, wherein the second amplifying means, Capacitor-connected first and second NMOS transistors for coupling and transferring the first and second signals output from the storage means, respectively; First and second PMOS transistors connected to a power supply voltage terminal and receiving input signals coupled to the gates from the first and second NMOS transistors connected to the capacitors, respectively; Latch means for latching and outputting the first and second output signals in response to the latch signal; First feedback means for feedback operation in response to a drain voltage of the first PMOS transistor; Second feedback means for feedback operation in response to a drain voltage of the first PMOS transistor; Potential stabilization means connected to said first and second feedback means for stabilizing a potential of a signal; Bias voltage supply means connected between a power supply voltage terminal and a ground power supply terminal for supplying a constant bias voltage; And First and second output means for driving the first and second output signals in response to the drain voltage and the bias voltage of the first PMOS transistor Comparing device for high speed operation comprising a. The method of claim 9, wherein the latch means, A third NMOS transistor connected to the drain terminal of the first PMOS transistor and receiving the latch signal through a gate; And A fourth NMOS transistor connected to the drain terminal of the second PMOS transistor and receiving the latch signal through a gate; Comparing device for a high speed operation comprising a.