KR100632000B1 - Method for forming gate insulation layer of high voltage device - Google Patents

Abstract

A method for forming a gate insulating layer in a high-voltage device is provided to minimize the loss of an HLD(High pressure Low temperature Deposition) oxide layer by using a triple structure as the gate insulating layer. A first oxide layer(19) is formed on a semiconductor substrate(11) having an isolation layer(13) by using thermal wet oxidation processing. A second oxide layer(21) is formed on the first oxide layer by using HLD processing. A nitride layer(24) is formed on the second oxide layer. By patterning the nitride layer, the second oxide layer and the first oxide layer, a gate insulating layer(39) of triple structure is then formed.

Description

Method for forming gate insulation layer of high voltage device

1 is a photograph for explaining the conventional problem.

Figure 2 is a process cross-sectional view for explaining a method of forming a gate insulating film of another conventional high voltage device.

3A to 3I are cross-sectional views illustrating processes of forming a gate insulating film of a high voltage device according to a first embodiment of the present invention.

4A through 4G are cross-sectional views illustrating processes of forming a gate insulating film of a high voltage device according to a second exemplary embodiment of the present invention.

      The present invention relates to a method of manufacturing a high voltage device, and more particularly, to a method of forming a gate insulating film of a high voltage device capable of improving reliability in forming a gate insulating film in a high voltage device having a device isolation film by an STI process. It is about.

In the manufacture of high voltage MOSFETs using the LOCOS isolation method, the HUMP characteristic, which is the main characteristic when applying the isolation of the STI structure, is not generated. However, due to the development of process technology and increased IC integration, the STI technique is applied to the manufacture of logics of 0.25 μm or less, and therefore, a method for preventing Hump (HUMP) generation is needed.

According to the development of the technology, the following problems occur in the process of forming each gate insulating film due to the structural difference between the low voltage MOSFET and the high voltage MOSFET in the process of merging the high voltage MOSFET in addition to the basic logic manufacturing.

As the gate insulating film of the low voltage device, an oxide film by a thin thermal wet method of 40 kW or less is used. In this case, the thickness difference between the sidewall of the device isolation film and the flat active region adjacent thereto is very thin due to the deposition of a very thin oxide film. Is generated.

As the gate insulating film of the high voltage device, an oxide film by a wet oxidation method has been used. Although the thickness of the deposited film is different depending on the operating voltage condition that determines the high voltage device, typically a film of hundreds to thousands of kHz should be formed.
However, unlike the low voltage device to which the very thin oxide film is applied, when the oxide film by the thermal wet method is used as the gate insulating film of the high voltage device, the device characteristics of the low voltage device region are changed due to silicon loss, or as shown in FIG. Similarly, the oxide film on the sidewall corner portion of the device isolation film grows thinner than the flat active region, and at the same time, the stress of the oxide film or the substrate is generated at the corner of the device isolation film due to excessive oxide film formation, thereby degrading the reliability of the device.

Thus, in order to improve the abnormal oxidation phenomenon of the corner portion of the device isolation film, as shown in FIG. 2, the first oxide film 5 by the wet oxidation method is formed as a gate insulating film of another conventional high voltage device, and thereon. A double film structure in which a high pressure low temperature deposition (HLD) oxide film 6 was deposited and annealed was used. Here, the annealing process is to prevent excessive loss of the HLD oxide film 6 by pre-cleaning or the like proceeding after the formation of the HLD oxide film 6, and proceeds at a high temperature for a long time.
In FIG. 1, reference numeral 1 denotes a semiconductor substrate, 2 denotes an isolation layer, 7 denotes a double-layered gate insulating layer, and 8 denotes a gate electrode. Unexplained I denotes a low voltage element region, III denotes a high voltage element region, and II denotes a medium voltage element region therebetween.

However, drawbacks of the leakage characteristics of the device, such as the stress of the device isolation film already formed by the annealing treatment for a long time at such a high temperature has been highlighted. Therefore, it is necessary to remove the abnormal structure of the gate insulating film for the high voltage device and to optimize the processing conditions for the high temperature process.

Accordingly, the present invention has been made to solve the above conventional problems, an object of the present invention is to use a high temperature annealing process to minimize the loss of the HLD oxide film used as the gate insulating film of the high voltage device high voltage device A method of forming a gate insulating film is provided.

In order to achieve the above object, the present invention provides a method for forming a gate insulating film of a high voltage device having a device isolation film by an STI process, the method comprising: forming a first oxide film by a wet oxidation method on a semiconductor substrate; Forming a second oxide film by an HLD method on the first oxide film, forming a nitride film on the second oxide film, and patterning the nitride film, the second oxide film, and the first oxide film. A method of forming a gate insulating film is provided.

The first oxide film is formed by wet oxidation at a temperature of 800 ~ 900 ℃.

The first oxide film is formed to a thickness of 150Å.

The second oxide film is formed to be 400 Å thick.

In addition, in order to achieve the above object, the present invention, in the method of forming a gate insulating film of a high voltage device equipped with a device isolation film by the STI process, the step of forming a first oxide film by a wet oxidation method on a semiconductor substrate; Forming a second oxide film by an HLD method on the first oxide film, forming a polysilicon film on the second oxide film, and wet oxidizing all of the polycrystalline silicon film to form a sacrificial oxide film; And patterning the sacrificial oxide layer, the second oxide layer, and the first oxide layer.

        (Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3I are cross-sectional views illustrating processes for forming a gate insulating film of a high voltage device according to a first exemplary embodiment of the present invention.

As shown in FIG. 3A, a semiconductor substrate 11 having a low voltage device region IV, a high voltage device region VI, and a medium voltage device region V therebetween is provided. Subsequently, the device isolation film 13 is formed on the substrate 11 through a well-known STI process, and then a well forming ion implantation process is performed to each of the high voltage P-type wells (HPW) 15 in the high voltage device region VI. ) And a high voltage N-type well (HNW) 17. Thereafter, a first oxide film 19 is formed on the entire surface of the substrate including the high voltage P type well (HPW) 15 and the high voltage N type well (HNW) 17 by a wet oxidation method. At this time, the first oxide film 19 is wet oxidized at a temperature of 800 ~ 900 ℃ to form a thickness of 150Å.

As shown in FIG. 3B, the second oxide film 21 is formed on the first oxide film 19 by the HLD method. At this time, the second oxide film 21 is formed to be 400 Å or more in thickness, and annealing is performed after deposition.

As shown in FIG. 3C, the nitride film 24 is formed on the second oxide film 21.

As shown in FIG. 3D, the nitride film 24, the second oxide film 21, and the first oxide film 19 are selectively etched using the first photoresist pattern 41 to exclude the high voltage device region VI. Open regions (IV) and (V).

As shown in FIG. 3E, after removing the first photoresist pattern, a thin third oxide film 25 is formed on the region (IV) (V). Subsequently, well forming ion implantation is performed in regions (IV) and (V) to form respective P wells 27, 31 and N wells 29, 33.

As shown in FIG. 3F, after the low voltage device region IV is selectively opened using the second photoresist pattern 43, the third oxide film is etched to expose the substrate surface. Reference numeral 26, which is not described in FIG. 3F, shows a third oxide film remaining in the intermediate voltage device region V after etching.

As shown in FIG. 3G, after the second photoresist pattern is removed, a fourth oxide film 35 that is relatively thinner than the third oxide film is formed in the low voltage device region IV.

As shown in FIG. 3H, a polysilicon film 37 for forming a gate electrode is formed on the entire surface of the substrate including the fourth oxide film 35.

As shown in FIG. 3I, the polysilicon layer 37, the fourth oxide layer 35, the third oxide layer 26, the nitride layer 24, the second oxide layer 21, and the first oxide layer 19 are etched. Thus, the gate insulating film 39 and the gate electrode 38 are formed in each region. At this time, in the high voltage device region VI, the gate insulating film 39 is formed of a triple stacked structure of the first oxide film 19 by the wet oxidation method and the second oxide film 21 and the nitride film 24 by the HLD method. .

4A through 4G are cross-sectional views illustrating processes of forming a gate insulating film of a high voltage device according to a second exemplary embodiment of the present invention.

As shown in FIG. 4A, a semiconductor substrate 51 having a low voltage device region IV, a high voltage device region VI, and a medium voltage device region V therebetween is provided. Subsequently, the device isolation film 53 is formed on the substrate 51 through a well-known STI process, and then a well-forming ion implantation process is performed to each of the high voltage P-type wells HPW 55 in the high voltage device region VI. ) And a high voltage N-type well (HNW) 57. Then, a first oxide film 59 is formed on the entire surface of the substrate including the high voltage P well (HPW) 55 and the high voltage N type well (HNW) 57 by a wet oxidation method. At this time, the first oxide film 59 is thermally wet oxidized at a temperature of 800 to 900 ° C. to form a thickness of 150 μs. Subsequently, after forming the second oxide film 61 by the HLD method on the first oxide film 59, a polysilicon film 63 is formed on the second oxide film 61 to a thickness of 100 Å.

As shown in FIG. 4B, the films are selectively etched using the first photoresist pattern 81 as a mask to open (IV) (V) regions. In FIG. 4B, reference numeral 60 denotes a first oxide film remaining after etching, reference numeral 62 denotes a second oxide film remaining after etching, and reference numeral 64 denotes a polycrystalline silicon film remaining after etching.

As shown in FIG. 4C, after the first photoresist layer pattern is removed, a thermal wet oxidation process is performed on the regions (IV) (V) to form a thin third oxide layer 65. At this time, the polysilicon film is completely sacrificially oxidized while the third oxide film 65 is formed.

On the other hand, reference numeral 64a, which is not described in Figure 4c represents a sacrificial oxide film.

As shown in FIG. 4D, the third oxide film in region (IV) is selectively removed using the second photosensitive film pattern 83 as a mask. Reference numeral 66, which is not described in FIG. 4D, indicates the third oxide film remaining in the region (V).

As shown in FIG. 4E, after the second photoresist pattern is removed, a fourth oxide film 67 is formed in the region IV, which is relatively thinner than the third oxide film. Thereafter, well formation ion implantation is performed in regions (IV) and (V) to form respective P wells PW and N wells NW.

As shown in FIG. 4F, a polysilicon film 69 for forming a gate electrode is formed on the entire surface of the substrate including the fourth oxide film 67.

As shown in FIG. 4G, the films are etched to form respective gate insulating films and gate electrodes. At this time, in the high voltage device region VI, the gate insulating film 71 has a triple stacked structure of the first oxide film-HLD method by the second oxide film-nitride film by the wet oxidation method.

In the second embodiment of the present invention, the thermal wet oxide film has a very low loss due to the post-treatment process, wherein the polycrystalline silicon film is formed on the HLD oxide film, and the entire sacrificial oxide film is formed by the thermal wet oxidation method. will be. Therefore, since the sacrificial oxide film serves to block the HDL oxide film, it is possible to minimize the loss of the HLD oxide film due to subsequent back and forth cleaning.

As described above, since the thermal wet oxide film-HLD oxide film-nitride film is sequentially formed as the gate insulating film according to the present invention, since the nitride film serves as a barrier layer, the loss of the HLD oxide film can be minimized during the subsequent back and forth cleaning process. Therefore, the thickness of the gate insulating film can be easily controlled to improve the reliability of the device.

In addition, by forming a wet oxide film-HLD oxide film-sacrificial oxide film (sacred-oxidized polysilicon film) as a gate insulating film according to the present invention, the sacrificial oxide film blocks HDL oxide film, so that the HLD oxide film by the back and forth cleaning that is subsequently performed Loss can be minimized. Therefore, a highly reliable gate insulating film of a high voltage device can be formed and the existing stress problem can be solved.

Claims (5)

In the method of forming a gate insulating film of a high voltage device provided with an isolation film by the STI process, Forming a first oxide film on the semiconductor substrate by a wet oxidation method; Forming a second oxide film by an HLD method on the first oxide film; Forming a nitride film on the second oxide film; And Patterning the nitride film, the second oxide film, and the first oxide film; A gate insulating film forming method of a high voltage device comprising a. The method of claim 1, wherein the first oxide film is wet oxidized at a temperature of 800 ° C. to 900 ° C. 6. The method of claim 1, wherein the first oxide film is formed to a thickness of 150 kHz. 2. The method of claim 1, wherein the second oxide film is formed to a thickness of 400 kHz. In the method of forming a gate insulating film of a high voltage device provided with an isolation film by the STI process, Forming a first oxide film on the semiconductor substrate by a wet oxidation method; Forming a second oxide film by an HLD method on the first oxide film; Forming a polysilicon film on the second oxide film; Wet oxidizing all of the polysilicon films to form a sacrificial oxide film; Patterning the sacrificial oxide film, the second oxide film, and the first oxide film; A gate insulating film forming method of a high voltage device comprising a.

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