KR100628086B1 - Apparatus and Method of address generation for DSP - Google Patents

Abstract

The present invention relates to address generation of a DSP. The present invention provides an address register for storing a current memory address, a bank size register for storing a bank size of the memory, an address switching register for switching addresses between the last channel and the first channel of all channels, and a channel size value. And a mux for selectively outputting one of a value stored in the bank size register or a value stored in an address change register according to a comparison with a current channel number, and an adder for adding the stored value of the address register and an output value of the mux. It provides an address generator of the DSP is configured. Therefore, according to the present invention, since an address required for data access is generated through the address generation device, an additional address calculation cycle is not required, and thus the interleaved data can be accessed without wasting cycles.

Data Access, Address Generator, DSP, Bank Size, Channel Size

Description

Apparatus and Method of address generation for DSP

1 illustrates a memory structure in which interleaved data is stored for each channel in a general audio encoder / decoder

2 is a flowchart illustrating a data access method according to the prior art.

3 is a diagram illustrating an address generator for accessing interleaved data according to the present invention;

4 is a flowchart illustrating an address generation method according to the present invention.

-Explanation of symbols for the main parts of the drawings-

10: address register 20: bank size register

30: address switching register 40: mux

50: adder

The present invention relates to address generation, and more particularly, to an apparatus and method for generating an address for multi-channel data access in a DSP.

Digital signal processing (DSP) refers to a processor for digital signal processing. Therefore, it uses various data addressing modes that are distinct from the general processor.

The mode includes an address increment mode, an address decrement mode, an address increment by index register mode, and an address decrement by index register. mode, circular addressing mode, reverse mode, etc., which are applied to all or specific algorithm implementations.

In general, in the case of an audio encoder / decoder, input / output data are interleaved for each channel. These data interleaved per channel or per specific number of channels are stored or output for each channel, which will be described below with reference to the accompanying drawings.

FIG. 1 illustrates a memory structure in which interleaved data is stored for each channel in a general audio encoder / decoder.

As shown in FIG. 1, data is divided into channels for each channel in the memory, namely, right and left channels for two channels, and for Right, Left, Surround Right, Surround Left, Center, and Low Freq. Each channel is interleaved, stored, and output. In this case, the memory is divided into banks for each channel and used.

In the interleaved and stored memory as described above, in order to access (access, read or write) the interleaved data, an address assignment operation of data is required.

This will be described with reference to the accompanying FIG. 2, which is a flowchart illustrating a data access method according to the prior art.

First, referring to the case of accessing the interleaved data of two channels, as shown in FIG. 2, a step of calculating an address for the left channel is needed, and accessing the data to the address calculated according to the above steps, and the remaining right channel The same is done for.

In addition, for 5.1 channels, an operation for calculating an address must first be performed for each channel, which takes approximately 2 to 3 cycles and as many as 4 to 5 cycles for each address calculation step.

In this case, implementation according to the Advanced Television System Committee (ATSC) standard will assign 48,000 samples per second in the above manner, and therefore only 9 to 13 Million Instructions Per Second (MIPS), and as many as 30 MIPS, in this address allocation portion. You will use the degree.

As a result, dozens of MIPS are used only for address assignment, which is a waste of cycles. Therefore, the development of a method for assigning addresses without wasting cycles in accessing interleaved data is an important problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to propose an efficient address generation apparatus and method for accessing interleaved and stored data.

In order to achieve the above object, the present invention provides an address register for storing a current memory address, a bank size register for storing a bank size of the memory, and an address switching for address switching between the last channel and the first channel of all channels. A mux for receiving a register and a channel size value and selectively outputting one of a value stored in the bank size register or a value stored in an address change register according to a comparison with a current channel number; It provides an address generator of a DSP that includes an adder that adds an output value.

The address change register stores a value obtained by subtracting 1 from a channel size and a product of a bank size.

The present invention provides a method of storing a channel size value and a bank size value, outputting an address increased by the bank size every time data access is performed to an initially set address, and performing data access by the channel size. After that, the present invention provides a method for generating an address of a DSP, which includes outputting an address increased by one word from the initially set address.

Therefore, according to the present invention, since an address required for data access is generated through the address generation device, an additional address calculation cycle is not required, and thus the interleaved data can be accessed without wasting cycles.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described.

In addition, the term used in the present invention was selected a general term that is widely used at present, but according to the emergence of a new technology, the term that the applicant deemed most appropriate in the present invention was arbitrarily used, and the meaning of the term in the corresponding description. It will be explained clearly. Therefore, in the understanding of the present invention, it is intended that the present invention should be understood as the meaning of terms rather than simple names of terms.

3 is a diagram illustrating an address generation apparatus for accessing interleaved data according to the present invention.

As shown in FIG. 3, the address generator according to the present invention includes an address register 10 in which a current memory address is stored, a bank size register 20 in which a bank size of a memory is stored, A value stored in the bank size register 20 or the last channel and the first channel according to a comparison between the register 30 and the channel size value for receiving an address between the last channel and the first channel among all the channels. A mux 40 for selectively outputting one of the values stored in the inter-channel address switching register 30, and an adder for adding the value stored in the address register 10 and the output value of the mux 40. It consists of 50.

The operation relationship of the address generation device according to the present invention configured as described above is as follows. In this case, for convenience of description, it will be described with reference to the accompanying Figure 1 showing the structure of the memory.

1 illustrates a structure of a memory in which data having 5.1 channels is stored. The bank size is 20h and the total channel size is 6, for example. In this case, the bank size indicates how many intervals the interleaved data is aligned.

Initially, address 0 indicating the address of the first channel is stored in the address register 10. The bank size register 20 also stores 20h as a bank size. A value according to the following expression is stored in the register 30 for address switching between the next last channel and the first channel.

 [1-{(channel size-1) * bank size}]

In the above formula, the first address of the last channel is a value obtained by subtracting 1 from the channel size and the bank size. The value obtained by subtracting the current address located in the last channel and adding 1 again is calculated according to a calculation process to be described later. It will be the next address of the first channel.

Therefore, assuming that the channel size is 6 and the bank size is 20h, the value of -99h will be stored in the register 30 for address switching between the last channel and the first channel.

Thereafter, the address of the next channel is transmitted to the adder 50 through the mux 40 and the value stored in the bank size register 20 is added to the adder 50 and stored in the address register 10. That is, 0h, which is the address of the current channel, and 20h stored in the bank size register 20 are added to make the address of the next channel 20h.

In this case, the mux 40 compares the current channel number with the channel size value and outputs the value stored in the bank size register 20 to the adder 50 when it is not the same.

In other words, the address stored in the bank size register 20 is outputted until the current channel number becomes 6, which is the channel size.

When the current channel number is 6, which is the channel size, the value stored in the register 30 for address switching between the last channel and the first channel is outputted. To be created.

Therefore, when the current channel address is 100h in the memory as shown in FIG. 1, the -99h value stored in the register 30 is output to the adder 500 through the mux 40, and the next address is added by adding 100h and -99h. 1h of the first channel.

In other words, when the first data is accessed, the address is automatically increased by the bank size to point to the corresponding address of the next bank. When this operation is performed by the channel size, the address is automatically pointed to the next word of the first data. Will be. This step is repeated by bank size.

Referring to Figure 4 attached to the address generation method according to the present invention in more detail as follows.

4 is a flowchart illustrating an address generation method according to the present invention, in which K denotes a channel number, A denotes a current address position, and I denotes a repetition number.

As shown in Fig. 4, initially, the channel number K and the repetition number I are set to 1, and the current address position will be 0. (S10)

Accordingly, the current address will be 0, which is an A value (S20), and a data access process is performed according to the set address.

Thereafter, it is checked whether the K value, which is the channel number, is equal to the channel size value, and if it is not the same, the channel number K value is increased by 1 and the bank size is added to the current address A.

Therefore, the next address becomes the current address A plus the bank size, and the address is generated by repeating the above steps.

In this manner, if the channel number K becomes equal to the channel size value, the current address is located in the last channel, and a [A- (k-1) * bank size] operation is performed.

After checking that the number of repetitions is equal to the bank size after performing the operation (S70), the current address and the number of repetitions on which the operation is performed are each added by one (S80). The next address becomes the current address, and the number of repetitions is repeated by the bank size.

That is, the above operation is automatically performed in the address generation apparatus according to the present invention to access the interleaved data without the need for a separate address calculation cycle.

The present invention is not limited to the above-described embodiments, and as can be seen in the appended claims, modifications can be made by those skilled in the art to which the invention pertains, and such modifications are within the scope of the present invention.

The address generation apparatus and method of the DSP according to the present invention described above can generate an address required for data access through the address generation apparatus, thereby eliminating the need for a separate address calculation cycle, thereby allowing access to interleaved data without wasting cycles. There is.

Claims (3)

An address register that stores a current memory address; A bank size register in which a bank size of the memory is stored; An address translation register for address switching between the last channel and the first channel of all channels; A mux for receiving a channel size value and selectively outputting one of a value stored in the bank size register or a value stored in an address change register according to a comparison with a current channel number; And, And an adder for adding the stored value of the address register and the output value of the mux. The method of claim 1, And a value obtained by subtracting 1 from a channel size and a value obtained by multiplying a bank size by 1 is stored in the address conversion register. Storing a channel size value and a bank size value; Outputting an address increased by the bank size every time data access is performed to an initially set address; And outputting an address increased by one word from the initially set address after performing data access by the channel size.

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